Patents Issued in September 30, 2014
  • Patent number: 8847604
    Abstract: Implementations are presented herein that include a test circuit and a reference circuit.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: September 30, 2014
    Assignee: Infineon Technologies AG
    Inventors: Thomas Baumann, Georg Georgakos, Christian Pacha, Anselme Urlick Tchegho Kamgaing
  • Patent number: 8847605
    Abstract: A connection diagnostic apparatus for a ground fault detector including an oscillator connected via a coupling capacitor to an electric circuit with a first connection line and a second connection line, and a voltage detector for detecting a voltage value between the oscillator and the coupling capacitor is provided with a first relay and a second relay provided in the first connection line and the second connection line, and a programmable controller. The programmable controller determines a connected state of the ground fault detector based on a change amount of a voltage value detected by the voltage detector when the first relay is turned on or off and determines the connected state of the ground fault detector based on a change amount of a voltage value detected by the voltage detector when the second relay is turned on or off.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: September 30, 2014
    Assignee: Nissan Motor Co., Ltd.
    Inventor: Tsuyoshi Morita
  • Patent number: 8847606
    Abstract: A method for assessing insulation deterioration in a live underground power cable may include, in one embodiment, attaching a coupling device to a live underground power cable and using the coupling device to couple a test signal onto the power cable. The power cable may carry a normal AC power signal at a first frequency, while the test signal may have a second frequency different from the first frequency. The test signal may be detected after it has traveled a distance along the power cable. It may then be analyzed to determine a change in velocity and/or attenuation of the test signal as a function of the normal AC power signal. The severity of water trees in the power cable may be inferred based on the magnitude of the change.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: September 30, 2014
    Assignee: University of California
    Inventors: Richard M. White, Igor Paprotny, Augusto Giovanni Gonzalez
  • Patent number: 8847607
    Abstract: A device is provided for protecting an electronic payment terminal that includes an electronic printed circuit board and a casing. The device includes at least one capacitive detector in a volume formed by a first ground plane of the printed circuit and a second ground plane positioned on an internal surface of the casing, the at least one capacitive detector being configured to deliver a reference capacitance. A capacitive measurement microprocessor detects a variation of capacitance of the at least one capacitive detector. A transmitter transmits the variation when an absolute value of a difference between the reference capacitance and the measured capacitance exceeds a predetermined threshold.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: September 30, 2014
    Assignee: Compagnie Industrielle et Financiere d'Ingenierie “Ingenico”
    Inventors: Laurent Rossi, Bernard Schang
  • Patent number: 8847608
    Abstract: A non-destructive on-line system for detecting a presence of a material in a sample of a substance, including: an MRI device; a flow conduit encompassed by the tunable RF coil of the MRI device and having an input duct and an output duct; a flow of the sample through the flow conduit; a signal detector for detecting frequency-dependent output signals from the MRI device as a function of a frequency variation of the RF tunable coil within a frequency range of an RF resonant frequency of a standard sample of the substance, and a processing unit.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: September 30, 2014
    Inventor: Uri Rapoport
  • Patent number: 8847609
    Abstract: A method of obtaining a material property of a pavement material from a microwave field generally includes generating a microwave frequency electromagnetic field of a first mode about the pavement material. The frequency response of the pavement material in the electromagnetic field can be measured, such as by a network analyzer. The measurement of the frequency response permits correlating the frequency response to a material property of the pavement material sample, such as the density. A method of correcting for the roughness of a pavement material divides the pavement into a shallow layer and a deep layer. Two planar microwave circuits measure the permittivity of the shallow and deep layer. The permittivities are correlated to correct for roughness. An apparatus for obtaining the density of a pavement sample includes a microwave circuit and a network analyzer. The network analyzer measures the frequency response to determine the density of the pavement material.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: September 30, 2014
    Assignee: Troxler Electronic Laboratories, Inc.
    Inventor: Robert Ernest Troxler
  • Patent number: 8847610
    Abstract: The invention relates to a system for transferring information closely connected to an object. The system is characterized in that it comprises a conductor arrangement, which comprises a number of conductor components, that forms an electromagnetic field, as well as a transmitter associated with the object. The aforementioned transmitter is arranged to connect by means of an electromagnetic field to the conductor arrangement and also to modulate the measuring signal formed by means of the field.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: September 30, 2014
    Assignee: Elsi Technologies Oy
    Inventor: Henry Rimminen
  • Patent number: 8847611
    Abstract: A rotary position sensor is provided that includes a sensing disc having an N-fold rotation symmetry and capacitive sensing pads arranged in an array pattern, where the array pattern has at least 4N-fold rotation symmetry, where N?2, a scale disc disposed opposite the sensing disc, where the scale disc includes a pattern of conductive pads that have a sinusoidal-shape, where the pattern of sinusoidal-shaped conductive pads produce four sinusoidal capacitance waveforms in quadrature phase with the capacitive sensing pads as the sensing disc and the scale disc are rotated relative to one another to provide angular position information. to provide angular position information. This is achieved by making the overlapping area of the of the capacitive sensing pads change in a sinusoidal fashion with rotation.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: September 30, 2014
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: John V Ulmen, Barrett E. Heyneman
  • Patent number: 8847612
    Abstract: In one embodiment, a method includes restricting current flow between a node of a touch sensor and each of a drive system of the touch sensor, a sense system of the touch sensor, and a test system of the touch sensor. The method further includes capacitively coupling the drive system to the sense system through the test system. The method further includes using at least the drive system and the test system, inducing a charge on the sense system. The method further includes measuring the induced charge on the sense system. The method further includes making a pass or fail determination for at least a portion of the touch sensor based at least in part on the measured induced charge.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: September 30, 2014
    Assignee: Atmel Corporation
    Inventor: Carl Olof Fredrik Jonsson
  • Patent number: 8847613
    Abstract: A capacitive sensing system (1) which includes an electrical charge providing unit (4) like an electret foil for providing a permanent electrical charge at a sensing site (6) of the object (3) and a capacitive sensor (2) including a sensing electrode (5) for generating a sensing signal by capacitively sensing the object (3) at the sensing site (6) of the object (3). By providing a permanent electrical charge at the sensing site (6) of the object (3), the bias between the object (3) and the sensing electrode (5) of the capacitive sensor (2) is intentionally preferentially made large, thereby increasing the sensitivity towards mechanical motions. The resulting sensing signal substantially caused by these mechanical motions between the object (3) and the sensing electrode (5) is generally larger than a signal generated substantially by an electrophysiological field.
    Type: Grant
    Filed: May 31, 2010
    Date of Patent: September 30, 2014
    Assignee: Koninklijke Philips N.V.
    Inventors: Mohammed Meftah, Bastiaan Feddes
  • Patent number: 8847614
    Abstract: A combiner box capable of monitoring energy output from a photovoltaic system and having improved troubleshooting functionality, the ability to independently verify utility charges, and a mechanism for reducing incorrect readings of energy output and consumption due to noise and interference.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: September 30, 2014
    Assignee: E Gear LLC
    Inventors: Christopher Robert DeBone, Steven Peter Godmere
  • Patent number: 8847615
    Abstract: A method, apparatus and system for integrated circuit testing, wherein a plural number of devices under test (DUTs) and a plural number of comparison apparatuses are placed on a common substrate. The DUTs all operate under the same input stimulation and each produce its own operation output. The outputs are compared by the comparison apparatuses to generate comparison characteristics which are used to filter-out the failed devices. This invention lowers the testing cost, shortens time to product mass-production, and lowers the miss rate of failed devices passed as good ones.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: September 30, 2014
    Assignee: Shanghai Xinhao (Bravechips) Micro Electronics Co. Ltd.
    Inventors: Kenneth ChengHao Lin, Hongxi Geng, Haoqi Ren, Bingchun Zhang, Changchun Zhen
  • Patent number: 8847616
    Abstract: A measurement apparatus is disclosed. The measurement apparatus includes a lid configured to be removably affixed to a microcircuit case. One or more penetrations through the lid allow insertion of a signal-conducting probe. The probe is removably affixed to the lid at the site of the penetration. The probe includes a central conductive pin. The central conductive pin transmits to a connection outside the case a radio-frequency signal inductively received from a source inside the case. The probe also includes a dielectric region radially surrounding a portion of the central conductive pin, and a grounded outer conductive housing radially surrounding the dielectric region and electrically isolated from the central conductive pin by the dielectric region.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: September 30, 2014
    Assignee: National Instruments Corporation
    Inventor: Ron Jay Barnett
  • Patent number: 8847617
    Abstract: Electronic device structures such as structures containing antennas, connectors, welds, electronic device components, conductive housing structures, and other structures can be tested for faults using a non-contact test system. The test system may include a vector network analyzer or other test unit that generates radio-frequency tests signals in a range of frequencies. The radio-frequency test signals may be transmitted to electronic device structures under test using an antenna probe that has one or more test antennas. The antenna probe may receive corresponding radio-frequency signals. The transmitted and received radio-frequency test signals may be analyzed to determine whether the electronic device structures under test contain a fault.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: September 30, 2014
    Assignee: Apple Inc.
    Inventors: Joshua G. Nickel, Jonathan P. G. Gavin
  • Patent number: 8847618
    Abstract: A circuit board tester and method that precisely aligns the probe plate and circuit board is disclosed. With a circuit board and probe plate mounting within a housing having a top and bottom, hinged together, at closure there may be slight misalignments of the two. By making one of the two plates floating, or laterally slideable with respect to each other, it is possible to make final alignment at closure. One of the two plates can be provided with a pin and the other with a pin receiving alignment block. With the lateral slideability, the pin and block can insure proper probe alignment. Additional systems for correcting misaligned pins or blocks are also disclosed.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: September 30, 2014
    Assignee: Circuit Check, Inc.
    Inventors: Gregory J. Michalko, Stuart K. Eickhoff, Jon A. Hample, Russell G. Carter
  • Patent number: 8847619
    Abstract: A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: September 30, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Ebrahim H Hargan, Layne Bunker, Dragos Dimitriu, Gregory King
  • Patent number: 8847620
    Abstract: A missing stator slot wedge in an electrical machine can be detected by analyzing a current spectrum of the machine in a high frequency area. A current spectrum is provided from a current measurement, and values of the current spectrum in the high frequency area used to determine whether a stator slot wedge is missing or not. The conclusion can be based on values of a relative current amplitude IdB or on presence of certain harmonics in the high frequency area.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: September 30, 2014
    Assignee: ABB Research Ltd.
    Inventors: Cajetan Pinto, Pedro Rodriguez
  • Patent number: 8847621
    Abstract: A circuit and methods for mitigating radiation-induced Single Event Effects (SEE) in Silicon-on-Insulator (SOI) Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits are presented. A primary logic output is generated from a primary logic gate in response to an input. A redundant logic output is generated from a redundant logic gate that duplicates the primary logic output in response to the input if an SEE is not present. An interleaved C-gate output is generated from an interleaved C-gate that emulates an inverter output when the primary logic output and the redundant logic output match, and does not changes its output when the primary logic output and the redundant logic output do not match during the SEE.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: September 30, 2014
    Assignee: The Boeing Company
    Inventors: Ethan Cannon, Salim Rabaa, Josh Mackler
  • Patent number: 8847622
    Abstract: A method for testing a set of circuitry in an integrated circuit (IC) is described. The IC includes multiple configurable circuits for configurably performing multiple operations. The method configures the IC to operate in a user mode with a set of test paths that satisfies a set of evaluation criteria. Each test path includes a controllable storage element for controllably storing a signal that the storage element receives. The method operates the IC in user mode. The method reads the values stored in the storage elements to determine whether the set of circuitry is operating within specified performance limits.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: September 30, 2014
    Assignee: Tabula, Inc.
    Inventor: Brian Fox
  • Patent number: 8847623
    Abstract: A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: September 30, 2014
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Bruce Millar
  • Patent number: 8847624
    Abstract: Operation of a programmable circuit is described. A circuit including a plurality of multiplexers may be used to perform at least one operation on a plurality of signals. The at least one operation may be performed by the multiplexers using a select line coupled to or shared by the multiplexers. Each input of the circuit may couple to a respective output of a plurality of logic elements. As such, the circuit may be used to perform at least one operation on signals supplied from a plurality of logic elements, thereby expanding the functionality of at least one logic element coupled to the circuit and/or increasing the number of logic elements and other resources available for implementing user designs or performing other functions.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: September 30, 2014
    Assignee: Altera Corporation
    Inventor: Valavan Manohararajah
  • Patent number: 8847625
    Abstract: A multi-valued logic (MVL) circuit includes a MVL clock generator that generates a MVL clock signal having three or more ith MVL levels, a single MVL clock signal distribution network connected to the MVL clock generator, and three or more ith MVL selection circuits connected to the single MVL clock signal distribution network where i=0 to N and N>=3. Each ith MVL selection circuit corresponds to a specified ith MVL level. The ith MVL selection circuit outputs an ith binary clock signal having: (a) a first logic level whenever the MVL clock signal is equal to the ith MVL level and the ith data input receives the first logic level, (b) a second logic level whenever the MVL clock signal is equal to the ith MVL level and the ith data input receives the second logic level, and (c) a previous logic level of the ith binary clock signal whenever the MVL clock signal is not equal to the ith MVL level.
    Type: Grant
    Filed: February 16, 2013
    Date of Patent: September 30, 2014
    Assignee: Southern Methodist University
    Inventors: Mitchell Aaron Thornton, Rohit Menon
  • Patent number: 8847626
    Abstract: A circuit includes first and second bidirectional clock networks and first and second clock signal generation circuits. A first multiplexer circuit is configurable to provide a first clock signal from a first pin to the first bidirectional clock network. A second multiplexer circuit is configurable to provide the first clock signal from the first bidirectional clock network to the second bidirectional clock network. Third multiplexer circuits are configurable to provide the first clock signal from the second bidirectional clock network to the first and the second clock signal generation circuits.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 30, 2014
    Assignee: Altera Corporation
    Inventors: Yan Chong, Warren Nordyke, Pradeep Nagarajan, James Kimble Lin, Weiqi Ding
  • Patent number: 8847627
    Abstract: A semiconductor device includes a first transistor, a second transistor, a first transistor group, and a second transistor group. The first transistor group includes a third transistor, a fourth transistor, and four terminals. The second transistor group includes fifth to eighth transistors and four terminals. The first transistor, the third transistor, the sixth transistor, and the eighth transistor are n-channel transistors, and the second transistor, the fourth transistor, the fifth transistor, and the seventh transistor are p-channel transistors.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: September 30, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuya Ohnuki
  • Patent number: 8847628
    Abstract: Integrated circuit devices may utilize automatic methods for adjusting the tail currents of current mode logic (CML) cells, which compensate for variations in process corners and thereby enable reliable operation of high performance circuits, such as frequency synthesizers. An integrated circuit may include a current mode logic (CML) circuit responsive to at least one input signal and a variable current source electrically coupled to the CML circuit. This variable current source can be configured to sink (or source) a first current from (or to) the CML circuit in response to a control signal. A control circuit may also be provided, which is configured to generate the control signal in response to a process corner indication signal. This process corner indication signal, which may be generated by a process corner detection circuit, preferably has a magnitude that estimates a relative speed of a process corner associated with the integrated circuit device.
    Type: Grant
    Filed: September 29, 2012
    Date of Patent: September 30, 2014
    Assignee: Integrated Device Technology inc.
    Inventors: Minhui Yan, Chien-Chen Chen, Harmeet Bhugra
  • Patent number: 8847629
    Abstract: The invention relates to a low leakage switch having an input node for receiving an input voltage and an output node for providing an output voltage. The low leakage switch comprises a main sampling transistor the backgate voltage of which is biased through other transistors, and wherein the control gate of the main sampling transistor is controlled through a second control signal and the control gates of the other transistors are controlled through a first control signal, wherein the electronic device is further configured to activate the other transistor for adjusting the backgate voltage of the main sampling transistor through the first control signal before activating the main sampling transistor for sampling the input voltage on a main sampling capacitor through the second control signal.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: September 30, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Aymen Landoulsi, Matthias Arnold
  • Patent number: 8847630
    Abstract: A driver circuit is provided that receives an ON or OFF logic control signal and further has: an output arranged to be connected to a load; a power switch, having a control terminal with a first current terminal connected to a first power supply and a second current terminal arranged to be connected to the output to drive the load; a control circuit of a first type arranged between the control terminal of the power switch and a second power supply; and a control circuit of a second type, arranged to couple the control terminal of the power switch to the first power supply when the control signal is in the OFF state.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: September 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mohammed Mansri, Kamel Abouda, Ahmed Hamada
  • Patent number: 8847631
    Abstract: A gate drive circuit includes an insulated gate semiconductor switch. A controlled current source is connected to the semiconductor switch gate terminal to provide a gate drive circuit that is responsive to recycled gate charge corresponding to an internal gate capacitance of the insulated gate semiconductor switch.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: September 30, 2014
    Assignee: General Electric Company
    Inventors: Fengfeng Tao, Seyed Gholamali Saddoughi, John Thomas Herbon
  • Patent number: 8847632
    Abstract: Provided is a semiconductor device with an output circuit in which a variation of a common voltage is suppressed in an idling mode and in a normal mode. The output circuit provided in the semiconductor device includes a first termination resistor and a second termination resistor and a drive circuit which flows current through the termination resistors. The output circuit is configured so as to be able to adjust the value of current which flows through the first termination resistor and the second termination resistor or the value of resistance of the first termination resistor and the second termination resistor.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: September 30, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Shigeyuki Suzuki, Masato Suzuki
  • Patent number: 8847633
    Abstract: Described is an integrated circuit (IC) which comprises: a first driver having stacked devices, the first driver operable on a first power supply and a first ground supply, the first driver to receive an input signal with a signal swing according to a second power supply and a second ground supply, the second power supply having a voltage level lower than a voltage level of the first power supply, and the second ground supply having a voltage level higher than a voltage level of the first ground supply; a second driver coupled to the first driver, the second driver operable on the second power supply and the second ground supply; and a pair of by-pass devices coupled to the first and second drivers, the pair of by-pass devices to provide the second power supply and the second ground supply according to an output of the first driver.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: September 30, 2014
    Assignee: Intel Corporation
    Inventors: Jaydeep P. Kulkami, Dinesh Somasekhar
  • Patent number: 8847634
    Abstract: A high-speed unity-gain input buffer steers the current that flows down a first path to an output node, and down a second path in response to an analog input signal. The current that flows down the second path is mirrored to sink a current out of the output node.
    Type: Grant
    Filed: May 4, 2013
    Date of Patent: September 30, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Bumha Lee, Satoshi Sakurai, Sing W. Chin
  • Patent number: 8847635
    Abstract: An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and includes a reference delay circuit that generates the first timing signal with a reference delay, and a delay emulation circuit that generates the second timing signal with an emulation delay that correlates with the output buffer delay.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: September 30, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Yu-Meng Chaung, Chun-Hsiung Hung, Kuen-Long Chang, Ken-Hui Chen
  • Patent number: 8847636
    Abstract: A method and circuit for implementing protection for complementary metal oxide semiconductor (CMOS) output drivers, and a design structure on which the subject circuit resides are provided. An output driver stage transistor stack includes a plurality of series connected PFETs series connected with a plurality of series connected NFETs connected between upper and lower voltage supply rails. A pair of offset DC voltage levels provides respective gate voltages of an intermediate PFET and an intermediate NFET in the output driver stage transistor stack. A pair of pre-driver circuits receiving voltage level translated logic signals drive respective gate inputs of the upper PFET and the lower NFET in the output driver stage transistor stack. A voltage feedback circuit provides respective gate voltages of the PFET and NFET connected together in the output driver stage transistor stack.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael K. Kerr, William F. Lawson
  • Patent number: 8847637
    Abstract: Described are a multi-modulus frequency divider and event counter that are based on time-interleaved signals generated from a received signal. For the frequency divider, each time-interleaved clock signal generated from a received clock signal is provided to a bit counter and the output signal from each bit counter is provided to a multiplexer. A multiplexer selection module controls over time which one of the output signals from the bit counters is presented at the output of the multiplexer. The transition frequency of the bits in the time-interleaved clock signals allows various circuit components such as the bit counters to be implemented as CMOS components. Thus the frequency divider is more power-efficient than conventional frequency divider circuits operating at high clock frequencies.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: September 30, 2014
    Assignee: Massachusetts Institute of Technology
    Inventor: Matthew C. Guyton
  • Patent number: 8847638
    Abstract: A high frequency divider involves a plurality of differential latches. Each latch includes a pair of cross-coupled P-channel transistors and a variable resistance element. The latch is controlled to have a lower output resistance at high operating frequencies by setting a multi-bit digital control value supplied to the variable resistance element. Controlling the latch to have a reduced output resistance at high frequencies allows the 3 dB bandwidth of the latch to be maintained over a wide operating frequency range. The variable resistance element is disposed between the two differential output nodes of the latch such that appreciable DC bias current does not flow across the variable resistance element. As a consequence, good output signal voltage swing is maintained at high frequencies, and divider current consumption does not increase appreciably at high frequencies as compared to output signal swing degradation and current consumption increases in a conventional differential latch divider.
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: September 30, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Ngar Loong Alan Chan, Shen Wang
  • Patent number: 8847639
    Abstract: A waveform generator for providing an analog output signal to a target device includes a look-up-table (LUT) that stores a plurality of binary address values and a digital-to-analog converter (DAC) that generates the analog output signal. The waveform generator receives an input trigger signal from the target device when the target device is ready to receive the analog output signal. The waveform generator generates a synchronized input trigger signal and aligns the analog output signal with the synchronized input trigger signal by reloading the LUT with a binary address value of zero.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: September 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Alok Srivastava, Shrestha Priya
  • Patent number: 8847640
    Abstract: A trigger signal detection apparatus includes: a clock gating circuit which is supplied with a trigger signal and a clock signal and outputs the clock signal; a trigger signal processing circuit which outputs a first signal only for a predetermined time when the clock signal is supplied from the clock gating circuit; a counter which operates in response to the trigger signal, thus outputting a count value of the clock signal; and a time set-up circuit which outputs a second signal to the trigger signal processing circuit when count value supplied from the counter reaches a preset value, and the trigger signal processing circuit stops outputting the first signal when the trigger signal processing circuit receives the second signal.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: September 30, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihide Suzuki
  • Patent number: 8847641
    Abstract: A phase detection range is enabled to be expanded to an arbitrary number of times of a cycle of a reference clock, and in the case of application to a DLL circuit, an operation cycle is enabled to be freely selected. A phase comparison device includes a divider that generates a division clock obtained by receiving a reference clock and dividing it by two; an inverter that inverts a phase of the division clock to generate a division inverted clock; a DFF circuit that synchronizes the division inverted clock with a delay clock to generate a synchronized clock; a DFF circuit that synchronizes the clock with the feedback clock to generate a final synchronized clock; and a phase comparator that receives the division clock and the final synchronized clock to compare phases of the division clock and the final synchronized clock.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: September 30, 2014
    Assignee: MegaChips Corporation
    Inventor: Shoichiro Kashiwakura
  • Patent number: 8847642
    Abstract: A charge pump phase-locked loop circuit includes an active loop filter, an adjustable reference voltage source, and a charge pump. The active loop filter includes an amplifier that has a negative input node, a positive input node, and an output node. The adjustable reference voltage source is coupled to the positive input node to provide an adjustable reference voltage. The charge pump is coupled to the negative input node to provide a current to or draw a current from the active loop filter in response to a signal from a phase detector. The charge pump includes a first current source coupled to a first voltage and a second current source electrically coupled to a second voltage, the second current source including a resistor. The second current source is configured such that a current provided by the second current source depends on a resistance value of the resistor and a difference between the reference voltage and the second voltage.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: September 30, 2014
    Assignee: MStar Semiconductor, Inc.
    Inventors: Ryan Lee Bunch, Walter H. Prada
  • Patent number: 8847643
    Abstract: A semiconductor device includes a delay part configured to assign a delay to an input signal, a phase detector configured to detect a phase of an output signal output from the delay part, a setting part configured to set a stable operations range of the phase of the output signal based on phase information output from the phase detector, and an error detector configured to set an acceptable range corresponding to the stable operations range, determine whether a phase of the output signal falls within the acceptable range, and change the acceptable range based on an extraneous factor of an input signal of the delay part.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: September 30, 2014
    Assignee: Fujitsu Limited
    Inventors: Koji Migita, Yoshito Koyama, Kazumasa Kubotera, Yasutaka Kanayama
  • Patent number: 8847644
    Abstract: A semiconductor apparatus includes: a variable delay unit configured to delay a reference clock signal in response to a delay code and generate a data latch clock signal; a delay amount control unit configured to convert a phase of external data and a phase of the data latch clock signal into first and second codes, respectively, and generate the delay code through a calculation of the first and second codes; and a data receiver configured to latch the external data as internal data in synchronization with the data latch clock signal.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: September 30, 2014
    Assignee: SK Hynix Inc.
    Inventor: Kwan Dong Kim
  • Patent number: 8847645
    Abstract: A semiconductor device includes a sampling unit suitable for sampling a logic value of an input signal based on an edge of an operation clock to output a sampling signal, an edge detection unit suitable for detecting an edge of the input signal based on the sampling signal, and a phase control unit suitable for controlling a phase of the operation clock while periodically changing a value of a clock delay code at each predetermined period and substituting a code value, which is obtained by calculating a value of the clock delay code corresponding to a time point at which an operation of the edge detection unit is completed and a value of a pre-phase code determined based on the sampling signal, for the clock delay code.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: September 30, 2014
    Assignee: SK Hynix Inc.
    Inventor: Sang-Yeon Byeon
  • Patent number: 8847646
    Abstract: In a system in which the phases of a data clock signal and a data signal differ between at an input and at an output, a semiconductor integrated circuit performs a simple BER test without using external equipment and, at the same time, performs a jitter evaluation required for a margin evaluation.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: September 30, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasushi Yamakawa
  • Patent number: 8847647
    Abstract: An input signal and a reset signal are provided to respective inputs of a resettable flip-flop. The resettable flip-flop generates an output signal. The output signal transitions from a first logic state to a second logic state in response to corresponding transitions of the input signal and transitions from the second logic state to the first logic state in response to assertion of the reset signal. A warning signal is asserted in response to transitions of the input signal from the second logic state to the first logic state. A logic gate forwards the output signal when the warning signal is de-asserted and provides a signal in the first logic state in response to assertion of the warning signal.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: September 30, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Mark Buckler
  • Patent number: 8847648
    Abstract: A voltage pulse train generator which may find application to control of an ultrasound piezoelectric injector, and including a voltage source providing a DC initial voltage, a DC/DC converter supplied with the initial voltage and configured to charge a capacitor according to an intermediate DC voltage greater than the initial voltage, a DC/AC converter operating by switching, by alternating active phases and inactive phases, which is configured to transform the intermediate voltage from the capacitor into a final voltage pulse train, and a control unit provided for driving the converters. The DC/DC converter is configured to operate to charge the capacitor at a same time as the DC/AC converter, at most during the inactive phases of the switching of the DC/AC converter.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: September 30, 2014
    Assignee: Renault S.A.S.
    Inventors: Paulo Barroso, Clement Nouvel
  • Patent number: 8847649
    Abstract: The present invention discloses a circuit and a method of adjusting system clock in low voltage detection, and a low voltage reset circuit. The circuit of adjusting system clock in low voltage detection comprises: a clock generator for supplying a clock to at least one circuit in a system; and a low voltage reset circuit for generating an adjustment signal according to a detected voltage level, so that the clock generator adjusts or stops the clock supplied to the at least one circuit in the system.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: September 30, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventor: Wen-Che Wu
  • Patent number: 8847650
    Abstract: A method and apparatus for generating a wave shaped pulse electronic signal of a predetermined format from a square pulse signal generator. A signal is applied from the square pulse generator to circuitry having a plurality of transmission lines. Each transmission line having a certain length creating a certain signal time delay and signal reflection for a signal applied to the circuitry from the square pulse generator so as to create a delay pulse from each transmission line. Each delay pulse is combined from each transmission line to generate the wave shaped pulse electronic signal of a desired predetermined format.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: September 30, 2014
    Assignee: Hamilton Sundstrand Corporation
    Inventor: Robert D. Klapatch
  • Patent number: 8847651
    Abstract: Techniques and mechanisms for operating an integrated circuit to communicate via a hardware interface for the integrated circuit, wherein a pinout with the hardware interface is based on the configuration. In an embodiment, the integrated circuit receives a first plurality of signals via the hardware interface, and sequentially latches a second plurality of signals based on the first plurality of signals. In another embodiment, some or all of the second plurality of signals are variously latched by the integrated circuit in an order which is based on the first configuration.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 30, 2014
    Assignee: Intel Corporation
    Inventor: Michael D. Mirmak
  • Patent number: 8847652
    Abstract: The present disclosure relates to a resonant clock system having a driver component, a clock load capacitor, and a reconfigurable inductor array. The driver component generates a driven input signal. The clock load capacitor is configured to receive the driven input signal. The inductor array is configured to have an effective inductance according to a selected frequency. The inductor array also generates a resonant signal at the selected frequency using the effective inductance.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chan-Hong Chern, Tao Wen Chung, Chih-Chang Lin, Ming-Chieh Huang, Tsung-Ching Huang, Fu-Lung Hsueh
  • Patent number: 8847653
    Abstract: A dither control circuit includes a pseudo random number generator, which generates a pseudo random number sequence in response to a frequency-divided clock signal, and a dither circuit which dithers an input digital code by using at least one output bit of the pseudo random number sequence and outputs a dithered digital code corresponding to a result of the dithering. The dither circuit may output, as the dithered digital code, a digital code corresponding to a sum of or a difference between the input digital code and the input digital code based on the at least one output bit. The dithered digital code may be input to an accumulator which operates in-sync with the frequency-divided clock signal.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: September 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Phil Hong, Jenlung Liu, Nan Xing, Jae Jin Park