Abstract: In a controlling circuit, a photo coupler is used for isolating noises, and a general purpose amplifier is used for adjusting a gain, so that a logic tester may test analog signals in cooperation with relays having different specifications and operating voltage level differences in an analog measurement module. A shift register of each controlling circuit of a controlling module also transmits a test data signal to a next stage controlling circuit, so that a logic tester may simultaneously output a plurality of bits to multiple controlling circuits and multiple analog measurement modules by using merely one I/O port.

Abstract: The present description relates to a semiconductor device including an array of two or more switching elements and a controller electrically connected to the array of switching elements. At least one switching element of the array of switching elements has a different electrical resistance than at least another switching element of the array of switching elements. The controller is configured to generate and transmit at least one coarse tuning signal and at least one fine tuning signal. The array of switching elements is configured to alter an electrical resistance of the array of switching elements in response to the at least one coarse tuning signal and the at least one fine tuning signal. The present description also includes a method of making a semiconductor device and a method of using a semiconductor device.

Abstract: A system that drives multiple MOSFETs in parallel for direct current and alternating current solid state power controller applications may include networks connected to the gates of the MOSFETs to protect the MOSFETs from being damaged during high current interruption. For direct current applications, the system may include a switching protection and damping network and a gate drive balancing network. For alternating current applications, the system may include two switching protection and damping networks and a gate drive balancing network.

Abstract: An apparatus comprising a first stage and a second stage. The first stage may be configured to generate an intermediate signal having a first voltage in response to an input signal having a second voltage received from a pad. The second stage may be configured to generate a core voltage in response to the first voltage. The voltage received from the pad may operate at a voltage compliant with one or more published interface specifications.

Abstract: An overdrive circuit includes a pull-up circuit and a pull-down circuit. The pull-down circuit includes first, second and third transistors electrically connected in cascode between an output node and a low voltage supply node. A capacitor is electrically connected from a gate electrode of the third transistor to a gate electrode of the first transistor. A first mono-directional bias device is electrically connected from a drain electrode of the first transistor to a gate electrode of the first transistor. A second mono-directional bias device is electrically connected from the gate electrode of the first transistor to a source electrode of the first transistor.

Abstract: A level shifter system includes an inverting portion, a non-inverting portion and a cross latch output component. The inverting portion is configured to receive an inverting input, a supply voltage and to generate an intermediary inverting output. The non-inverting portion is configured to receive a non-inverting input, the supply voltage and to generate an intermediary non-inverting output. The cross latch output component is configured to drive the intermediary inverting and non-inverting outputs to inverting and non-inverting outputs, respectively. The inverting and non-inverting outputs are at selected upper and lower levels according to the inverting input and non-inverting inputs, respectively.

Abstract: According to one embodiment, in a level shift switch, a first input signal is inputted into a first input-output terminal, a first output signal is outputted from a second input-output terminal, a second input signal is inputted into the second input-output terminal, a second output signal is outputted from the first input-output terminal. The level shift switch includes a transmission circuit, a first MOSFET, a second MOSFET, and a first one-shot pulse generation circuit.

Abstract: Disclosed is a level shift device. The level shift device to convert an input signal having a low-voltage level into an output signal having a high-voltage level includes a latch-type level shifter and a voltage generator. The latch-type level shifter includes two upper pull-up P channel transistors and two lower P channel transistors to prevent the gate-source voltage breakdown of the two upper pull-up P channel transistors. The two upper pull-up P channel transistors and the two lower P channel transistors form a latch structure. The voltage generator generates a voltage to prevent the gate-source voltage brake down of the two upper pull-up P channel transistors and provides the voltage to the gate electrodes of the two lower P channel transistors.

Abstract: A mixer for providing a mixed signal by mixing an input signal and an oscillation signal, comprising a follower and a switch. The follower is arranged to conduct a driving contribution from a bias terminal to an output terminal following a signal at an input terminal, wherein the input terminal and the bias terminal are respectively coupled to the input signal and the oscillation signal, and the output terminal is arranged to output the mixed signal. The switch is arranged to selectively conduct the output terminal to a reference level in response to alternating of the oscillation signal. An associated signal circuit is also disclosed.

Abstract: A gate drive circuit which drives a gate terminal of a semiconductor switching device includes: a first wireless signal transmitter which transmits an input first AC signal wirelessly; a second wireless signal transmitter which transmits an input second AC signal wirelessly; a first rectifier circuit which includes a first diode that rectifies an output signal from the first wireless signal transmitter; and a second rectifier circuit which includes a second diode that rectifies an output signal from the second wireless signal transmitter. A threshold voltage of the second diode is larger than a threshold voltage of the first diode.

Abstract: A gate control circuit including: a gate input arranged to receive an input gate feed signal; a gate output arranged to be connected, during normal operation, to at least one switching module for controlling current through a main circuit, the gate output being connected to the gate input; a power supply; and a switch connected between the power supply and the gate output, the switch being arranged to close as a response to a failure. A corresponding power module and method are also presented.

Abstract: A semiconductor device has an analog switch, in which a P channel transistor and an N channel transistor are connected in parallel between an input terminal and an output terminal; a variable voltage circuit, which variably generates, according to an input voltage applied to the input terminal, potentials of a first gate voltage and first back gate voltage of the P channel transistor and of a second gate voltage and second back gate voltage of the N channel transistor; and a control circuit, which supplies to the variable voltage circuit a control signal controlling the analog switch to be conducting or non-conducting. In response to the control signal causing the analog switch to be conducting, the variable voltage circuit outputs the variable-generated first gate voltage and second gate voltage to the respective gates of the P channel transistor and N channel transistor.

Abstract: A radio frequency (RF) switch includes a common port, a first port, and a second port, a first semiconductor switching element disposed in a first RF pathway between the common port and the first port, a second semiconductor switching element disposed in a second RF pathway between the common port and the second port, a first pair of direct current (DC) blocking capacitors disposed to isolate the first semiconductor switching element in the first RF pathway, and a second pair of DC blocking capacitors disposed to isolate the second semiconductor switching element in the second RF pathway. The respective pairs of DC blocking capacitors allow for different bias voltages to be applied to the respective RF pathways. A charge-discharge circuit may also be employed to decrease transient switching time of the RF switch.

Abstract: An RF switch circuit for switching RF signals includes a first terminal and a second terminal and a series connection of a plurality of transistors between the first terminal of the RF switch circuit and the second terminal of the RF switch circuit. Furthermore, the RF switch circuit includes a control circuit configured to conductively couple, in a high impedance state of the RF switch circuit, the first terminal of the RF switch circuit to a control terminal of a first transistor in a series of the series connection of the plurality of transistors. The second terminal of the RF switch circuit is conductively coupled to a control terminal of a last transistor in the series of the series connection of the plurality of transistors.

Abstract: An RF switch includes a transistor and a compensation capacitor circuit. The compensation capacitor circuit includes a first compensation capacitor and a second compensation capacitor of the same capacitance. The compensation capacitor circuit is used to improve voltage distribution between a control node and a first node of the transistor and between the control node and a second node of the transistor.

Abstract: A method for controlling a temperature of a terminal and a terminal supporting the same are provided. A terminal supporting temperature control includes a temperature sensor for detecting a temperature of the terminal, and a controller for performing at least one of a first throttle procedure including driving the controller with a first preset driving frequency when the temperature of the terminal detected by the temperature sensor is a first preset temperature, and driving the controller with a second driving frequency higher than the first driving frequency when the temperature of the terminal is reduced to a second preset temperature lower than the first preset temperature, and a second throttle procedure including driving the controller with the first preset driving frequency for a first time, and driving the controller with the second driving frequency higher than the first driving frequency for a second time after the first time elapses.

Abstract: An input apparatus includes a touch plate, a decoration layer, a film sensor, an electrode portion, a wire portion, and a guard layer. The touch plate is a basal plate for finger manipulation. The decoration layer is on a front side of the touch plate to decorate the front side. The film sensor is bonded to a rear side of the touch plate. The electrode portion is on the film sensor. The wire portion is on the film sensor and connected to the electrode portion to transmit a signal outputted from the electrode portion. The guard layer contains a guard layer formation material to suppress an electrostatic capacity between the finger and the wire portion. The guard layer formation material is combined into the decoration layer such that the decoration layer and the guard layer are provided as a single integrated member.

Abstract: A charge pump comprises, a plurality of branches each having serially-connected T-circuit cells, wherein each of the branches has a first end for receiving an input voltage and a second end for outputting a charge pump voltage, wherein each of the T-circuit cells comprises a first transistor, a second transistor, and a capacitor, wherein the first transistor and the second transistor of each of the T-circuit cells have a common drain, and wherein the gate of the first transistor of a certain one of the T-circuit cells of a certain branch is connected to a first branch and the gate of the second transistor of the certain one of the T-circuit cells of the certain branch is connected to a second branch.

Abstract: Embodiments provide a switching device including one or more field-effect transistors (FETs). In embodiments, a resistive divider comprising a first resistor and a second resistor may be coupled with the FET at a position electrically between a gate terminal of the FET and a body terminal of the FET.

Abstract: A conventional circuit requires a booster circuit for generating a voltage higher than an external power supply voltage, thus low power consumption is difficult to be achieved. In addition, a display device incorporating the aforementioned conventional switching element for booster circuit has problems in that the current load is increased and the power supply becomes unstable with a higher output current.

Abstract: A device includes a digital to analog converter (DAC) configured to generate a voltage output or a current output. The device also includes an integrated circuit configured to receive at least one of the voltage output or the current output and transmit the at least one of the voltage output or the current output to a load, wherein the integrated circuit is configured to measure a voltage level or a current level related to the transmission of the at least one of the voltage output or the current output. In one embodiment, a current limiter is included for voltage outputs as a form of power limiting and circuit protection. Additionally, the device includes a controller configured to receive an indication of the measurement from the integrated circuit and determine if the indication of the measurement exceeds a predetermined threshold.

Abstract: A semiconductor device comprises a plurality of circuit blocks, a plurality of local wirings which supply power to the plurality of circuit blocks, respectively, a global wiring which supplies the power to the plurality of local wirings, a plurality of first switches which are disposed between the plurality of local wirings, respectively, and the global wiring, and a second switch which is disposed between two local wirings. A power control unit controls open/close of the plurality of first switches and the second switch based on the potential difference between the two local wirings.

Abstract: A system that includes a polyphase filter comprises first and second gm-C filters with first and second variable biasing and a bias controller coupled to the first and second gm-C filters and configured to offset the first variable biasing and corresponding first gm of the first gm-C filter relative to the second variable biasing and corresponding second gm of the second gm-C filter to thus improve image rejection in the system. A corresponding method includes processing a signal in a complex polyphase filter and controlling biasing of the first gm-C filter stage relative to the second gm-C filter stage to provide a mismatched gm and thereby improve rejection of the image signal.

Abstract: According to one embodiment, an amplification circuit can be switched between amplifying and calibration modes. During calibration, a preamplifier amplifies a differential input signal and generates a differential output signal. The amplifier circuit includes an input switch unit which sets a differential input signal as the reference voltage signal of the same voltage level at the time of calibration, a PWM conversion unit which carries out Pulse-Width-Modulation of the differential output signal, and generates a differential PWM signal based on the result of comparing the differential output signal with the reference signal, a calibration unit which generates an offset adjustment signal according to the phase difference of differential PWM signals, and an electric amplifier which carries out electric power amplification of the differential PWM signal and generates the differential final output signal.

Abstract: A frequency compensation circuit for a voltage regulator is provided in embodiments of the present invention.

Abstract: Amplifier units and methods of use are described herein. A amplifier unit includes a first amplifier and a second amplifier connected in parallel, the first amplifier and the second amplifier comprising semiconductor devices that are not the same amplifier design. The present application also discloses a signal input line connected to the first amplifier and the second amplifier. A signal output line is also disclosed which is connected to the first amplifier and the second amplifier.

Abstract: A combiner for a Doherty amplifier includes, on and in a dielectric substrate, a carrier input terminal, a peak input terminal, an output terminal, a combining point for combining an output signal from the carrier amplifier and an output signal from the peak amplifier, a first ?/4 line connected between the carrier input terminal and the combining point, a second ?/4 line connected between the combining point and the output terminal, and a first directional coupler. The first directional coupler includes a third ?/4 line electromagnetically coupled to one, to be monitored, of the first ?/4 line and the second ?/4 line.

Abstract: An amplifier may include two or more pulse-width modulators (PWMs) controlling respective sets of switches to produce an amplified version of a source signal. The clocking for the amplifier may be controlled to delay signal processing within the PWMs relative to one another in time, thereby providing an effective time offset between the respective edge transitions of the controlling signals provided to the respective sets of switches. The PWMs may count down to zero from the next PWM duty-cycle value when a new data sample is detected, beginning a new count for each new sample, with the PWM outputting a pulse when the counter value is nonzero. A “data-sample-ready” signal may be decoded from a master counter, which may be clocked based on the high speed PWM clock, and the decode value may be adjusted to determine when the PWM should initialize to the next data sample.

Abstract: A differential amplifying circuit includes: two metal oxide semiconductor transistors to form a differential pair and receive a differential signal; a plurality of capacitance elements coupled in series between drains of the two metal oxide semiconductor transistors; and an inductance circuit coupled between at least one connection node of the plurality of capacitance elements and a bias power terminal.

Abstract: Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.

Abstract: A push-pull amplifier includes an amplifier input, a push amplifier stage, a pull amplifier stage and an inverting amplifier output.

Abstract: A radio frequency (RF) power amplifier is disclosed. The RF radio power amplifier includes a bias current generating unit, a first impedance unit, a second impedance unit, a third impedance unit and an output stage unit. The bias current generating unit receives a reference voltage. There is a first voltage with negative temperature coefficient between the first impedance unit and the second impedance unit, and the second unit receives a ground current. There is a second voltage between the third impedance unit and the second impedance unit, and the second voltage is a partial voltage of the first voltage. The bias current generating unit outputs a bias current with positive temperature coefficient according to the second voltage. The output stage unit receives an input current. The bias current is a sum of the input current with positive temperature coefficient and the ground current.

Abstract: An amplifier device having an extended bandwidth includes a DC coupled amplifier and multiple low noise amplifiers connected in series with one another and connected in parallel with at least a portion of the DC coupled amplifier. The DC coupled amplifier has a broad bandwidth, and each of the low noise amplifiers has a narrow bandwidth and a center frequency higher than a high end frequency of the broad bandwidth of the DC coupled amplifier. The extended bandwidth of the amplifier device is a combination of the broad bandwidth and the first narrow bandwidth.

Abstract: A method for processing signals may include comparing an output voltage signal in an output stage of an amplifier with a reference voltage signal. If the output voltage signal is greater than the reference voltage signal, a comparator voltage signal may be generated. Bias voltage for at least one output stage transistor may be increased by increasing current generated by a first bias current source of the at least one output stage transistor. The current may be increased in proportion to the generated comparator voltage signal. The output voltage signal may be divided prior to the comparing. The at least one output stage transistor may be dynamically biased based on the generated comparator voltage signal. The comparator voltage signal may be generated using at least one differential pair with a current mirror load.

Abstract: Techniques for improving linearity of amplifiers are described. In an exemplary design, an amplifier (e.g., a power amplifier) may include a plurality of transistors coupled in a stack and at least one diode. The plurality of transistors may receive and amplify an input signal and provide an output signal. The at least one diode may be operatively coupled to at least one transistor in the stack. Each diode may provide a variable bias voltage to an associated transistor in the stack. Each diode may have a lower voltage drop across the diode at high input power and may provide a higher bias voltage to the associated transistor at high input power. The at least one transistor may have higher gain at high input power due to the higher bias voltage from the at least one diode. The higher gain may improve the linearity of the amplifier.

Abstract: Aspects of the embodiments include a method for synchronizing a device having an oscillator to a reference signal. A correction signal can be determined based on the reference signal. A mathematical model of the oscillator can be trained based at least upon the correction signal. A predicted correction signal for the trained mathematical model can be determined. A time error using the predicted correction signal can be generated to assess suitability of the trained mathematical model for disciplining drift in the oscillator and synchronizing the device when the reference signal is not available.

Abstract: A gated voltage controlled oscillator has four identically structured delay cells, each of the delay cells having the same output load by connecting to the same number of inputs of other ones of the delay cells. Optionally a four phase sampling clock selects from the delay cell output and samples, at a four phase sampler, an input signal. Optionally an edge detector synchronizes the phase of the gated voltage controlled oscillator to coincide with NRZ bits. Optionally a variable sampling rate selects different phases from the delay cells to selectively sample NRZ bits at a lower rate. Optionally, a pulse width modulation (PWM) mode synchronizes a phase of the sampling clock to sample PWM symbols and recover encoded bits.

Abstract: Oscillators and method of operating the same are provided, the oscillators include a magnetic layer, and a magnetization fixing element configured to fix a magnetization direction of the magnetic layer. The oscillators generate a signal by using precession of a magnetic moment of the magnetic layer.

Abstract: A system and method is disclosed that provides a technique for generating an accurate time base for MEMS sensors and actuators which has a vibrating MEMS structure. The accurate clock is generated from the MEMS oscillations and converted to the usable range by means of a frequency translation circuit.

Abstract: A quartz crystal vibrator element having the weight section is provided with the intermediate weight section formed to have an arm width W1 larger (thicker) than the arm width W of the vibrating arm section and smaller (thinner) than the arm width W2 of the tip weight section, thereby making the intermediate weight section follow the vibration (the amplitude) of the vibrating arm section. Further, the tip weight section formed to have an arm width W2 larger (thicker) than the arm width W1 of the intermediate weight section is provided, thereby making the tip weight section follow the vibration (the amplitude) of the vibrating arm section and the intermediate weight section. Therefore, the vibration characteristics of the vibrating arm section can be stabilized.

Abstract: A substantially temperature-independent LC-based oscillator is achieved using an LC tank that generates a tank oscillation at a phase substantially equal to a temperature null phase. The temperature null phase is a phase of the LC tank at which variations in frequency of an output oscillation of the LC-based oscillator with temperature changes are minimized. The LC-based oscillator further includes frequency stabilizer circuitry coupled to the LC tank to cause the LC tank to oscillate at the phase substantially equal to the temperature null phase.

Abstract: A high speed flexible interconnect cable for an electronic assembly includes a number of conductive layers and a number of dielectric layers. Conductive signal traces, located on the conductive layers, combine with the dielectric layers to form one or more high speed electrical transmission line structures. The cable can be coupled to electronic components using a variety of connection techniques. The cable can also be terminated with any number of known or standardized connector packages.

Abstract: A communication system of the present invention includes: a communication coupler that transmits a signal; and a signal transmitting apparatus that communicates by propagating, as an electromagnetic field, the signal transmitted from the communication coupler, the communication coupler includes a coupler case disposed on the signal transmitting apparatus, a noise suppressing section is provided on a lower end surface of the coupler case, the lower end surface faces the signal transmitting apparatus, and the noise suppressing section suppresses noise by creating a high impedance.

Abstract: A high-speed feedthrough (HSFT) is disclosed for transmitting a signal having a highest frequency of at least 10 GHz between first and second locations separated by a vertical distance of at least approximately half of the shortest transmitted wavelength, and separated by a horizontal distance. A substrate structure includes multiple stacked layers. An RF transmission line is connected through the structure between the first and second locations for transmitting the signal. The RF transmission line comprises a series of sequentially connected horizontal conductors having lengths less than half of the effective wavelength and vertical conductors having heights less than one quarter of the effective wavelength, thereby spanning the horizontal and vertical distance between the two locations in a stairs-like shape through the structure's layers. Each conductor's geometry may deviate from standard 50 ohm buried strip lines and is optimized for complete 3-dimensional structure.

Abstract: A circuit substrate on which a duplexer is mounted includes a substrate body. First, second and third external electrodes are provided on a first main surface of the substrate body. Fourth, fifth and sixth external electrodes are provided on a second main surface of the substrate body. First, second and third signal paths connect the first, second and third external electrodes to the fourth, fifth and sixth external electrodes, respectively. First and second ground conductors are embedded in the substrate body, and overlap with a mounting area so as to contain the mounting area where the duplexer is mounted, in a planar view seen from the z-axis direction. The first, second and third signal paths extend from the inside of the mounting area to the outside of the mounting area between the first main surface and the second ground conductor.

Abstract: The filter includes one or more series resonators and one or more parallel resonators. An inductance is connected in series to at least a parallel resonator of the parallel resonators, and a antiresonance frequency of the parallel resonator to which the inductance is connected in series is equal to or higher than that of the series resonators. The duplexer, the communication module and the communication device are provided with the filter.

Abstract: A DC blocking device of a small size is disclosed. The disclosed DC blocking device may include: an internal conductor where RF signals are inputted; and an external conductor electrically connected to a ground; wherein the internal conductor has an insertion groove, and an insertion conductor is inserted into the insertion groove without touching the internal conductor and at a designated distance, and the diameter of the external conductor in the portion where the insertion conductor is inserted is set to be different from the diameter of another portion. The disclosed DC blocking device has the advantages of minimizing the spatial constraint when the DC blocking device is mounted on a mobile communication device, and of achieving suitable coupling even if the length of the part where coupling is achieved is reduced in the DC blocking device.

Abstract: Systems and methods which utilizes a stub array microstrip line for providing a phase shifter configuration are shown. A stub array microstrip line phase shifter of embodiments may comprises a microstrip line structure, an isolation structure, and a phase tuning structure cooperative to provide phase shifting of signals passed through the microstrip line structure. A microstrip line structure comprises a stub array microstrip line having a plurality of microstrip stubs provided in association with a slotted ground plane having a plurality of slots. The stub array microstrip line is adapted to provide compensation for capacitance and/or inductance associated with the slots of the slotted ground plane. A phase tuning structure provides coupling of signals transmitted by the stub array microstrip line to the slots of the slotted ground plane for signal phase shifting.

Abstract: The invention relates to a filtering network in HR-Si silicon technology defined by at least one cut-off frequency and comprising an input terminal for receiving the signal to be filtered and an output terminal for delivering a filtered signal. The network comprises a first ground line connected by its ends to first and second ground points connected directly to the ground plane, a second ground line connected via its ends to third and fourth ground points directly connected to the ground plane, a plurality of L/C resonant elements connected in parallel and linked via one end to one of the two ground lines and via the other end between them, by means of coupling inductors which thus create transmission zeros.

Abstract: In an electronic component, a laminated body includes a plurality of insulator layers laminated on each other. First, second and third LC parallel resonators are loop-shaped LC parallel resonators that include via hole conductors extending in a z-axis direction and conductor layers provided on the insulator layers, and define a band pass filter. Loop planes of the first and third LC parallel resonators and a loop plane of the second LC parallel resonator are parallel to the z-axis direction and not parallel to each other.