Abstract: An endoscope according to the present invention includes: a first image pickup optical system for observing a first observation direction, a second image pickup optical system for observing an observation a second observation direction, a light guide guiding illumination light, and an illumination optical system including a ring-shaped portion illuminating the first observation direction, an incident surface being in contact with an end surface of the light guide to receive the illumination light, and two reflecting surfaces disposed at a position opposite to the incident surface, having inclinations in two directions with respect to a surface orthogonal to the longitudinal direction of the insertion portion, disposed so as to face each other, and reflecting the illumination light incident from the light guide toward directions along tangent lines of the ring-shaped portion of the illumination optical system, to cause the illumination light incident to inside of the illumination optical system.

Abstract: A light source apparatus includes a light source, an optical fiber, and a positioning mechanism. The positioning mechanism is configured with a planar position adjustment mechanism, an axial line position adjustment mechanism, and an orientation maintaining mechanism. The planar position adjustment mechanism adjusts a position of the optical fiber in a direction following the light-emitting surface. The axial line position adjustment mechanism adjusts the position of the optical fiber in a direction intersecting with the light-emitting surface. The orientation maintaining mechanism holds the optical fiber in a state where an axis direction of the optical fiber lies in a predetermined intersecting direction with respect to the light-emitting surface.

Abstract: A LED light bar, a related planar light source and a method of manufacturing such light bar is provided. The light source includes a light guide plate having a first surface and a second surface; at least one light bar, on which a plurality of LEDs is disposed, wherein the light bar is disposed on a lateral side of the light guide plate, and the LEDs are disposed inside the light guide plate to output light; a reflector, which is disposed outside the second surface and reflects light; and a diffuser, which is disposed outside the first surface and scatters reflected light of the reflector. Because LEDs are pre-disposed in a mold when the light guide plate is manufactured, the LEDs and the light guide plate are integrally formed, the loss of light can be avoided, and the efficiency of the planar light source can be enhanced.

Abstract: A backlight unit is disclosed. The backlight unit includes a light emitting device to emit light, an optical member to guide the light emitted from the light emitting device, a bottom chassis disposed on a rear surface of the optical member so as to support the optical member, a supporting member coming into partial contact with the bottom chassis so as to support a module including the light emitting device and a shock-absorbing member disposed between the rear surface of the optical member and the bottom chassis.

Abstract: An optical system comprises a light source emitting light, a collimating structure to substantially collimate the light, a converter unit to receive the substantially collimated light having an area illuminating a first aspect ratio and outputting light having an area illuminating a second aspect ratio, the second aspect ratio greater than the first aspect ratio by at least a factor of four, and a backlight light guide to receive the light from the converter unit.

Abstract: A backlight module including a light guiding plate, a light source and a block is provided. The light guiding plate includes a first surface, a second surface opposite to the first surface, a light incident surface connecting to the first surface and the second surface, and a side surface opposite to the light incident surface. A thickness of at least part of the light guiding plate decreases progressively from the side surface towards the light incident surface. The light source is disposed beside the light incident surface and is capable of emitting a light beam into the light guiding plate through the light incident surface. The block is disposed beside the side surface and includes a reflecting surface facing towards the side surface. The reflecting surface is a concave surface on the block, and the reflecting surface is capable of reflecting the light beam returning to the side surface.

Abstract: A light source device includes: a rod-shaped light source or an array light source extending in a main scanning direction; a reflector that is placed opposite the rod-shaped light source or the array light source, extends in the main scanning direction, and reflects light output from a side face of the rod-shaped light source or the array light source; and a plurality of reflector supports that are arranged at an interval along the main scanning direction and support the reflector.

Abstract: According to one aspect, a luminaire comprises a waveguide body including a central section and first and second separate side sections extending away from the central section along first and second opposed directions, respectively. The central section includes a coupling portion and the waveguide body has a length and includes a plurality of light extraction features that extract light out of the side sections. At least one LED is disposed adjacent the coupling portion and is operated by a power circuit to produce light that is directed into the waveguide body by the coupling portion. At least one structural member extends along the length of the waveguide body for supporting the waveguide body and encloses at least one of the power circuit and the at least one LED.

Abstract: A display module includes an outer frame, a light emitting unit, a panel device, and a light guide plate having a light entrance surface, a light exit surface, and a connecting side. A connecting ear portion is extendedly formed from the connecting side for extending into the outer frame to fix the light guide plate onto the outer frame. The light emitting unit is disposed in the outer frame corresponding to the light entrance surface for emitting light into the light guide plate via the light entrance surface. The panel device is disposed on the light guide plate and contained in the outer frame for receiving light emitted from the light guide plate. The connecting ear portion is away from the light exit surface by a vertical distance, and the ratio of the length of the connecting ear portion to the length of the connecting side is greater than 0.2.

Abstract: A backlight assembly includes a plurality of point light sources, a light guide plate (“LGP”) and a printed circuit board (“PCB”). The LGP has a light incident face in which light is incident, a side surface extending from an edge portion of the light incident face, and a fixing groove which is formed from the side surface toward an inner portion thereof The PCB includes a point light source disposing portion in which the point light sources are disposed along a first direction, an extending portion extending from the point light disposing portion along a second direction substantially perpendicular to the first direction, and a protrusion which is fixed at an end portion of the extending portion. The protrusion of the PCB is coupled with the fixing groove of the LGP.

Abstract: A light guiding device includes a light input surface, a light output surface extending from a first edge of the light input surface, a connecting surface extending from a second edge of the light input surface, and a reflecting surface interconnecting the output surface and the connecting surface. Relationships of ?<?, ?<?T and L?(AD)/tan? are satisfied, where ?T is a critical angle for total internal reflection, ? is an angle between extensions of the connecting surface and the light output surface, ? is an angle between the reflecting and light output surfaces, (L) is a distance between the second edge and the end edge, and (AD) is a distance between a location of incidence of a light beam on the light input surface and one of the first or second edge.

Abstract: A power conversion apparatus includes a primary side circuit and a secondary side circuit magnetically coupled to the primary side circuit via a transformer, and converts power between a primary side port of the primary side circuit and a secondary side port of the secondary side circuit, using switching of each of the primary side circuit and the secondary side circuit. The power conversion apparatus further includes a control unit that controls a frequency of the switching and a phase difference between the switching of the primary side circuit and the switching of the secondary side circuit such that power conversion efficiency between the primary side port and the secondary side port is increased.

Abstract: A power conversion apparatus includes: a primary side circuit; a secondary side circuit that is magnetically coupled to the primary side circuit by a transformer; and a control unit that adjusts a transmitted power transmitted between the primary side circuit and the secondary side circuit by changing a phase difference between a switching operation of the primary side circuit and a switching operation of the secondary side circuit such that a port voltage of one port from among a primary side port provided in the primary side circuit and a secondary side port provided in the secondary side circuit converges on a target voltage. The control unit reduces the target voltage when the phase difference is equal to an upper limit value and the port voltage is smaller than a set threshold.

Abstract: A power conversion apparatus includes a primary side circuit, a secondary side circuit that is connected to the primary side circuit through a reactor and magnetically coupled thereto through a transformer, and a control unit that adjusts power transmitted between the primary side circuit and the secondary side circuit by changing a phase difference between switching of the primary side circuit and switching of the secondary side circuit. The control unit adjusts the frequency of switching of the primary side circuit and the secondary side circuit according to the value of an equivalent inductance of the reactor and the transformer.

Abstract: A power conversion apparatus includes a plurality of power supply circuits each including a primary side circuit, and a secondary side circuit that is magnetically coupled to the primary side circuit via a transformer. Electrical power that changes according to a phase difference between switching of the primary side circuit and switching of the secondary side circuit is input and output to and from the power supply circuit. The power conversion apparatus includes a first power supply circuit, a second power supply circuit that uses, as an input side thereof, an output side of the first power supply circuit, and a control unit that adjusts residual power obtained by subtracting input power of the second power supply circuit from output power of the first power supply circuit, by controlling a phase difference of the first power supply circuit and a phase difference of the second power supply circuit.

Abstract: A LLC bidirectional resonant converter comprising: a resonant tank, a first switching circuit connected to the resonant tank via first power conduits, a second switching circuit connected to the resonant tank via second power conduits, a switching element, and at least one switchable inductive element which is arranged by the switching element to be in parallel across the second power conduits when operating in a first mode of operation and arranged by the switching element to be in parallel across the first power conduits when operating in a second mode of operation.

Abstract: Aspects of the disclosure provide a circuit that includes a detector and a controller. The detector is configured to detect a firing start by a triode for alternating current (TRIAC) in a power supply. The controller is configured to control a switch in connection with a magnetic component in response to the firing start to shape a profile of a current pulled from the power supply to satisfy a latch current requirement and a hold current requirement of the TRIAC.

Abstract: A switching power-supply device includes a COMP-voltage comparator circuit that compares a COMP-voltage obtained by performing phase compensation on the feedback signal, with a first threshold voltage which is a threshold value; and an intermittent-oscillation control circuit that, if it is detected by the COMP-voltage comparator circuit that the COMP-voltage is lower than the first threshold voltage, stops the switching operation of the switching device and performs a transition to a first intermittent oscillation operation in which the switching device performs the switching operation every predetermined first period, wherein if a predetermined delay period elapses in a state where the COMP-voltage is lower than the first threshold voltage, the intermittent-oscillation control circuit performs a transition to a second intermittent oscillation operation in which the switching device performs the switching operation every second period which is an integral multiple of the first period.

Abstract: A dc link module for a power circuit includes a first connector for connecting to a first power conversion circuit, a second connector for connecting to a second power conversion circuit, wherein the second power conversion circuit is connected to a load circuit arranged to at least intermittently operate as a power source to the power circuit, at least one dc link capacitors arranged between said first connector and said second connector for processing a voltage signal received at said first connector or said second connector, and at least one voltage compensation circuits arranged between said first connector and said second connector, said one or more voltage compensation circuits arranged to generate a voltage signal

Abstract: A direct current to alternating current inverter sub-system is for a HVDC distribution system. The DC to AC inverter sub-system includes an enclosure and a DC to DC galvanically isolated buck converter having a DC input electrically connectable to a HVDC cable and a DC output. A DC to AC inverter includes a DC input electrically connected to the DC output of the DC to DC galvanically isolated buck converter and an AC output electrically connectable to an AC transmission line. The DC to AC inverter is mounted in an enclosure with the DC to DC galvanically isolated buck converter, in order that the DC output of the DC to DC galvanically isolated buck converter is directly electrically connected within the enclosure to the DC input of the DC to AC inverter.

Abstract: A power converter module is provided. The power converter module includes a first converter leg and a second converter leg. The first converter leg includes a first switching unit and a second switching unit coupled in series. The second switching unit is disposed in a reverse orientation with respect to an orientation of the first switching unit. The second converter leg includes a third switching unit and a diode coupled in series. The third switching unit is disposed in a reverse orientation with respect to the orientation of the first switching unit. The power converter also includes a first energy storage device operatively coupled between the first converter leg and the second converter leg. The power converter module further includes a second energy storage device operatively coupled between the first converter leg and the second converter leg.

Abstract: A method of operating a power converter arrangement, the power converter arrangement includes a dc link and a dc load/source, an active rectifier/inverter having dc terminals connected to the dc link and is adapted to provide a variable dc link voltage between a maximum and a minimum limits, an interleaved buck converter having a plurality of converter circuits connected between the dc link and the dc load/source, wherein each converter circuit includes a first switch, a second switch, and a reactor, the method including determining one or more null values of dc link voltage with reference to the voltage across the dc load/source, and if a null value of dc link voltage is between the maximum and the minimum limits, controlling the active rectifier/inverter to provide a dc link voltage that is substantially the same as the null value of dc link voltage.

Abstract: An interleaved converter configured by connecting a plurality of switching converter circuits in parallel includes an inter-inductor switch that selects whether inductors are connected in series, an input side switch that is connected to a connection point of the inductor and the inter-inductor switch and selects whether electric power is supplied from a rectifier circuit to the inductor side, an output side switch that is connected to a connection point of the inductor and the inter-inductor switch and selects whether electric power is supplied from the inductor to the diode side, and a control circuit that controls the inter-inductor switch, the input side switch, and the output side switch.

Abstract: There is provided a rectifier circuit, including a rectifying unit rectifying input power to output rectified power corresponding to a magnitude of the input power and including a plurality of rectifier diodes, a first capacitor connected in parallel to any one of the plurality of rectifier diodes, a switch element connected to the first capacitor in series and controlling energy accumulation or discharge of the first capacitor according to a switching operation, and a controlling unit controlling the switch element based on the magnitude of the input power.

Abstract: Embodiments of the subject invention relate to a method and apparatus for providing a low-power AC/DC converter designed to operate with very low input voltage amplitudes. Specific embodiments can operate with input voltages less than or equal to 1 V, less than or equal to 200 mV, and as low as 20 mV, respectively. Embodiments of the subject low-power AC/DC converter can be utilized in magnetic induction energy harvester systems. With reference to a specific embodiment, a maximum efficiency of 92% was achieved for a 1 V input, and efficiencies exceeding 70% were achieved for a 200 mV input. A specific embodiment functioned properly when connected to a magnetic energy harvester device operating below 200 mV input.

Abstract: One or more variable configuration controller (VCC) systems may produce various combinations of series or parallel couplings of coils, winding or inductive elements of an electric machine such as a generator and/or electric motor. The VCC systems include a plurality of bridge rectifiers, and a first number of switches operated to selectively couple respective pairs of coils in series from parallel on an AC side of the bridge rectifiers. The bridge rectifiers provide for automatic electrical isolation of coils on occurrence of open circuit, low voltage or short circuit conditions. A second number of switches with different performance characteristics (e.g., speed, loss) than the first number of switches may be coupled in parallel with respective ones of the first number of switches. Power factor correction may be used.

Abstract: A power converter comprises a first diode, a second diode, a first capacitor, a second capacitor, and an AC switch. The first diode has a cathode terminal connected to a DC positive bus. The second diode has a cathode terminal connected to an anode terminal of the first diode, and an anode terminal connected to the DC negative bus. The first capacitor is connected between the DC positive bus and a neutral point. The second capacitor is connected between the DC negative bus and the neutral point. An AC switch is connected between the connection point of the first and second diodes, and the neutral point.

Abstract: A power supply circuit for a gate driving circuit for driving semiconductor switching devices of a power converter that is configured to perform a DC to AC conversion. The power supply circuit includes a DC power supply including a plurality of serially-connected single DC power supplies, a flying capacitor type power conversion circuit including a plurality of flying capacitors connected in parallel to a plurality of the semiconductor switching devices, and a plurality of serially-connected circuits each having an insulating device, a middle part of the series-connected circuits being connected to a middle potential point of the flying capacitors, and to a fixed potential point of the DC power supply.

Abstract: A ternary content-addressable cell is configured to compare an input binary data item present on an input terminal with two reference binary data items, and to output a match signal on a match line. The cell includes: a first storage circuit (storing a potential representing the first reference binary data item) and a second storage cell (storing a potential representing the second reference binary data item). A comparison circuit is connected to the first and second storage circuits and to the input terminal SL. A comparison node presents a potential representing the comparison of the input binary data item with the first and second reference data items. The comparison node is connected to an output stage, and the output stage is connected to the match line. The signal on the match line is based on the potential of the comparison node.

Abstract: Electronic component including a ternary content-addressable memory component, configured to compare the input data items with a set of pre-recorded reference data words; the memory component incorporates a matrix of elementary cells arranged in lines and columns; each line incorporates cells in each of which is recorded one bit of one of the reference data words; the cells of a given column are dedicated to the comparison of the same bit of the input data word; each cell incorporates: two memory points storing the data representing the reference data bit; a comparison circuit connected to the memory points, with a comparison point of which the potential represents the comparison if the input data bit and the data stored in the memory points, and also incorporating a common comparison circuit to which are connected the comparison circuits of all or part of the cells of a given column; the comparison circuit incorporates terminals to which the bit from the input data word and its complement are applied.

Abstract: A semiconductor cell comprises a plurality of metal layers. A first layer comprises a VDD conductor, a bit-line, and a complimentary bit-line. Each of the VDD conductor, the bit-line, and the complementary bit-line extend in a first direction. A second layer comprises a first VSS conductor and a first word-line. The VSS conductor and the first word-line extend in a second direction different than the first direction. A third layer comprises a second VSS conductor. The second VSS conductor extends in the first direction. A fourth layer comprises a second word-line. The second word-line extends in the second direction. The first word-line is electrically coupled to the second word-line.

Abstract: A semiconductor device includes a fuse array having a plurality of fuse sets suitable for outputting a plurality of fuse status signals having different levels according to whether fuses of the plurality of fuse sets are cut or not, a code counter suitable for counting selection codes in a preset order in response to an enable signal and an operation clock, and storage blocks suitable for receiving and storing the plurality of fuse status signals in a preset order in response to the selection codes.

Abstract: A method for reading the state of a memory element within a crossbar memory array includes storing a first electric current sensed from a half-selected target memory element within the crossbar memory array; and outputting a final electric current based on the stored first electric current and a second electric current sensed from the target memory element when the target memory element is fully selected.

Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises a memory cell block that includes a memory cell array, the memory cell array including: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; and a memory cell that is provided at each of intersections of the plurality of first lines and the plurality of second lines and includes a variable resistance element, the memory cell array further including a protective resistance film that is provided respectively at each of the intersections of the plurality of first lines and the plurality of second lines and that is connected in series with the memory cell and ohmically contacts the memory cell, and the protective resistance film being configured from a material having a resistivity of 1˜100 ?·cm.

Abstract: Methods for precharging bit lines using closed-loop feedback are described. In one embodiment, a sense amplifier may include a bit line precharge circuit for setting a bit line to a read voltage prior to sensing a memory cell connected to the bit line. The bit line precharge circuit may include a first transistor in a source-follower configuration with a first gate and a first source node electrically coupled to the bit line. By applying local feedback from the first source node to the first gate, the bit line settling time may be reduced. In some cases, a first voltage applied to the first gate may be determined based on a first current drawn from the first bit line. Thus, the first voltage applied to the first gate may vary over time depending on the conductivity of a selected memory cell connected to the bit line.

Abstract: A resistive switching memory device and a method for operating the same are disclosed. The device includes a plurality of resistive switching memory units arranged in a matrix, each of which includes a switching element and a resistive switching device, and the switching element being connected to a word line at its control terminal, to the resistive switching device at one terminal, and to a bit line at the other terminal; a word line decoder adapted to decode an input address signal to switch on the switching element in at least one of resistive switching memory units; and a driving circuit adapted to apply a voltage pulse whose front edge changes slowly across the resistive switching device by the bit line synchronously with the switching-on of the switching element.

Abstract: Various embodiments comprise apparatuses including drive circuitry to provide signal pulses of a selected time duration and/or amplitude to a number of memory cells. The memory cells may include an array of resistance change memory cells to be electrically coupled to the drive circuitry. The resistance change memory cells may be programmed for a range of retention time periods and operating speeds based on the received signal pulse. Additional apparatuses and methods are described.

Abstract: A memory comprises a two dimensional array of memory cells. Each memory cell comprises a first transistor, a second transistor and a capacitor. A multi-bit datum is stored as one of a plurality of voltage signal levels driven over a vertical input signal line and further across a source and a drain of the first transistor to be stored onto a gate of the second transistor. The first transistor is selected by a horizontal WR control line. The gate of the second transistor is connected to a first terminal of the capacitor. A second terminal of the capacitor is connected to a horizontal RD control line. The RD control line is driven to couple the second transistor to drive a signal onto a vertical output signal line during a read of the stored signal on the gate.

Abstract: Disclosed are devices, systems and/or methods relating to an eight transistor (8T) static random access memory (SRAM) cell, according to one or more embodiments. In one embodiment, an SRAM storage cell is disclosed comprising a word line, a write column select line, a cross-coupled data latch, and a first NMOS switch device serially coupled to a second NMOS switch device. In this embodiment, the gate node of the first NMOS switch device is coupled to the word line, a source node of the first NMOS switch device is coupled to the cross-coupled data latch, a gate node of the second NMOS switch device is coupled to the write column select line, and a source node of the second NMOS switch device is coupled to the cross-coupled data latch.

Abstract: A static random access memory structure is provided. The static random access memory structure includes a storage region having a first storage node and a second storage node which is complementary to the first storage node. The static random access memory structure also includes a reading region having a first reading transfer gate and a second reading transfer gate, and a reading word line electrically connecting with the gate of the first reading transfer gate and the gate of the second reading transfer gate. Further, the static random access memory structure includes a writing region independent of the reading region having a first writing transfer gate and a second writing transfer gate and a writing word line electrically connecting with the gate of the first writing transfer gate and the gate of the second transfer gate.

Abstract: A write method for a STT-RAM MTJ is disclosed that substantially reduces the bit error rate caused by intermediate domain states generated during write pulses. The method includes a plurality of “n” write periods or pulses and “n?1” domain dissipation periods where a domain dissipation period separates successive write periods. During each pulse, a write current is applied in a first direction across the MTJ and during each domain dissipation period, a second current with a magnitude equal to or less than the read current is applied in an opposite direction across the MTJ. Alternatively, no current is applied during one or more domain dissipation periods. Each domain dissipation period has a duration of 1 to 10 ns that is equal to or greater than the precession period of free layer magnetization in the absence of spin torque transfer current.

Abstract: A semiconductor storage device includes: a memory cell array in which a plurality of pairs of bit lines and source lines, a plurality of word lines, and a plurality of resistance change memory cells are arranged; a write driver, a sense amplifier, a global bit line and a global source line provided on a first end side; a plurality of bit line switches provided between the plurality of bit lines and the global bit line; a plurality of source line switches provided between the plurality of source lines and the global source line; a column decoder; a row decoder; a plurality of bit line ground switches provided between the plurality of bit lines and a ground line on a second end side; and a plurality of source line ground switches provided between the plurality of source lines and a ground line on the second end side.

Abstract: A Phase-Change Memory (PCM) includes a factory programming interface to receive data changing on both a positive transition and a negative transition of a dual edge clock. A transition detector generated internal clock provides a delayed edge to latch the program data. This dual-edge clock scheme provides a doubling in the data transfer rate.

Abstract: A semiconductor memory device includes memory cell strings including selection transistors and memory cells coupled between the selection transistors, a peripheral circuit configured to apply an operating voltage to the memory cell strings during a read operation or a verify operation, and a control circuit configured to control the peripheral circuit so that the operating voltage being applied to the selection transistors is controlled to reduce a potential level of a channel of the memory cell strings during the read operation or the verify operation.

Abstract: A method of operating a semiconductor memory device includes checking an erase-program cycling number, setting a target erase level to be maintained when the erase-program cycling number is less than a predetermined critical number, and setting the target erase level to be increased when the erase-program cycling number is greater than or equal to the predetermined critical number, and performing an erase operation so that threshold voltages of selected memory cells are less than the set target erase level.

Abstract: A memory controller identifies a predominant type of error of a memory unit of solid state memory cells. An error type differential is calculated. The error type differential is a difference between a number of charge loss errors and a number of charge gain errors of the memory unit. A VT offset error differential is calculated. The VT offset error differential is a difference between a number of errors of the predominant type at a first VT offset and a number of errors of the predominant type at a second VT offset. A VT offset is determined using a ratio of the error type differential and the VT offset error differential.

Abstract: A method for data storage includes accepting data for storage in an array of analog memory cells, which are arranged in rows associated with respective word lines. At least a first page of the data is stored in a first row of the array, and at least a second page of the data is stored in a second row of the array, having a different word line from the first row. After storing the first and second pages, a third page of the data is stored jointly in the first and second rows.

Abstract: Techniques are disclosed herein for performing an Internal Data Load (IDL) to sense non-volatile storage elements. Read pass voltages that are applied to the two neighbor word lines to a selected word line may be adjusted to result in a more accurate IDL. The read pass voltage for one neighbor may be increased by some delta voltage, whereas the read pass voltage for the other neighbor may be decreased by the same delta voltage. In one aspect, programming of an upper page of data into a word line that neighbors a target word line is halted to allow lower page data in the target memory cells to be read using an IDL and preserved in data latches while programming the upper page in the neighbor word completes. Preservation of the lower page data provides for a cleaner lower page when later programming the upper page into the target memory cells.

Abstract: An embodiment of an apparatus includes a substrate, a body semiconductor, a vertical memory access line stack over the body semiconductor, and a body connection to the body semiconductor.

Abstract: A nonvolatile memory device comprises a plurality of vertical NAND flash memory cells arranged in a three dimensional (3D) structure, a first memory block disposed in the 3D structure and having memory cells selected by a first ground selection line and a second ground selection line, wherein the first and second ground selection lines are electrically separated from each other, a second memory block disposed in the 3D structure and having memory cells selected by a third selection line and fourth selection line, wherein the third and fourth ground selection lines are electrically separated from each other, and a pass transistor that transfers a driving signal to turn on ground selection transistors respectively connected to the first and third ground selection lines in response to a block selection signal.