Abstract: A HiNAND array with a hierarchical-BL scheme configured to divide a large global bit line (GBL) capacitance into J number of small local bit line (LBL) capacitances for reducing bit line precharge voltage and discharge time to achieve faster Read and Program-Verify speed, lower power consumption, lower latency, and lower word line disturbance for a reliable DRAM-like latch sensing. A reduced precharge voltage can be increased by M-fold (M?2) using a Multiplier between each bitline and each Latch sense amplifier (SA). Between each Multiplier and each Latch SA, there is a Connector with two optional designs for either fully passing a sense voltage to the Latch SA with a same-polarity and value or reversing the polarity the sensing voltage with additional amplification. The Latch SA is configured to transfer stored threshold states of a memory cell into a bit of a page buffer.

Abstract: Apparatuses and methods for transposing select gates, such as in a computing system and/or memory device, are provided. One example apparatus can include a group of memory cells and select gates electrically coupled to the group of memory cells. The select gates are arranged such that a pair of select gates are adjacent to each other along a first portion of each of the pair of select gates and are non-adjacent along a second portion of each of the pair of select gates.

Abstract: A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.

Abstract: An EEPROM circuit includes a data reception register and a column decoder. A buffer memory having a size corresponding to the size of a data page is included between the data reception register and the column decoder.

Abstract: Memory, memory devices, and a method for a backup sequence are disclosed. In one such memory device, sense circuitry and page buffers are coupled between a three transistor memory cell device and a non-volatile memory device. Enable/disable gates enable selective access to the sense circuitry and page buffers by either the three transistor memory cell device or the non-volatile memory device.

Abstract: This invention discloses a 2T-string NOR-based CAM logic cell comprising two physical NAND cells connected in series with two horizontal WLs and one vertical BL and one vertical SL. Additionally, a sector of NOR-based CAM logic cell array is configured with N vertical cell strings each including M 2T-string NOR-based CAM logic cells connected in parallel sharing a local vertical SL and one dedicated vertical ML as an Operand word vertical page. Each 2T-string NOR-based CAM logic cell can be either a binary or ternary CAM cell associated with two or three physical states assigned to NAND cells' Vt levels for defining CAM logic states. Logic match of M-logic-bit inputs is found for at least one vertical page if the corresponding M 2T-string NOR-based CAM logic cells are in non-conduction state, providing M times faster Compare performance over the NAND-based CAM and 2 time faster than SRAM-based CAM.

Abstract: Memory devices and methods of operating memory devices are shown. Configurations described include a memory cell string having an elongated n type body region and having select gates with p type bodies. Configurations and methods shown can provide a reliable bias to a body region for memory operations such as erasing.

Abstract: A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line among word lines adjacent to the selected word line; and while applying a second pass voltage to the remaining unselected word lines (other than the at least one unselected word line to which the first pass voltage is applied). The level of the first pass voltage is higher than the level of the second pass voltage. The level of the first pass voltage may be set based on the level of the read voltage.

Abstract: A group of non-volatile, solid state memory cells are transferred from an active list that includes memory cells accessible to a host to a temporary list that includes memory cells temporarily inaccessible to the host. The memory cells included in the temporary list are maintained at a temperature that is substantially the same as or lower than that of memory cells included in the active list. The memory cells are transferred from the temporary list to the active list in response to satisfaction of a trigger condition.

Abstract: A semiconductor device includes a memory block coupled to word lines and configured to a memory cell including a floating gate, an inter-poly dielectric and a control gate and a peripheral circuit configured to perform an erase loop operation, a program loop operation an electron injection operation of the memory cell, the electron injection operation trapping electrons in the inter-poly dielectric.

Abstract: A semiconductor apparatus includes an input buffer configured to buffer data inputted through a data input/output pad; a data input control unit configured to transfer an output of the input buffer to a data input/output line in response to a write clock; a test loop control unit configured to output one of a signal of the data input/output line and test latch data in response to a test mode signal; a data output control unit configured to output an output of the test loop control unit in response to a read clock; an output inversion select unit configured to output an output signal of the data output control unit by inverting or non-inverting it; and an output buffer configured to buffer an output signal of the output inversion select unit and output a resultant signal to a node which is coupled with the data input/output pad and input buffer.

Abstract: The semiconductor device includes a pre-signal generator and a data output portion. The pre-signal generator generates a pre-input control signal and a pre-output control signal. The pre-signal generator also generates a pre-latch pulse signal by detecting when the pre-input control signal and the pre-output control signal are generated. The data output portion receives an input control signal, a latch pulse signal, and a first output control signal. The data output portion receives an input clock signal in response to the input control signal and the latch pulse signal to generate a shift clock signal, and the data output portion also shifts the first output control signal in response to the shift clock signal to generate a second output control signal.

Abstract: Semiconductor devices are provided. The semiconductor device includes a control signal generator and a first data input unit. The control signal generator generates an inverted control signal including a first bit and a second bit using a decoded signal in response to a test enable signal. The first data input unit inverts a first bit of input data in response to the first bit of the inverted control signal to generate a first bit of first internal data. Further, the first data input unit inverts a second bit of the input data in response to the second bit of the inverted control signal to generate a second bit of the first internal data.

Abstract: In one embodiment, a memory interface comprises a cleanup phase-locked loop (PLL) configured to receive a reference clock signal, and to generate a clean clock signal based on the reference clock signal. The memory interface also comprises a synchronization circuit configured to receive data, a data clock signal, and the clean clock signal, wherein the synchronization circuit is further configured to sample the data using the data clock signal, and to synchronize the sampled data with the clean clock signal.

Abstract: A method of performing a read operation on nonvolatile memory device comprises receiving a read command, receiving addresses, detecting a transition of a read enable signal, generating a strobe signal based on the transition of the read enable signal, reading data corresponding to the received addresses, and outputting the read data after the strobe signal is toggled a predetermined number of times.

Abstract: A semiconductor package includes first and second slave chips stacked vertically; and a master chip connected to the first and second slave chips, each of the slave chips including, a plurality of memory blocks, and a redundancy block, and the master chip including, a fuse block configured to repair a defective memory block detected from the first slave chip and a defective memory block detected from the second slave chip by using the redundancy block of the first slave chip and the redundancy block of the second slave chip, respectively, and a block selection circuit configured to, connect the redundancy blocks of the first and second slave chips, one or more non-defective ones of the plurality of memory blocks of the first slave chip, and one or more non-defective ones of the plurality of memory blocks of the second slave chip to an input/output circuit.

Abstract: Various embodiments include apparatus, systems, and methods having multiple dies arranged in a stack in which the dies or a logic chip in communication with the dies stores a flag for indicating whether a threshold number of cells of the dies have failed during test operations.

Abstract: Apparatuses and methods related to memory arrays with separate global read and write lines and/or sense amplifier region column select lines are disclosed. An example apparatus includes first and second memory sections, and further includes a sense amplifier region. A memory section includes a word line extending in a first direction and a digit line extending in a second direction, and the sense amplifier region is disposed between the first and second memory sections. The sense amplifier region includes a sense amplifier coupled to the digit line, a local input/output (LIO) line, a column select circuit coupled to the sense amplifier, and a column select line. The column select line extends in the first direction and is configured to provide a column select signal to the column select circuit. Capacitance of a LIO line may be reduced by coupling fewer sense amplifiers of a group to the LIO line.

Abstract: The present invention relates to a voltage regulator and to a method of operating a voltage regulator that is operable in a reset mode and in a sampling mode. The voltage regulator comprises: a capacitive voltage divider having a first capacitor and a second capacitor in series with the first capacitor, wherein the capacitive voltage divider is connectable to an output of a voltage supply to activate the sampling mode, a comparator having an output connected to an input of the voltage supply, the comparator further having a first input connected to a sampling node arranged between the first capacitor and the second capacitor and the comparator having a second input connected to a reference voltage, wherein the sampling node is connectable to the reference voltage for activating the reset mode.

Abstract: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.

Abstract: Apparatuses and methods including a plurality of memory units are disclosed. An example apparatus includes a plurality of memory units. Each of the plurality of memory units include a master/slave identification (ID) node coupled to a first voltage source node via a resistive element. Each of the plurality of memory units further include a master/slave ID circuit configured to determine whether a memory unit is a master memory unit or a slave memory unit based on a voltage level detected at the master/slave ID node. The master/slave ID node of each of the plurality of memory units other than a first memory unit is further coupled to a respective second voltage source node via a through—substrate via (TSV) of a respective adjacent memory unit of the plurality of memory units.

Abstract: A block selection circuit and a semiconductor device having the same may include a row decoder which includes a high voltage generating circuit configured to output a block selection voltage in response to upper addresses, switching circuits configured to receive the block selection voltage and aprecharge high voltage, and forward the block selection voltage through one of the switching circuits that is selected in response to selection signals, and pass transistor groups configured to select a memory block in response to the forwarded block selection voltage.

Abstract: Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency.

Abstract: A semiconductor memory device may include a memory cell array, a plurality of first sub word line drivers, and a plurality of second sub word line drivers. The memory cell array may comprise a plurality of sub cell arrays, a plurality of first word lines and a plurality of second word lines, wherein a loading of each of the first word lines is greater than a loading of each of the second word lines. Each of the plurality of first sub word line drivers may be connected to drive a corresponding one of the plurality of first word lines, wherein each of the first sub word line drivers has a first driving capability. Each of the plurality of second sub word line drivers may be connected to drive a corresponding one of the plurality of second word lines, wherein each of the second sub word line drivers has a second driving capability different from the first driving capability.

Abstract: A method and apparatus for the mixing of a solution and reagents for various reactions and/or testing having a closed cartridge reaction well, a magnetically responsive bead within the well having a chemically inert coating. A heat source then heats the contents to a target temperature while oscillating magnetic fields move the bead within the well in order to mix the contents and make the contents of the reaction well homogeneous.

Abstract: A static fluid and a second fluid are placed into contact along a microfluidic free interface and allowed to mix by diffusion without convective flow across the interface. In accordance with one embodiment of the present invention, the fluids are static and initially positioned on either side of a closed valve structure in a microfluidic channel having a width that is tightly constrained in at least one dimension. The valve is then opened, and no-slip layers at the sides of the microfluidic channel suppress convective mixing between the two fluids along the resulting interface. Applications for microfluidic free interfaces in accordance with embodiments of the present invention include, but are not limited to, protein crystallization studies, protein solubility studies, determination of properties of fluidics systems, and a variety of biological assays such as diffusive immunoassays, substrate turnover assays, and competitive binding assays.

Abstract: The ultrasound imaging system comprises an ultrasound probe (3) and computer (20) for controlling the ultrasound probe and for visualizing an image. The system comprises a processing device located between the probe and the computer that comprises a processing unit (15) to operate an imaging method and switch unit (13) for routing the input and output data.

Abstract: A transmit circuit outputs test pulses to a probe including a transducer to generate an image of a test object. A composite signal including the test pulses and a reflected signal is output by the transducer. A receive circuit receives the composite signal including the test pulses and the reflected signal and includes a filter circuit that filters the test pulses from the composite signal and passes the reflected signal. An impedance of the filter circuit is equal to substantially zero when the reflected signal is within a predetermined frequency range. A clipper circuit limits a magnitude of an output of the filter circuit. An amplifier amplifies the output of the filter circuit and that outputs an amplified voltage. A processing module generates a signal for displaying the image of the test object based on the amplified voltage.

Abstract: A towable and steerable elongated float for a marine seismic source arrangement for use in making a seismic survey at sea, having first attachment means at a lower or bottom part of a float body for allowing at least one seismic source to be suspended from the float, and second attachment means on a fore part of the float body for attachment of a strength taking source towing line or umbilical. The float body comprises first and second elongated steering foils being attached to and spaced from respective port and starboard sides of the fore part of said float body by respective support arrangement. The steering foils have respective longitudinal steering foil axes being oriented in a direction substantially perpendicular to a longitudinal axis of the float body and so as to be substantially perpendicular to a sea surface when in use, the elongated steering foils having respective first and second chord axes.

Abstract: A method of detecting seismic waves traveling through a subsurface formation includes lowering a cable into a borehole in the subsurface formation, the cable having at least one optical fiber associated therewith, and causing descent of a remote end of the cable to be arrested. The method further includes feeding a further length of the cable into the borehole such that the cable is slack and in contact with at least part of a wall of the borehole, and using an interrogator coupled to the at least one optical fiber to detect seismic waves traveling through the subsurface formation and into the cable.

Abstract: Techniques have been developed for transmitting and receiving information conveyed through the air from one portable device to another as a generally unperceivable coding within an otherwise recognizable acoustic signal. For example, in some embodiments in accordance with the present invention(s), information is acoustically communicated from a first handheld device toward a second by encoding the information in a signal that, when converted into acoustic energy at an acoustic transducer of the first handheld device, is characterized in that the acoustic energy is discernable to a human ear yet the encoding of the information therein is generally not perceivable by the human. The acoustic energy is transmitted from the acoustic transducer of the first handheld device toward the second handheld device across an air gap that constitutes a substantially entirety of the distance between the devices.

Abstract: The ultrasonic transducer device in accordance with the present invention includes a body unit and a fixing member. The body unit includes a housing including a space which is in a front surface of the housing and is for receiving an ultrasonic transducer, and a clip part provided to a side surface of the housing. The fixing member includes a fixing plate including a fixing surface to be attached to a rear surface of an exterior panel of a vehicle, and a through hole to communicate to an opening in the exterior panel, and an interlocked part removably connected to the clip part so that the space faces the through hole. The clip part includes an interlocking part, and a spring part keeping the interlocking part in a position in which the interlocking part is physically connected to the interlocked part.

Abstract: A method for generating acoustic waves under water includes actuating first and second pistons with an actuator system provided inside an enclosure of a source element, to generate a wave having a first frequency, and actuating the first and second pistons with a pressure mechanism attached to the enclosure, to control a pressure of a fluid inside the enclosure such that a pressure of the fluid is substantially equal to an ambient pressure of the enclosure. The enclosure has first and second openings and the first and second pistons are configured to close the first and second openings.

Abstract: Systems, methods, articles of manufacture and apparatus are disclosed to calculate distance from audio sources. An example method disclosed herein includes transmitting a first radio frequency (RF) signal to prompt a reference audio collecting device to begin collecting audio samples at a first time, initiating a dwell period in response to the first RF signal to reduce battery consumption of a portable audio collecting device by preventing the portable audio collecting device from collecting the audio samples at the first time, and when the dwell period expires, prompting the portable audio collecting device to collect the audio samples at a second time.

Abstract: An arrangement on a component of a motor vehicle, having a sensor with a substantially planar end surface, a sealing ring which encloses the sensor, and a carrier element for maintaining the spacing of the sensor in the axial direction relative to the component. The sensor extends with the sealing ring into a cut-out of the component. The sensor has a surrounding sealing ring, an additional ring element which lies further to the outside in a radial direction and has at least two cut-outs which are distributed over the circumference. The elastic ring element of the sealing ring or decoupling ring seals against water which enters from outside and for correct self-positioning in the cut-out of the component. The cut-outs according in the ring element, which lies on the outside, allow water which has entered to drain.

Abstract: A watch including: a case middle forming a transparent central region, a first and second display placed on each face of the watch; at least two transparent indicator plates placed in a pivoting fashion in the central region and including at least one indicator; a drive unit driving each indicator plate in rotation at its periphery; a holding element capable of holding each indicator plate at its periphery in a position roughly perpendicular to its rotation axis; the drive unit and holding element being housed completely in the case middle of the watch such that the drive unit and the holding element the are outside the central region; and said at least one indicator of each of the indicator plates is visible on one face so as to form the first display, and visible on the other face so as to form the second display.

Abstract: A timing device for indicating a passage of a duration of time is disclosed. The timing device in accordance with the embodiments of the invention has a grid array architecture. The grid array architecture includes an electrode structure with an anode layer, a cathode layer and a thermistor layer. The anode layer and the thermistor layer are electrically coupled through a plurality of cathode line structures. In operation the timing device is actuated through a suitable mechanism to initiate depletion of the anode layer and, thereby, indicate a passage of a duration time. As the anode layer depletes, sequential cathode line structures are exposed and the thermistor layer acts as a variable resistor through a plurality of exposed cathode line structures.

Abstract: A disk drive is disclosed comprising a disk and a head actuated over the disk, the head comprising a fly height actuator (FHA). The disk drive further comprises control circuitry including disk access circuitry, wherein during a calibration operation, the disk access circuitry is configured into a calibration mode that increases a heating of the head, and a fly height of the head is measured periodically to generate periodic fly height measurements that vary due to the heating of the head. A dynamic fly height (DFH) write profile is generated based on the periodic fly height measurements. During a write operation, the disk access circuitry is configured into a write mode and a DFH control signal is generated and applied to the FHA based on the DFH write profile.

Abstract: A data storage system, having a data processor operable to convert digital data signals into ink dot patterns, and a data processor operable to receive the ink dot patterns and convert them into digital signals, the system having at least one print media receiving carrier or panel, a printing member operable to deposit ink dot patterns in a print medium on the carrier panel, and a print media reader operable to read the ink dot patterns and create data signals there from, and a method of storing and retrieving data.

Abstract: A testing device for testing performance parameters of a disc player which includes a display, and a storage. The storage at least one sector table associated with a disc in the disc player, each sector table recording sector information corresponding to a plurality of physical sectors of the disc, a testing command associated with each physical sector, and a reference value range of each of performance parameters of the disc player. The testing command corresponding to the physical sector of the disk is obtained to be executed by the disc player to obtain a value of each performance parameter of the disc player. The testing device determines whether the disc player is qualified or not according to the obtained value.

Abstract: A method and apparatus for disc authentication are disclosed. The authentication method includes measuring at least one physical property of a data disc, which includes at least one of an angle and an eccentricity parameter associated with two data layers of a data disc, and authenticating the disc by determining whether a match exists between the measured property and encoded information on data layer the data disc relating to the physical property.

Abstract: A hard-disk drive having a structurally efficient magnetic head slider utilizes a MAMR-based spin torque oscillator (STO) for head-disk contact detection and for flying height sensing. Contact detection and spacing estimation techniques consider the nominal temperature difference, and thus different criteria, between read and write operations.

Abstract: In a multilayer optical disc having information layers conforming to a plurality of different optical disc standards, because the type of each information layer is not recorded in the other information layers, in read and write operations by a compatible optical disc device conforming to a plurality of optical disc standards, every time the information layer being accessed changes, it has been necessary to read the type of the information layer and select a method of generating a tracking error signal adapted to the type of information layer, so access has taken time. In order to solve the above problem, in the optical multilayer disc according to the present invention, having information layers conforming to a plurality of different optical disc standards, in an area in one of the information layers, information about the other information layers is recorded. The time required to access the other information layers can be reduced by using this information to select a tracking error signal generating method.

Abstract: The present disclosure provides an orthogonal codes based code division multiplexing method of performing the code division multiplexing of demodulation reference signals in multiple layers of resource blocks by using orthogonal matrices, the method comprising: changing the order of chips in particular rows of a first orthogonal matrix to obtain a second orthogonal matrix with the changed order of chips; and multiplying the chips in respective rows of the second orthogonal matrix by the demodulation reference signals in corresponding layers of resource blocks correspondingly in the time direction to obtain code division multiplexing signals. The technical scheme of the present disclosure can improve the power jitter situation of downlink signals on the time, thereby the usage efficiency of the power amplifier at the base station side can be improved.

Abstract: A base station apparatus for transmitting a reference signal in a wireless communication system is provided in which a processor generates the same sequence for resource elements (REs) allocated to each layer for reference signal transmission and spreads or covers Walsh codes for a user equipment-specific reference signal sequence such that sequences generated for the resource elements can be orthogonal to each other on a time axis. The Walsh code spreading or covering by the processor is applied on a frequency axis based on a plurality of resource blocks (RBs) or based on a pair of resource blocks such that mutually different sequences having mutually different sequence values can be mapped between resource blocks or between pairs of resource blocks. A transmission module transmits the reference signal, to which the generated reference signal sequence is applied to user equipment via each layer.

Abstract: A group of tourists traveling, for example, in a foreign land needs to be sure that no-one becomes lost. Embodiments of the present invention take advantage of mobile wireless terminals colloquially known as “smartphones” to quickly identify any members of a tour group that stray from the group, and to help them rejoin the group. Also, with the assistance of a Central Command Center, appropriate authorities such as a tour leader or relatives can be automatically notified, and search operations initiated if needed.

Abstract: The network including functional nodes (10) connected in series by a data transmitter (11; 12), in which the data assumes the form of discrete messages propagating from node to node in the network, is characterized in that the a data transmitter (11; 12) between the nodes are bidirectional to allow data to propagate in both circulation directions of the network, and each node (10) includes at least one first and one second port associated by programming, for data input/output (13, 14), connected to adjacent nodes by a corresponding data transmitter (11; 12) and the operation of which is controlled exclusively and sequentially, by a communication automaton (15), between an operating mode for the asynchronous reception of data from the adjacent nodes, and an operating mode for the synchronous transmission of data to the nodes adjacent thereto.

Abstract: A data transmitting device coupling to a plurality of nodes in a network includes a plurality of communication paths, the data transmitting device includes a memory and a processor coupled to the memory configured to set a routing table based on a command that designates a first communication path included in the plurality of communication paths, to detect a link failure occurred in the network, and when the link failure has occurred at a first location between the data transmitting device and a first node adjacent to the data transmitting device on the first communication path, to modify the routing table so that data are to be transmitted to a second node on a second communication path different from the first communication path, and when the link failure has occurred at a second location that differs from the first location in the network, to maintain the routing table.

Abstract: A VRRP router group can operate in either a standard VRRP mode or a distributed gateway mode in which all VRRP routers generate VRRP control packets but transmit those packets only to local access network-side hosts. The rate of VRRP control packet generation may be decreased in the distributed gateway mode relative to the standard mode. Moreover, VRRP router CPUs may cease processing of VRRP control packets in the distributed gateway mode.

Abstract: A network system according to the present invention includes a backbone network that is constituted by combining a plurality of switch devices, and a subnetwork that is constituted by a plurality of switch devices connected linearly, where the switch devices positioned at both ends of the linear connection are connected to the backbone network, wherein among physical ports included in the switch devices that constitute the backbone network, a first physical port that is one of two physical ports to which the subnetwork is connected blocks a packet with a specific logical port number having arrived from a specific direction, and passes other packets, and a second physical port that is the other of the two physical ports passes a packet with the specific logical port number having arrived from the specific direction, and blocks other packets.