Abstract: A method and an apparatus for controlling a grid-connected converter which includes a boost converter, a buck converter, and a current source inverter having an output CL filter. An input of the buck converter input is connected to an output of the boost converter, and an input of the current source inverter is connected to an output of the buck converter. The method includes controlling a boost converter input voltage, controlling a boost converter output voltage through control of a buck converter output voltage, and controlling the current source inverter to produce an AC current from the buck converter output voltage. The apparatus implements the method.

Abstract: The present invention relates to a double-output half-bridge LLC serial resonant converter, comprising: a half-bridge rectifying unit, a first resonant unit, a first transformer unit, a first rectifying unit, a first output unit, a second resonant unit, a second transformer unit, a second rectifying unit, a second output unit, a voltage dividing unit, a voltage regulating unit, a light-coupling isolation unit, and a control unit. In the present invention, the double-output half-bridge LLC serial resonant converter has an inventive circuit framework, which can not only solve the unbalance load current and the output voltage cross regulation occurred in the conventional double-output convertor, but also normally modulate the no-load or light-load output voltage; therefore the output voltage deviation can be effectively controlled.

Abstract: Systems, apparatuses, and techniques for pulse width modulation (PWM) are described. A described system includes a circuit that contains an inductor and a transistor that controls current through the inductor based on a PWM signal to produce an output; and a controller to provide the PWM signal, which includes PWM cycles that include on-durations and off-durations. The controller can receive a first signal indicating an input voltage that is applied to the inductor, receive a second signal indicating a current through the inductor, use an on-duration parameter value to control the on-duration, determine a maximum off-duration of the off-durations corresponding to the PWM cycles occurring within a first voltage cycle, the first voltage cycle being defined between two consecutive zero-crossing events as indicated by the first signal, and adjust the on-duration parameter value for a second, subsequent voltage cycle based on the maximum off-duration to regulate the output voltage.

Abstract: A multi-level converter includes a plurality of alternating current (AC) terminals connected to an AC source or load, at least three direct current (DC) terminals connected to a multi-level DC source or load, and a plurality of solid-state switches that are selectively turned On and Off to connect each of the plurality of AC terminals to one of the DC terminals. A controller provides PWM control signals to the solid-state switches. The controller utilizes space vector modulation to organize the various switching state configurations, and increments the switching states during a first half of the switching period and decrements the switching states during a second half of the switching period to center-align the PWM signals provided about the center of the switching period. The switching states utilized during the switching period dictate the PWM control signals provided to the plurality of switches employed in the three-level converter.

Abstract: An inverter circuit contains a first and second DC sources for providing a DC voltage, a common boost converter for boosting the DC voltage, an intermediate circuit capacitor connected between the outputs of the common boost converter, and an inverter for converting the DC voltage provided by the capacitor into an AC voltage. The common boost converter contains a series circuit having a first inductance and a first rectifier element and is connected between an output of the first DC source and one side of the intermediate circuit capacitor as well as a series circuit which includes a second inductance and a second rectifier element and is connected between an output of the second DC source and another side of the intermediate circuit capacitor. The common boost converter further contains a common switching element formed by at least two circuit-breakers which are connected between the first and second DC sources.

Abstract: A capacitor discharger applied to a power conversion system including a DC voltage source, a power conversion circuit having a pair of input terminals via which the DC voltage source is electrically connected to the power conversion circuit, and a capacitor electrically connected between the pair of input terminals of the power conversion circuit. The capacitor discharger includes a first series connection of resistive elements and a second series connection of resistive elements. In the capacitor discharger, a parallel connection of the first and second series connections of resistive elements is electrically connected between the pair of input terminals of the power conversion circuit. This can ensure a discharge path for discharging the capacitor even in the presence of an abnormality in a portion of the parallel connection of the first and second series connections of resistive elements.

Abstract: A main circuit of a three-level active neutral point clamped voltage source converter having a pair of additional main switches provides two paths between an output node and a neutral point in which one of the paths involves only switches of an inner pair of switches that are operated at a high frequency. An auxiliary circuit operating at a high frequency for only a brief period during each high frequency switching cycle selects the path involving only the inner switches and provides operation with zero voltage switching and avoids reverse recovery of diodes connected antiparallel with the main and additional main switches. Accordingly, turn-on switching losses in the main switches is avoided and the voltage source converter can be operated at increased frequency to allow reduction in size of magnetic components and full potential power transfer to be achieved.

Abstract: A ternary content addressable memory (TCAM) is formed by TCAM cells that are arranged in an array. Each TCAM cell includes a first and second SRAM cells and a comparator. The SRAM cells predominantly in use have a horizontal topology with a rectangular perimeter defined by longer and shorter side edges. The match lines for the TCAM extend across the array, and are coupled to TCAM cells along an array column. The bit lines extend across the array, and coupled to TCAM cells along an array row. Each match line is oriented in a first direction (the column direction) that is parallel to the shorter side edge of the horizontal topology layout for the SRAM cells in each CAM cell. Each bit line is oriented in a second direction (the row direction) that is parallel to the longer side edge of the horizontal topology layout for the SRAM cells in each CAM cell.

Abstract: Low leakage CAMs and method of searching low leakage CAMs. The method includes performing a pre-search and compare on a small number of pre-search bits with pre-search CAM cells powered to normal voltage levels at all times while the main-search CAM cells are powered to a lower voltage level. Only if a match is detected on the pre-search bits are the main-search CAM cells powered-up to normal voltage levels and the search of the main-search bits activated. The main-search CAM cells are powered to normal voltage levels during read and write operations.

Abstract: A multi-chip package includes a first group of memory chips that includes a first memory chip and a second memory chip, a second group of memory chips that includes at least one memory chip, a first internal wiring system that couples the first memory chip and the second memory chip to a first terminal configured to receive a chip-enable signal, a second internal wiring system that couples the at least one memory chip to a second terminal configured to receive the chip-enable signal. The first memory chip and the second memory chip each include a chip address memory region configured to store an address associated with the memory chip, and an address rewrite module configured to rewrite the address associated with the memory chip and stored in the chip address memory region in response to an external operation.

Abstract: A stacked semiconductor memory device is provided which includes a first memory chip including a first transmission line, a second transmission line, and a logic circuit configured to execute a logic operation on a first signal of the first transmission line and a second signal of the second transmission line. The stacked semiconductor memory device further includes a second memory chip stacked over the first memory chip, an inter-chip connection unit electrically coupled between the second memory chip and the first transmission line of the first memory chip, and a dummy inter-chip connection unit electrically coupled to the second transmission line of the first memory chip and electrically isolated from the second memory chip.

Abstract: A memory system includes a plurality of memory devices on a printed circuit board, each of the memory devices including a plurality of external pads; a plurality of connection terminals formed on the printed circuit board, and electrically connected to respective ones of the external pads; and a plurality of signal lines formed on the printed circuit board to connect the connection terminals with the external pads, each of the signal lines between a corresponding connection terminal and a corresponding external pad and having a length. The plurality of memory devices are arranged at different distances from the plurality of connection terminals, and each signal line that connects a connection terminal to an external pad of a memory device either is connected to or does not connect a stub resistor depending on a length of the line.

Abstract: Memory devices, memory arrays, and methods of operation of memory arrays with segmentation. Segmentation elements can scale with the memory cells, and may be uni-directional or bi-directional diodes. Biasing lines in the array allow biasing of selected and unselected select devices and segmentation elements with any desired bias, and may use biasing devices of the same construction as the segmentation elements.

Abstract: The present disclosure provides a reference one time programmable (OTP) cell, wherein the reference OTP cell can generate a reference bias current in at least a programmed-on configuration; a current mirror coupled to an output of the OTP cell, wherein the current mirror includes at least two gate-coupled field effect transistors (FETs); wherein a current gain of a second of the two FETS is a fraction less than one of a first of the at least two gate-coupled FETs; a programmable OTP memory bit element (OTPMBE) coupled to an input of the current mirror; and a comparator having an input coupled to a node between the OTPMBE and the current mirror.

Abstract: Junction diodes fabricated in standard CMOS logic technologies can be used as program selectors for a programmable resistive device, such as electrical fuse, contact/via fuse, anti-fuse, or emerging nonvolatile memory such as MRAM, PCM, CBRAM, or RRAM. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a high voltage to the P terminal of a diode and switching the N terminal of a diode to a low voltage for proper duration of time, a current flows through a resistive element in series with the program selector may change the resistance state. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI isolations. If the resistive element is an interconnect fuse based on CMOS gate material, the resistive element can be coupled to the P+ active region by an abutted contact such that the element, active region, and metal can be connected in a single rectangular contact.

Abstract: The present disclosure provides a resistive-switching device capable of implementing multiary addition operation and a method for implementing multiary addition operation using the resistive-switching device. The resistive-switching device has a plurality of resistance values each corresponding to a respective data value stored by the resistive-switching device and ranging from a high resistance value to a low resistance value. The data value stored by the resistive-switching device is increased by ‘1’ successively with a series of set pulses having a same pulse width and a same voltage amplitude being applied thereto. The data value stored by the resistive-switching device is set to ‘0’ with a reset pulse being applied thereto, and meanwhile a data value stored by a higher-bit resistive-switching device is increased by ‘1’ with a set pulse being applied thereto. In this way, multiary addition operation is implemented.

Abstract: A resistive memory device includes a resistive memory cell, and a read/program circuit configured to program the resistive memory cell from a first state to a second state. The read/program circuit reads a resistance in the first state of the resistive memory cell and adjusts a compliance current supplied to the resistive memory cell according to the read resistance during the program operation.

Abstract: Apparatuses and methods of forming a memory cell is described. In one such method, a forming charge applied to a memory cell, such as a Resistive RAM (RRAM) memory cell, is monitored to determine the progress of the forming the cell. If the cell is consuming charge too slowly, a higher voltage can be applied. If the cell is consuming charge too quickly, a lower voltage can be applied. The charge may be monitored by charging a capacitor to a certain level, then monitoring the discharge rate of the capacitor though the cell. The monitoring may use comparators to measure the charge. The monitoring may also use an analog to digital converter to perform the monitoring.

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal.

Abstract: A write and/or read current generator for nonvolatile memory device, especially for Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM), may include a current supplying circuit which changes a level of a sample current, determines a resistance state change current of a sample bit cell based on a feedback signal obtained through the sample bit cell whose resistance state is changed according to a level of the sample current. The current supplying circuit may calibrate a write and/or read current of a memory cell in response to a sample current applied at a point of time when a resistance state of the sample bit cell is switched into another resistance state. A calibration circuit may generate the feedback signal indicating a resistance area of a predetermined resistance range to which a resistance state of the sample bit cell belongs.

Abstract: A storage device in which held voltage is prevented from decreasing due to feedthrough in writing data to the storage device at high voltage is provided. The storage device includes a write circuit, a bit line, a word line, a transistor, and a capacitor. A gate of the transistor is electrically connected to the word line. One of a source and a drain of the transistor is electrically connected to the bit line. The other of the source and the drain of the transistor is electrically connected to one terminal of the capacitor. The other terminal of the capacitor is electrically connected to a ground. The write circuit includes an element holding write voltage and a circuit gradually decreasing voltage from the element holding write voltage. The write voltage is output from the write circuit to the word line.

Abstract: A device, comprising: first and second signal lines; first and second transistors of first conductivity type coupled in series between first and second signal lines and coupled to each other at first node; third and fourth transistors of second conductivity type coupled in series between first and second lines and coupled to each other at second node; power supply node coupled in common to first and second nodes; fifth transistor of first conductivity type coupled between first and second signal lines; and sixth transistor of second conductivity type coupled between first and second signal lines, wherein each of first, second and fifth transistors is configured to receive first control signal at gate electrode thereof, each of the third and fourth transistors is configured to receive second control signal at gate electrode thereof, and sixth transistor is configured to receive third control signal at gate electrode thereof.

Abstract: A memory cell is provided. The memory cell comprises a write port and a read port. The write port comprises a pair of cross-coupled inverters and a plurality of metal lines. The first inverter comprises a first pull-up device and a first pull-down device. The second inverter comprises a second pull-up device and a second pull-down device. The metal lines comprise a Vcc conductor line, a first Vss conductor line, and a second Vss conductor line. The first pull-down device has a source terminal coupled to the first Vss line. The second pull-down device has a source terminal coupled to the second Vss line. The read port comprises a cascaded device, a read word line, read bit line and a third Vss conductor line. The cascaded device comprises a read pull-down device and a read pass device. The read pull-down device has a source terminal coupled to the third Vss conductor line. The read pass device has a drain terminal coupled to the read bit line.

Abstract: The present invention provides a magnetic memory element that has a spin valve structure formed using a free layer, a non-magnetic layer, and a pinned layer. The free layer has a three-layer structure having a first magnetic layer, an intermediate layer, and a second magnetic layer arranged in this order viewed from the non-magnetic layer. The first magnetic layer is made of a ferromagnetic material. The intermediate layer is made of a non-magnetic material. The second magnetic layer is made of an N-type ferromagnetic material having a magnetic compensation point in the temperature range where a memory storage operation can be available. The magnetization direction of the first magnetic layer and the magnetization direction of the second magnetic layer are parallel to each other at the temperature lower than the magnetic compensation point Tcomp.

Abstract: A write driver for writing to a spin-torque magnetoresistive random access memory (ST-MRAM) minimizes sub-threshold leakage of the unselected (off) word line select transistors in the selected column. An effective metal resistance in the bit line and/or source line is reduced and power supply noise immunity is increased. Write driver bias signals are isolated from global bias signals, and a first voltage is applied at one end of a bit line using one of a first NMOS-follower circuit or a first PMOS-follower circuit. A second voltage is applied at opposite ends of a source line using, respectively, second and third PMOS-follower circuits, or second and third NMOS-follower circuits.

Abstract: A memory array that includes a SOI substrate and lateral bipolar junction transistors (BJTs) fabricated on the SOI substrate. The BJTs form first and second inverters cross coupled to form a memory cell. A read circuit outputs the binary state of the memory cell. A power supply is configured to supply a Vdd voltage to the read circuit and to supply a Vcc and a Vee voltage to the first set of lateral bipolar transistors and the second set of lateral bipolar transistors, wherein the Vee voltage is at least zero volts and the Vcc voltage is greater than the Vee voltage and is equal to or less than the Vdd voltage.

Abstract: A method of programming a NAND flash memory cell string. The method includes a pre-boost stage configured to elevate channel voltage of a selected memory cell, and a boost stage is introduced after the pre-boost stage. The pre-boost stage has at least the following steps of biasing a bit line to a first voltage, biasing a string select transistor to a second voltage; and ramping down the string select transistor to the first voltage. In particular, the second voltage is higher than the first voltage.

Abstract: A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.

Abstract: One or more embodiments of 8T NVSRAM cell are provided for improving NVSRAM memory architecture with reduced cell size as opposed to the prior art of 12T NVSRAM cell. This novel 8T NVSRAM cell uses one step Write operation under either a FN-channel write scheme to increase a paired flash transistor Vt values in positive direction with a desired ?Vt12 ?1V or a FN-edge write scheme to decrease the Vt values in negative direction with a similar desired ?Vt12?1V to write the ?Vt12 into the paired flash transistors within 1-10 ms without requiring a pre-erase step. There is no need of Program-Inhibit Voltage (SBPI) to inhibit non-select flash transistor from programming. In addition, this 8T NVSRAM cell uses DRAM-like charge-sensing scheme to detect the ?V on Q and QB nodes of SRAM in which is coupled and generated from the ?Vt12 stored in MC1 and MC2 flash transistors.

Abstract: In a method of operating a memory circuit, which includes a plurality of memory arrays each coupled with a corresponding input/output (IO) interface and a redundancy memory page a failing address of a failing bit cell is determined. The failing address is located in a memory page of one of the memory arrays. The method further includes repairing the failing bit cell by replacing the memory page with the redundancy memory page.

Abstract: An indication of a page type which failed error correction decoding is received. A threshold to adjust is selected from a plurality of thresholds based at least in part on the page type. A third adjusted threshold associated with the page type is generated, including by: determining a first number of flipped bits using a first adjusted threshold associated with the page type, determining a second number of flipped bits using a second adjusted threshold associated with the page type, and generating the third adjusted threshold using the first number of flipped bits and the second number of flipped bits.

Abstract: Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device is described including a memory array including a plurality of blocks of memory cells. The device also includes a controller to perform a leakage-suppression process. The leakage-suppression process includes determining that a given block of memory cells includes one or more over-erased memory cells. Upon the determination, the leakage-suppression process also includes performing a soft program operation to increase the threshold voltage of the over-erased memory cells in the given block.

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.

Abstract: Erasing memory cells in certain 3-D NAND charge-storage memory arrays is achieved by rapidly charging vertical conductors using Gate Induced Drain Leakage (GIDL) current generated in select transistors. When bit line voltage drops below its nominal value, select line voltage is controlled to maintain a constant voltage difference between bit line voltage and select line voltage thus maintaining a gate-drain voltage difference in select transistors that provides sufficient GIDL current for erase.

Abstract: Programming accuracy is increased for select gate transistors and memory cells by using a dynamic verify voltage which increases from an initial level to a final level during a programming operation. Faster-programming transistors are locked out from programming before slower-programming transistors, but experience program disturb which increases their threshold voltage to a common level with the slower-programming transistors at the conclusion of the programming operation. For programming of memory cells to different target data states, an offset between the initial and final verify levels can be different for each data state. In one approach, the offset is greater for lower target data states. The increases in the dynamic verify voltage can be progressively smaller with each subsequent program-verify iteration of the programming operation. The start of the increase can be adapted to the programming progress or can be at a predetermined program-verify iteration.

Abstract: A flash memory module may include a plurality of flash memory chips. The memory chips may include one or more blocks. Each block may be a unit of erasing data. A flash controller may be coupled to the plurality of flash memory chips. The flash controller may program data to block and erase data from a block. The flash controller may manage a recent programming time for each of the plurality of blocks. The flash controller may erase data stored in a block for which an elapsed programming time is larger than a first value.

Abstract: According to one embodiment, a control circuit of a memory cell array is configured to write data to a memory cell array by applying a first write pass voltage, which is lower than the program voltage, to a first group of nonselective word lines adjacent to a selective word line. The control circuit is further configured to apply a second write pass voltage, which is higher than the first write pass voltage, to a second group of second nonselective word lines, the second group not including the word lines of the first group.

Abstract: Provided is a programming method of a nonvolatile memory device. The nonvolatile memory device includes a substrate and a plurality of memory cells which are stacked in the direction perpendicular to the substrate.

Abstract: A mass storage device includes a controller configured to communicate with a host. The controller is coupled to a first memory and a second memory, the first and second memories being of different types. The mass storage device includes a storage media partitioned into a plurality of Logical Units (LUNs) based on capabilities and resources of the mass storage device. The mass storage device further includes the first memory and the second memories and a hybrid reserved area spanning at least a portion of the first and second memories.

Abstract: Methods, apparatuses, and systems for comparing threshold voltages of a plurality of flash memory cells to a plurality of reference voltages. A number of flash memory cells having threshold voltages that fall within each bin of a plurality of bins is determined. The plurality of bins each represent a plurality of threshold voltage ranges. A threshold voltage distribution of the plurality of flash memory cells is calculated based at least in part on the number of flash memory cells that fall into each of the bins.

Abstract: A semiconductor memory device includes a plurality of memory blocks configured to include memory cells, a voltage supply circuit configured to supply an erase voltage for an erase operation of a memory block selected from the memory blocks and supply an erase verify voltage and an erase pass voltage for an erase verify operation of the memory block selected from the memory blocks, and a control logic configured to group word lines per specific word lines, when the erase verify operation for the selected memory block is performed, and control the voltage supply circuit so that one or more of the erase verify voltage and the erase pass voltage rise whenever the erase verify operation is performed.

Abstract: The semiconductor memory device includes a memory cell block including a plurality of memory cells, a peripheral circuit section configured to perform an erase loop including a supply operation supplying an erase voltage and an erase verification operation to erase data stored in the memory cells, a fail bit counter configured to count the number of memory cells not erased in an erase operation among the memory cells to generate a count signal based on a fail count corresponding to a counting result in the erase verification operation, and a controller configured to control the peripheral circuit section to set a new erase voltage by increasing an erase voltage, used in a previous erase loop, by a first step voltage or decreasing the erase voltage by a second step voltage based on the fail count, and perform the erase loop using the new erase voltage.

Abstract: A nonvolatile memory apparatus includes: a memory cell area including a plurality of memory cells connected to a word line and a bit line; a program time controller configured to determine a program voltage application time for a selected word line, as the selected word line is selected in response to a program command and an address signal; and a controller configured to apply a program voltage to the selected word line according to the program voltage application time determined by the program time controller.

Abstract: A flash memory device may include two or more flash memory cells organized as a NAND string in a block of flash memory cells, and flash cells, coupled to the NAND string at opposite ends, to function as select gates. The flash memory device may be capable of providing information related to a voltage threshold of the select gates to a flash controller, erasing the flash cells that function as select gates in response to a select gate erase command, and programming the flash cells that function as select gates in response to a select gate program command.

Abstract: A method of retiming a circuit that includes a RAM having data stored therein, a register following the RAM, and registers preceding the RAM for registering input, address and enable signals of the RAM includes pushing a value in the register following the RAM back into a memory location in the RAM, pushing back data stored in the RAM and initial values in the registers preceding the RAM to accommodate the value pushed back from the register following the RAM, and setting new values in the registers preceding the RAM so that, on a first clock cycle after retiming, the circuit assumes a condition before retiming. The method also may be used to configure a programmable logic device with a user logic design.

Abstract: Disclosed are various apparatuses and methods for a memory with a multiple read word line design. A memory may include a plurality of bit cells arranged in a row, a first read word line connected to a first subset of the plurality of bit cells, and a second read word line connected to a second subset of the plurality of bit cells, wherein the first and second subsets are located in the same row of bit cells. A method may include asserting, during a first read operation, a first read word line connected to a first subset of a plurality of bit cells arranged in a row of bit cells, and asserting, during a second read operation, a second read word line connected to a second subset of the plurality of bit cells, wherein the first and second subsets are located in the same row of bit cells.

Abstract: A semiconductor structure includes a first strap cell, a first read port, and a first VSS terminal. The first strap cell has a first strap cell VSS region. The first read port has a first read port VSS region, a first read port read bit line region, and a first read port poly region. The first VSS terminal is configured to electrically couple the first strap cell VSS region and the first read port VSS region.

Abstract: A semiconductor memory device includes memory cells for storing data, page buffers each configured to comprise a dynamic latch and a static latch on which data to be programmed in to the memory cells or data read from the memory cells are latched, and a control logic configured to store a plurality of refresh mode select codes corresponding to various refresh cycles, and refresh the dynamic latch by exchanging data between the static latch and the dynamic latch according to a refresh cycle corresponding to a selected refresh mode select code.

Abstract: A semiconductor memory device includes an internal clock generation unit configured to generate an internal clock including periodic pulses during a period of a test mode; a DQ information signal generation block configured to generate DQ information signals which are sequentially enabled, in response to the internal clock; and a data output block configured to output the DQ information signals to DQ pads during a period of the test mode.

Abstract: Circuitry to provide a supply voltage. A voltage regulator is coupled to receive a target reference signal. The voltage regulator generates a supply voltage (Vtt) and is coupled to receive the supply voltage as an input signal. An upper limit comparator receives an upper limit voltage signal that is higher than the target reference voltage signal and the supply voltage to generate a “too high” signal when the supply voltage exceeds an upper threshold. A lower limit comparator receives a lower limit voltage signal that is lower than the target reference voltage signal and the supply voltage to generate a “too low” signal when the supply voltage is below a lower threshold. A pull up current source is coupled to pull the supply voltage up in response to the too low signal. A pull down current source is coupled to pull the supply voltage down in response to the too high signal.