Abstract: A tester system is disclosed. The tester system comprises a tester module operable to generate test signals for testing a plurality of DUTs. It also comprises a plurality of cables operable to communicatively couple the tester module with a tray comprising the plurality of DUTs through a thermal chamber wall interface. Further, it comprises a plurality of connectors in contact with the tray, wherein the plurality of connectors is operable to provide an interface between the plurality of cables and conductive traces on the tray, and further wherein each of the plurality of connectors is operable to pass a respective subset of the test signals to each DUT on the tray via the conductive traces.

Abstract: A semiconductor device includes: a first circuit; a first power switch provided either between a power supply potential terminal and a power supply potential node of the first circuit or between a reference potential terminal and a reference potential node of the first circuit; a power switch control circuit configured to control a voltage of a control terminal of the first power switch; a test terminal; and a first test control circuit configured to control connection of the test terminal and the control terminal of the first power switch.

Abstract: A testing apparatus includes a base mounted on a motherboard, an inserting unit mounted on the base, a movable unit secured to the inserting unit, and a driving device mounted between the movable unit and the base. The movable unit is driven to move by the driving device, thereby enabling the inserting unit to move to enable the expansion card to be inserted into the motherboard. The movable unit is driven to move by the driving device, thereby enabling the inserting unit to move to enable the expansion card to move out of the motherboard.

Abstract: A high frequency probe card for probing a photoelectric device includes a substrate having a first opening and at least one first through hole, an interposing plate disposed on the substrate and having a second opening and at least one second through hole, a circuit board disposed on the interposing plate and having a third opening and at least one third through hole, and a probe module mounted to the substrate and having at least one ground probe and at least one high-frequency impedance matching probe having a signal transmitting structure and a grounding structure passing through the at least one first, second and third through holes and being electrically connected with a signal pad and a ground pad of the circuit board, respectively. The first, second and third openings are communicated with each other for light transmission.

Abstract: A board for a probe card includes a ceramic board including a first insulating layer, and second insulating layers disposed on one surface of the first insulating layer and including cavities for receiving electronic components, conductive patterns disposed on the first and second insulating layers, conductive vias electrically connecting the conductive patterns, and a capacitor disposed in the cavities. The cavities have a depth greater than a thickness of the capacitor to secure a space in a lower portion of the cavity after receiving the capacitor.

Abstract: The present invention proposes a testing method for testing a semiconductor element, including: providing a semiconductor element having a first surface on which a first testing area is formed and a second surface on which a second testing surface is formed; placing the semiconductor element on a plane surface, allowing any one of the first surface and the second surface to be in no parallel to the plane surface; and electrically connecting a testing apparatus to the first testing area and the second testing area of the semiconductor element. The semiconductor element is placed in a non-horizontal manner on the testing apparatus, which makes contact with the two opposing surfaces of the semiconductor element in a horizontal way without directly exerting a downward force against the surface of the semiconductor element, thereby preventing the semiconductor element from damages.

Abstract: A semiconductor device includes a through silicon via (TSV) formed in a semiconductor substrate including a first-type impurity; and a first doping region formed in the semiconductor substrate located below the TSV. The first doping region is configured to include a second-type impurity and selectively electrically coupled to the TSV.

Abstract: A touch panel and a method thereof are provided. The touch panel includes a touch sensor, a shielding layer, and a plurality of conducting foils. The shielding layer is disposed on the touch sensor. The plurality of conducting foils is disposed via an Anisotropic Conductive Film (ACF) on a surface of the shielding layer, which is on an opposite side of a surface of the touch sensor. Any two of the plurality of conducting foils, the ACF, and the shielding layer are connected in series as a signal path.

Abstract: A circuit and method for detecting a brown-out condition and providing a feed-forward transfer function in a power supply circuit. A comparison circuit is coupled to a delay element through a latch. A second delay element is connected between the first delay element and an input of the latch. The output of the first delay element is connected to a clamping circuit via a logic circuit. A first voltage is compared with a reference voltage to generate a comparison voltage, which is transmitted through the latch and the first delay element. The comparison voltage is monitored at an output of the first delay element. A brown-out condition occurs if the comparison voltage being monitored at the output of the first delay element results from the first voltage being less than the reference voltage.

Abstract: A semiconductor component includes a semiconductor substrate, and a doped well having a well terminal and a transistor structure having at least one potential terminal formed in the semiconductor substrate. The transistor structure has a parasitic thyristor, and is at least partly arranged in the doped well. The potential terminal and the well terminal are connected via a resistor.

Abstract: A packaged component may include an interposer and integrated circuit dies mounted on the interposer. At least one of the dies may be a radiation-hardened integrated circuit die, whereas the remaining dies may be non-radiation-hardened dies. If desired, the interposer may be a radiation-hardened interposer whereas the integrated circuit dies may be non-radiation-hardened dies. The radiation-hardened die or the radiation-hardened interposer may include monitor circuitry that is used to test non-radiation-hardened circuitry of the packaged component. Test results may be stored in a database at the monitor circuitry or transmitted to external devices such as a server. The monitor circuitry may be used to reconfigure failed circuitry or may control multiplexing circuitry in the interposer to functionally replace the failed circuitry. If desired, the monitor circuitry may adjust power consumption of non-radiation-hardened circuitry based on the test results.

Abstract: Disclosed is a wafer-level stacked chip assembly, comprising a plurality of chip layers vertically stacked together with vertically electrical interconnections between the adjacent chip layers realized by TSVs (Through Silicon Via). Each chip layer includes a switching mechanism for selectively bypassing chip coding sequence to deactivate failed IC area and its chip coding sequence, thereby the interconnection relationship among the chip layers can be re-defined and the function and chip code of the failed IC area can be deactivated. Accordingly, any known failed chip in the wafer-level stacking chip assembly can be controlled as a dummy chip to realize the wafer-level chip stacking of non-known good dices with exclusion of failed chip(s).

Abstract: The present invention relates to a multiplexer comprising at least a first input and a second input and one output connected to the first input via a first pass gate and to the second input via a second pass gate, wherein the first pass gate comprises at least a first double-gate transistor, and the second pass gate comprises at least a second double-gate transistor, and each of the first and second double-gate transistors has a first gate controlled based on a first control signal and a second gate controlled based on a second control signal. The invention further relates to a look-up table and a and an FPGA based on the multiplexer.

Abstract: Methods and apparatuses are disclosed for driving a node to one or more elevated voltages. One example apparatus includes a first driver circuit configured to drive a node to a first voltage, and a second driver circuit configured to drive the node to a pumped voltage after the node reaches a voltage threshold. The apparatus also includes a controller circuit configured to disable the first driver circuit and enable the second driver circuit responsive to the node reaching the voltage threshold.

Abstract: A methodology for controlling FET switch-on with VGS temperature compensation is based on establishing a VGS clamping voltage with PTAT and CTAT voltage references with complimentary temperature coefficients. In one embodiment, the methodology can include: (a) generating a PTAT current from a PTAT ?VBE current source including a ?VBE resistor; (b) supplying the PTAT current to the gate node to control FET switch-on; and (c) establishing a temperature compensated VGS clamping voltage at the gate node. The VGS clamping voltage can be established with gate control circuitry that includes the PTAT and CTAT voltage references. A PTAT voltage VPTAT is dropped across a PTAT resistor RPTAT characterized by a temperature coefficient substantially the same as the ?VBE resistor. The CTAT voltage VCTAT is dropped across one or more CTAT VBE component(s) each characterized by a VBE,CTAT voltage drop with a CTAT temperature coefficient.

Abstract: An improved gate drive circuit is provided for a power device, such as a transistor. The gate driver circuit may include: a current control circuit; a first secondary current source that is used to control the switching transient during turn off of the power transistor and a second secondary current source that is used to control the switching transient during turn on of the power transistor. In operation, the current control circuit operates, during turn on of the power transistor, to source a gate drive current to a control node of the power transistor and, during turn off of the power transistor, to sink a gate drive current from the control node of the power transistor. The first and second secondary current sources adjust the gate drive current to control the voltage or current rate of change and thereby the overshoot during the switching transient.

Abstract: A voltage-controlled oscillator (VCO) comprises a supply voltage node, configured to receive a supply voltage, a VCO output capacitor, configured to provide an oscillating output voltage across the capacitor, a discharge switch configured to discharge the capacitor according to an oscillation frequency of the oscillating output voltage, and a comparator circuit configured to provide, to a control terminal of the discharge switch, a control signal that is determined based on a comparison of the output voltage and a specified threshold voltage. The oscillating output voltage includes a pulse having a ramp slope that is determined as a function of a magnitude of the supply voltage, and is capable of being adjusted independently of the oscillation frequency.

Abstract: A drive circuit is provided with an input terminal for receiving input signals, an output terminal that outputs drive signals generated from the input signals, a control power supply terminal that receives a control power supply voltage, an output terminal that outputs an output signal, and a reset terminal that receives a reset signal. The output signal is given to a gate of a MOSFET. A secondary side circuit and a MOSFET constitute a step-down chopper circuit, which steps down a voltage through duty ratio control of the gate drive signal and generates a control power supply voltage. Upon receipt of a reset signal, the drive circuit stops outputting the drive signal and changes the output signal so as to reduce the control power supply voltage VCC.

Abstract: The present invention provides a digitally controlled oscillator device capable of realizing a reduction in DNL. The digitally controlled oscillator device includes, for example, an amplifier circuit block, coil elements and a plurality of unitary capacitor units coupled in parallel between oscillation output nodes. Each of the unitary capacitor units is provided with capacitive elements, and a switch which selects whether the capacitive elements should be allowed to contribute as set parameters for an oscillation frequency. The switch is driven by an on/off control line extending from a decoder circuit. The on/off control line is shielded between the oscillation output nodes by a shield section.

Abstract: A flip-flop circuit may include a master latch and a slave latch. Each latch may have a transparent mode and a storage mode. The slave latch may be in storage mode when the master latch is in transparent mode; and vice-versa. A clock signal may control the mode of each latch through a pair of clock-gated pull-up transistors and a pair clock-gated of pull-down transistors, for a total of four clock-gated transistors. The clock-gated transistors may be shared by the master latch and the slave latch. Fewer clock-gated transistors may be required when they are shared, as opposed to not being shared. Clock-gated transistors may have parasitic capacitance and consume power when subjected to a varying clock signal, due to the charging and discharging of the parasitic capacitance. Having fewer clock-gated transistors thus may reduce the power consumed by the flip-flop circuit.

Abstract: Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase interpolator. The more linear slope on the output of the push-pull buffer may improve the linearity of a phase interpolator using the dock signals output from the push-pull buffers.

Abstract: A circuit for skewing differential signals includes a coarse adjustment stage configured to receive a differential input signal having a true component and a complement component, the coarse adjustment stage configured to impart a first controllable delay to at least one of the true component and the complement component of the differential signal, and a fine adjustment stage configured to impart a second controllable delay to at least one of the true component and the complement component of the differential signal, the second controllable delay having a resolution different than a resolution of the first controllable delay, the first controllable delay and the second controllable delay providing a timing skew between the true component and the complement component of the differential signal.

Abstract: A delay circuit includes first and second transistors and a biasing circuit. The first transistor has a control node coupled to an input node of the delay circuit, a first main current node coupled to a first supply voltage, and a second main current node coupled to an output node of the delay circuit. A second transistor has a control node coupled to the input node, a first main current node coupled to a second supply voltage, and a second main current node coupled to the output node. The biasing circuit is configured to generate first and second differential control voltages , to apply the first differential control voltage to a further control node of the first transistor and to apply the second differential control voltage to a further control node of the second transistor.

Abstract: The application discloses a voltage regulation method, and a corresponding HPM, chip, and chip system. The method is used to regulate a working voltage of the chip, which includes an AVS module and at least one HPM. The method includes: outputting, by the AVS module, a clock signal to the HPM; generating, by the HPM, a corresponding pulse signal according to the clock signal and at least performing first delaying for the pulse signal to acquire a first actual output value and performing second delaying for the pulse signal to acquire a second actual output value; and fitting, by the AVS module, the first and second actual output values at least according to weights of the first and second actual output values to acquire a fitting output value and determine, by comparing the fitting output value with a predetermined reference value, whether to regulate the working voltage of the chip.

Abstract: Embodiments of the invention provide IGBT circuit modules with increased efficiencies. These efficiencies can be realized in a number of ways. In some embodiments, the gate resistance and/or voltage can be minimized. In some embodiments, the IGBT circuit module can be switched using an isolated receiver such as a fiber optic receiver. In some embodiments, a single driver can drive a single IGBT. And in some embodiments, a current bypass circuit can be included. Various other embodiments of the invention are disclosed.

Abstract: A gate driving circuit for a display is disclosed. The gate driving circuit utilizes at least one transistor connected in series between an input end of a reference voltage signal and a transistor connected to a node providing a high voltage level for making the at least one transistor share the voltage difference between the source electrode and the drain electrode of the transistor connected to the node. In such a manner, the gate driving circuit can reduce the occurrence of current leakage in the transistor, thereby improving the stability of driving voltage of the gate driving circuit and the reliability of the gate driving circuit.

Abstract: A sequence circuit includes first through third signal terminals, first through ninth resistors, and first through fifth electronic switches. The sequence circuit receives a first signal through the first signal terminal. The sequence circuit receives a second signal through the second signal terminal. The sequence circuit outputs a third signal through the third signal terminal. The sequence circuit is used to ensure the sequence of the first through third signals.

Abstract: An embodiment of an apparatus, such as a circuit breaker, includes an input node, an output node, and a digital circuit. The input node is configured to receive an input voltage, and the output node is coupled to the input node and is configured to carry an output current. And the digital circuit is configured to uncouple the output node from the input node in response to a power drawn from the input node exceeding a threshold.

Abstract: A circuit which is constituted by a plurality of n-channel transistors includes, in at least one embodiment, a transistor (T1) which has a drain terminal to which an input signal is supplied and a source terminal from which a output signal is supplied; and a transistor (T2) which has a drain terminal to which a control signal is supplied and a source terminal connected to a gate terminal of the transistor (T1). A gate terminal of the transistor (T2) is connected to the source terminal of the transistor (T2). With the arrangement, it is possible to provide (i) a semiconductor device which is constituted by transistors having an identical conductivity type and which is capable of reducing an influence of noise, and (ii) a display device including the semiconductor device.

Abstract: Various embodiments include approaches for controlling a supply voltage or a clock frequency to an integrated circuit (IC). Various additional embodiments include circuitry for controlling a supply voltage or a clock frequency of an IC. In some cases, a method includes: locating a set of temperature sensors on bin locations in an IC; determining temperature bounds of the bin locations in the IC as a function of a determined temperature at the set of temperature sensors; determining timing constraints as a function of supply voltages at the bin locations and the determined temperature at the set of temperature sensors; and determining operational voltage bounds for the IC as a function of the determined temperature at the set of temperature sensors.

Abstract: A charge pumping device includes unit cells. Each unit cell includes first and second cells, each including a charge transfer circuit, a switch controlling a charge transfer operation thereof, and a charge storage circuit having a first end connected to an output terminal of the charge transfer circuit. The switch of the first and second cell is controlled by a first and second clock and the output terminal of the second and first cell, respectively. The first and second clocks are inputted to a second end of the charge storage circuit of the second and first cells, respectively. A first interface circuit connects first and second cells of a first unit cell to second and first cells of a second unit cell, respectively. Output terminals of a final unit cell connect to a load capacitor. Input terminals of an initial unit cell connect to a supply voltage.

Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.

Abstract: An integrated circuit has a semiconductor layer, at least one metal layer, a plurality of functional circuit blocks formed on the semiconductor layer, and a power mesh formed on the at least one metal layer. The power mesh has a specific area corresponding to a specific functional circuit block of the functional circuit blocks. The specific area at least has a first power trunk of a first power source and a second power trunk of a second power source distributed therein.

Abstract: This invention makes the change in current drawn from the power grid in an integrated circuit gradual by sequencing the power switch chains differently for both power up and power down. During power up, this invention establishes a reasonable connection with the power grid through a series of weak power switches and then starts turning on the strong power switches. During power down, this invention reverses the process. Strong switches are all turned off before turning off the weak switches.

Abstract: An embodiment of a semiconductor integrated circuit, which receives a power supply voltage at an input terminal and outputs a feedback voltage for controlling a level of the power supply voltage, includes a feedback voltage generating unit that generates the feedback voltage corresponding to the level of the power supply voltage at the input terminal. The feedback voltage generating unit includes a variable resistance element. A resistance control unit controls the resistance value of the variable resistance element to account for changes in a desired target level for the power supply voltage.

Abstract: Traditionally, designs have been very conservative on power grid design using higher margins than those needed for safe operation. This is especially true for process driver designs which may not have enough data on process characteristics. This invention allows us to recoup these inefficiencies and to speed up the power up/power down dynamically. This invention sequences plural power supply switches serially or in plural parallel sets as set by a wake up mode.

Abstract: The optimal low power complex filter, as a second order complex filter, is based on current amplifiers (CAs) and is utilized to implement a 4th order current-mode filter that can be used for intermediate frequency (IF) applications, such as, for example, low-IF Bluetooth receivers. Fabricated in a standard 0.18 ?m CMOS technology, experimental results show that the present design offers improved characteristics over the existing solutions in terms of power consumption and spurious-free dynamic range (SFDR). The 4th order filter exhibits in-band SFDR of 65.8 dB while consuming only 1 mW.

Abstract: Devices and methods to reduce adjacent channel power of an amplifier are described. The adjacent channel power can be reduced by considering the third harmonic output from the amplifier, and minimizing such third harmonic amplitude by implementing a phase shifter feedback circuit to the amplifier. The phase shifter feedback circuit can shift the phase of the feedback signal in order to reduce the third harmonic amplitude, which in turn reduces the adjacent channel power.

Abstract: To generate amplitude modulation to phase modulation (AMPM) predistortion data that compensates for phase distortion in a power amplifier of a communication device, a test signal is amplified via the power amplifier. The amplified test signal is combined, by wave superposition, with a reference oscillator signal into a resultant signal. The resultant signal is an outcome of interference between the amplified test signal and the reference oscillator signal. The resultant signal power is measured using envelope information and, from the measurement, a predistortion phase shift is determined that when applied to the test signal maximizes the interference between the amplified test signal and the reference oscillator signal. AMPM predistortion data is generated to correspond with the predistortion phase shift.

Abstract: A distortion compensation apparatus compensates for non-linear distortion of a power amplifier. The distortion compensation apparatus includes a pre-distorter, a learning unit, and a gain control unit. During training of the pre-distorter, the learning unit repeatedly updates a compensation coefficient on the basis of signals output from the power amplifier. While the training continues after update of the compensation coefficient, the gain control unit performs gain control on a signal before input to the power amplifier.

Abstract: A device includes a Doherty amplifier. The Doherty amplifier has a carrier path and a peaking path. The Doherty amplifier includes a carrier amplifier configured to amplify a signal received from the carrier path and a peaking amplifier configured to amplify a signal received from the peaking path. The device includes a resistive switch having a first terminal connected to the peaking path and a second terminal connected to a voltage reference, and a controller configured to set the resistive switch to a first resistance value when a power input of the Doherty amplifier is below a threshold and to a second resistance value when the power input of the Doherty amplifier is above the threshold.

Abstract: A differential input circuit (FIG. 3A) is disclosed. The circuit includes a first input terminal (drain of 310) and a second input terminal (drain of 312). A first input transistor (310) has a first control terminal and has a current path coupled to the first input terminal. A second input transistor (312) has a second control terminal and has a current path coupled to the second input terminal. A third transistor (306) has a third control terminal and has a current path between a first differential input terminal (Vin+) and the first control terminal. A fourth transistor (308) has a fourth control terminal and has a current path between a second differential input terminal (Vin?) and the second control terminal.

Abstract: A charge preamplifier for converting an electric charge generated in a charge source sensor into a voltage signal, including: a phase inverting amplifier including an input related to the charge source sensor, and an output for providing the voltage signal; a storage capacitor connected between the input and the output of the phase inverting amplifier; a reset system connected to the input of the phase inverting amplifier, for providing to the storage capacitor a discharging current as a function of a control signal, and a control element including: a first input connected to the output of the phase inverting amplifier, for withdrawing the voltage signal, a second input subjected to a reference voltage, a set of components configured and arranged to generate a control signal proportional to the deviation between the voltage signal and the reference voltage, the proportionality coefficient being lower than one in a high frequency band, an output connected to the reset system to provide thereto the control sign

Abstract: An implementation of an operational amplifier circuit includes a first stage amplifier circuit, a second stage amplifier circuit and a first feedforward circuit. The first stage amplifier circuit is coupled to a first input node for receiving a first input signal and amplifying the first input signal to generate a first amplified signal. The second stage amplifier circuit is coupled to the first stage amplifier circuit for receiving the first amplified signal and amplifying the first amplified signal to generate a first output signal at a first output node. The first feedforward circuit is coupled between the first input node and the second stage amplifier circuit for feeding the first input signal forward to the second stage amplifier circuit.

Abstract: The programmable multi-gain current amplifier circuitry includes a pair of MOS transistors setting the voltage at X terminal to zero using negative feedback formed by a third MOS transistor. Input resistance is in the range of few tens of ohms. The input current ix, which is forced by the constant currents of the circuitry, is conveyed to the output port Z by source-coupling a complementary output pair of MOS transistors. Since this coupled pair is biased with a constant tail current, the drain current changes are equal but with opposite sign, regardless of their matching resulting in negative type CA with unity gain (iz=ix). Programmability is achieved utilizing the output stages. When a second differential pair is connected in parallel, it provides two additional current outputs. With the two differential pairs being biased with different tail currents (IT1 and IT2), the outputs are programmed by adjusting these tail currents.

Abstract: A scalable periphery digital power control arrangement is presented. The scalable periphery digital power control arrangement comprises a plurality of PMOS transistors connected in parallel, where the plurality of transistors is operatively coupled to a voltage source. The plurality of PMOS transistors that is operatively coupled to the voltage source can operate as a controlled current source. Current flow from the voltage source can be controlled by a logic circuit, which sends a logic signal to enable or disable each individual PMOS transistor of the plurality of PMOS transistors connected in parallel. As more PMOS transistors are enabled, the current flow through the scalable periphery digital power control arrangement to the amplifier can increase.

Abstract: A signal receiver includes a current source providing a current having a current value, a pair of active input devices, and a pair of resistors. Each active input device includes a control node, a first conduction node, and a second conduction node. One of the control nodes receives an input signal. The first conduction nodes are connected to each other and receive the current. One of the second conduction nodes serves as an output node. The active input devices output an output signal to a core circuit according to the current and the input signal. Each resistor has a resistance value. A target voltage value is determined according to the resistance value and the current value, such that a voltage swing of the output signal is limited within the target voltage value, and an operating voltage of the core circuit is substantially equal to the target voltage value.

Abstract: In RF power transistors, the current distribution along edges of the transistor die may be uneven leading to a loss in efficiency and in the output power obtained, resulting in degradation in performance. When multiple parallel dies are placed in a package, distribution effects along the vertical dimension of the dies are more pronounced. A RF power device (600) for amplifying RF signals is disclosed which modifies the impedance of a portion of the respective one of the input lead and the output lead and redistributes the current flow at an edge of the transistor die.

Abstract: The disclosed invention is intended to adjust the driving power of an oscillation circuit to be optimal with a simple circuit configuration. A chip includes an oscillation circuit, an amplifier, an effective value measuring circuit, and a control unit. The oscillation circuit includes an inverting amplifier and a resistor coupled in parallel to the inverting amplifier. The oscillation circuit in which the inverting amplifier is coupled to a crystal oscillator outside the chip generates an oscillation circuit by driving the crystal oscillator. The effective value measuring circuit measures an effective value of an oscillation signal produced by the oscillation circuit. The control unit controls the gain of the inverting amplifier so that the effective value will be equal to a target voltage.

Abstract: A PLL device includes a variable frequency oscillator and a frequency divider section. The variable frequency oscillator varies an oscillation frequency in response to a control signal including information on a phase difference between a reference signal and a frequency division signal and oscillates an output signal obtained by multiplying a frequency of the reference signal. The frequency divider section frequency-divides the output signal to generate the frequency division signal. An injection locked frequency divider is arranged in the frequency divider section, the control signal is input to the injection locked frequency divider, and the operation frequency of the injection locked frequency divider is controlled by the control signal.