Abstract: A DC/DC resonant converter system includes a primary converter unit having a split resonant tank circuit. The resonant converter unit further includes a plurality of primary switching units that control the current flowing into the split resonant tank circuit. A controlled secondary rectifier unit includes a plurality of rectifier switching units to reduce reactive power in the primary converter unit. A phase-shift controller is in electrical communication with the primary converter unit and the controlled secondary rectifier unit. The phase-shift controller is configured to determine a rectifier phase-shift angle based on the plurality of primary switching units and to control switching of the plurality of rectifier switching units based on the rectifier phase-shift angle.

Abstract: An electric power source device has a transformer, a primary-side semiconductor module, a secondary-side semiconductor module, a secondary-side electrical component, a base plate and a circuit substrate on which substrate-side electrical components are mounted. The primary-side semiconductor module has a larger exterior size than the secondary-side electrical component. The primary-side semiconductor module and the secondary-side electrical component form a stacked section. In the stacked section, the secondary-side electrical component is stacked, in a vertical direction, i.e. a direction of a normal line of a mounting surface of the base plate, on the primary-side semiconductor module. The primary-side semiconductor module is directly mounted on the mounting surface.

Abstract: A digital control unit generates a control signal to control a duty cycle of a switched mode power supply such that a faster response to an input voltage transient is achieved. The digital control unit comprises a feedback compensator, a feed forward compensator, a transient detector, and a controller. The transient detector receives a signal indicative of the input voltage of the switched mode power supply and detects transients on the received signal. The feedback compensator receives a signal indicative of the output voltage of the switched mode power supply and adjusts the control signal. The feed forward compensator receives a signal indicative of the input voltage of the switched mode power supply, performs a relatively fast, but coarse, adjustment of the control signal, and then performs a more accurate, but relatively slow, adjustment of the control signal.

Abstract: The invention relates to a voltage converter (100), including: a plurality of two-way conversion cells (303), each cell comprising a primary circuit (307, Wp), and a secondary circuit (308, Ws) that is insulated from the primary circuit, wherein each circuit can be separately activated in order to supply an output voltage from the converter; and at least one control circuit (306) configured to, in a first operating mode, control the activated cells in order to transfer electrical energy from the primary circuit to the secondary circuit, and control the inactivated cells in order to transfer electrical energy from the secondary circuit to the primary circuit.

Abstract: On the secondary side of a flyback switching power converter, a compensation diode and a voltage divider with an averaging circuit generate an output current-compensated reference voltage that is proportional to converter output current. The current-compensated reference voltage is added to a regulation feedback controller reference voltage, which in turn adjusts the negative feedback signal to the PWM regulation controller on the primary side in proportion to the converter output current draw. The net effect is to increase the converter output voltage set-point in proportion to the converter output current draw as compensation for a voltage drop in a cable connecting the converter to a powered device. More precisely-regulated voltage levels may be delivered to an input of the powered device as a result.

Abstract: A controller for generating jitters in a quasi resonant mode includes a feedback pin, a voltage generation unit, a pulse generator, and a comparator. The feedback pin is used for receiving a feedback voltage from a secondary side of a power converter. The voltage generation unit is used for generating a first voltage according to the feedback voltage and a pulse. The pulse generator is used for generating the pulse when a control signal controlling a power switch of a primary side of the power converter is enabled. The comparator is used for controlling enabling and disabling of a switching signal according to the first voltage and a variable reference voltage. The variable reference voltage is monotonously swung within a predetermined range according to a digital signal.

Abstract: A power control device includes a first terminal, a second terminal connected to a transmission line, a first cascade multilevel inverter (CMI) and a second CMI. The first CMI is connected to the second terminal. The second CMI connected in series between the first terminal and the second terminal.

Abstract: The invention comprises a high frequency inductor filter apparatus coupled with an inverter yielding high frequency harmonics and/or non-sixty Hertz output. For example, an inductor/converter apparatus is provided using a silicon carbide transistor that outputs power having a carrier frequency, modulated by a fundamental frequency, and a set of harmonic frequencies. A filter, comprising an inductor having a distributed gap core material and optional magnet wires, receives power output from the inverter/converter and processes the power by passing the fundamental frequency while reducing amplitude of the harmonic frequencies.

Abstract: An embodiment of the present invention is directed to an integrated electromagnetic compatibility (EMC) filter and power line communication (PLC) interface. The EMC filter and PLC interface comprises a first filter winding and a second filter winding configured as a common mode choke; and a two-part winding on the common mode choke, wherein the two-part winding comprises (i) a first winding coupled proximate the first filter winding and (ii) a second winding coupled proximate the second filter winding, wherein the first winding and the second winding have an equal number of turns, and wherein phasing of the first winding is reversed with respect to the second winding.

Abstract: A power controller in a multi-chip module is disclosed. The power controller comprises a power controller die, an ultra-high voltage startup die, and a multi-chip module. The power controller die is operable to control a power switch when powered by an operation power source. The operation power source has a maximum voltage limit of tens volt. The ultra-high voltage startup die comprises an ultra-high voltage pad tolerable to receiving an input line voltage higher than one hundred volt. During a startup procedure the ultra-high voltage startup die charges the operation power source, and during a normal operation the ultra-high voltage startup die substantially performs an open-circuit. The multi-chip module packages both the power controller die and the ultra-high voltage startup die.

Abstract: An AC to DC power supply is provided based on feedback control of an analog current blocking (ACB) device. The ACB element receives rectified high voltage AC. The output of the ACB element is provided to an integrating circuit that provides an output DC voltage. The output DC voltage depends on the average current passed by the ACB element. The average current passed by the ACB element depends on the current limit of the ACB element, which is under feedback control.

Abstract: Methods, systems, circuits, and devices for power-packet-switching power converters using bidirectional bipolar transistors (BTRANs) for switching. Four-terminal three-layer BTRANs provide substantially identical operation in either direction with forward voltages of less than a diode drop. BTRANs are fully symmetric merged double-base bidirectional bipolar opposite-faced devices which operate under conditions of high non-equilibrium carrier concentration, and which can have surprising synergies when used as bidirectional switches for power-packet-switching power converters. BTRANs are driven into a state of high carrier concentration, making the on-state voltage drop very low.

Abstract: An automatic equalization method and apparatus for bus bar voltages of a Power Factor Correction (PFC) circuit. The method includes calculating a difference in voltages of a positive bus bar and a negative bus bar, and increasing the rotation speed of a fan in the PFC circuit according to the difference in voltages of the positive bus bar and the negative bus bar until the voltages of the positive and negative bus bars are equalized. The apparatus includes a voltage difference module configured to calculate a difference in voltages of a positive bus bar and a negative bus bar, and a rotation speed control module configured to increase a rotation speed of a fan in the PFC circuit according to the difference in voltages of the positive bus bar and the negative bus bar, until the voltages of the positive and negative bus bars are equalized.

Abstract: The present invention relates to a rectifier circuit with a three-phase rectifier arrangement (1) of semiconductor valves (2), preferably a bridge rectifier circuit of diodes, wherein the rectifier arrangement (1) comprises a three-phase mains input (3) and a DC output (4), and at least one of the three phases (U, V, W) at the mains input (3) is connected to a first pole connection (A) of a three-pole circuit (5) for diverting an injection current (ih3) into the three-pole circuit (5).

Abstract: A power supply device of the invention includes a first switching leg including first and second switching elements between DC terminals; a second switching leg including third and fourth switching elements between the DC terminals; a first capacitor leg including first and second capacitors between the DC terminals; a second capacitor leg including third and fourth capacitors between AC terminals; a first inductor between a connection of the first and second switching elements and one of the AC terminals; a second inductor between a connection of the third and fourth switching elements and another of the AC terminals; a controller; an AC power supply connected to the AC terminals and the connection of the third and fourth capacitors; and a DC power supply between the DC terminals, wherein the controller charges the first and second capacitors to a voltage higher than a voltage crest of the AC power supply.

Abstract: A semiconductor memory cell includes a set of circuit structures, each having column input/output circuits. The semiconductor memory cell further includes a set of replicas corresponding to the column input/output circuits. The set of replicas are non-functional and fills an empty space next to the column input/output circuits and hence, provides context protection for the column input/output circuits.

Abstract: Some embodiments include apparatus and methods having dice arranged in a stack. The dice include at least a first die and a second die, and a connection coupled to the dice. The connection may be configured to transfer control information to the first die during an assignment of a first identification to the first die and to transfer the control information from the first die to the second die during an assignment of a second identification to the second die.

Abstract: The present disclosure includes memory cell array structures and methods of forming the same. One such array includes a stack structure comprising a memory cell between a first conductive material and a second conductive material. The memory cell can include a select element and a memory element. The array can also include an electrically inactive stack structure located at an edge of the stack structure.

Abstract: A device includes a first power supply line supplying a first voltage, first, second, and third nodes, a selection circuit connected between the first power supply line and the first node, a first anti-fuse connected between the first node and the second node, and a second anti-fuse connected between the first node and the third node. The second node and the third node are not connected to each other.

Abstract: A programmable resistive device cell using at least one MOS device as selector can be programmed or read by turning on a source junction diode of the MOS or a channel of the MOS. A programmable resistive device cell can include at least one programmable resistive element and at least one MOS device. The programmable resistive element can be coupled to a first supply voltage line. The MOS can have a source coupled to the programmable resistive element, a bulk coupled to a drain, a drain coupled to a second supply voltage line, and a gate coupled to a third supply voltage line. The programmable resistive element can be configured to be programmable or readable by applying voltages to the first, second, and/or third supply voltage lines to turn on the source junction of the MOS and/or to turn on the channel of the MOS.

Abstract: A mask-programmed read-only memory (MROM) has a plurality of column line pairs, each having a bit line and a complement bit line. The MROM includes a plurality of memory cells corresponding to a plurality of intersections between the column line pairs and a plurality of word liens. Each memory cell includes a high Vt transistor and a low Vt transistor.

Abstract: This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a lower electrode, a variable resistance element over the lower electrode, an upper electrode disposed over the variable resistance element and including metal, and a metal compound layer configured to surround a side of the upper electrode. The metal compound layer includes a compound of the metal of the upper electrode.

Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.

Abstract: A method and a memory for sensing a state of a memory cell while the memory cell capacitor is isolated from a data line are described. An activation device of the memory cell can be enabled to couple the memory cell capacitor to a parasitic capacitance of the active data line for charge sharing. The activation device can then be disabled to isolate the memory cell capacitor from the active data line. The state of the memory cell can then be sensed while the memory cell capacitor is isolated from the active data line. After the sense operation, the activation device can be re-enabled in order to restore the data to the memory cell capacitor that was destroyed during the sense operation.

Abstract: A multiport bitcell including a pair of cross-coupled inverters is provided with increased write speed and enhanced operating voltage range by the selective isolation of a first one of the cross-coupled inverters from a power supply and ground during a write operation. The write operation occurs through a write port that includes a transmission gate configured to couple a first node driven by the first cross-coupled inverter to a write bit line. A remaining second cross-coupled inverter in the bitcell is configured to drive a second node that couples to a plurality of read ports.

Abstract: The present invention provides a method of detecting the transistor mismatch in a SRAM cell. The SRAM cell comprises two pass-gate transistors and a bi-stable circuit including two pull up transistors and two pull down transistors. The method comprises: providing two measuring transistors, whose gates are connected to a second word line, sources are connected to the outputs of the bi-stable circuit respectively and drains are connected to two measuring terminals respectively; turning on the measuring transistors and turning off the pass-gate transistors; detecting the voltage-current curve of the two pull down transistors and the two pull up transistors through the measuring transistors at the measuring terminals so as to detect the transistor mismatch in the SRAM cell.

Abstract: There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.

Abstract: A method of operating an SRAM array may include: providing a plurality of bit cells, each of the plurality of bit cells comprising a cross coupled inverter pair; a first pass gate; and a second pass gate. A word line voltage may be applied to the first pass gate and the second pass gate, while a first cell positive voltage supply CVdd may be applied to terminals of the cross coupled inverter pair.

Abstract: Circuitry and a method provide a plurality of timed control and bias voltages to sense amplifiers and write drivers of a spin-torque magnetoresistive random access memory array for improved power supply noise rejection, increased sensing speed with immunity for bank-to-bank noise coupling, and reduced leakage from off word line select devices in an active column.

Abstract: Disclosed herein are resistive switching devices having, e.g., an amorphous layer comprised of an insulating aluminum-based or silicon-based material and a conducting material. The amorphous layer may be disposed between two or more electrodes and be capable of switching between at least two resistance states. Circuits and memory devices including resistive switching devices are also disclosed, and a composition of matter involving an insulating aluminum-based or an silicon-based material and a conducting material. Also disclosed herein are methods for switching the resistance of an amorphous material.

Abstract: Methods of programming memory devices include biasing each data line of a plurality of data lines to a program inhibit voltage; discharging a first portion of data lines of the plurality of data lines, wherein the first portion of data lines of the plurality of data lines are coupled to memory cells selected for programming; and applying a plurality of programming pulses to the memory cells selected for programming while biasing a remaining portion of data lines of the plurality of data lines to the program inhibit voltage.

Abstract: A nonvolatile memory device includes a memory cell array having multiple memory blocks. Each memory block includes memory cells arranged at intersections of multiple word lines and multiple bit lines. At least one word line of the multiple word lines is included in an upper word line group and at least one other word line of the multiple word lines is included in a lower word line group. The number of data bits stored in memory cells connected to the at least one word line included in the upper word line group is different from the number of data bits stored in memory cells connected to the at least one other word line included in the lower word line group.

Abstract: An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within a memory block of the nonvolatile memory, supplying a non-selection word line voltage to word lines connected with an unselected sub-block within the memory block during a first delay time from a point of time when the erase voltage is supplied, and thereafter floating the word lines connected with the unselected sub-block.

Abstract: A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit.

Abstract: A semiconductor memory device and a method of operating the same are provided. When threshold voltages of memory cells are boosted to use the memory cells as a selection transistor, a threshold voltage of an outermost memory cell may be boosted to the highest level so that a leakage current can be reduced and a channel boosting level can be increased to reduce the influence of program disturbance.

Abstract: A nonvolatile semiconductor memory device including: a memory cell array including NAND strings; a plurality of word lines; a plurality of bit lines; a source line; and a control circuit configured to execute a write operation. The control circuit is configured to, when charging an unselected memory string prior to the write operation, execute both first and second charging operations, the first charging operation applying to the bit line connected to the unselected memory string a first voltage and rendering conductive a first select transistor to charge the unselected memory string, and the second charging operation applying to the source line connected to the unselected memory string a second voltage and rendering conductive a second select transistor to charge the unselected memory string, the first and second charging operations being executed at different timings.

Abstract: A circuit for a differential current sensing scheme includes first and second cell segments, first and second reference cells, and first and second current sense amplifiers. The first and second reference cells are configured to store opposite logic values. The first and second current sense amplifiers are each configured with a first node and a second node for currents therethrough to be compared with each other. A cell of the first cell segment and a cell of the second cell segment are coupled to the first nodes of the first and second current sense amplifiers, respectively, and the first and second reference cells are coupled to both the second nodes of the first and second current sense amplifiers.

Abstract: A write is performed to a first cell of a memory at a first row and column during a first memory access cycle. A memory access operation is made to a second cell at a second row and column during an immediately following second memory access cycle. If the memory access is a read from the second cell and the second row is the same as the first row, or if the memory access is a write to the second cell and the second row is the same as the first row and the second column is different than the first column, then a simultaneous operation is performed during the second memory access cycle. The simultaneous operation is an access of the second cell (for read or write) and a re-write of data from the first memory access cycle write operation back to the first cell.

Abstract: A memory device includes a memory cell array having a plurality of memory cells, and a page buffer unit including a plurality of page buffers configured to store a plurality of pieces of data sequentially read from some of the plurality of memory cells at different read voltage levels, respectively, and to perform a logic operation on the plurality of pieces of data, respectively.

Abstract: A memory macro comprises a data line, a first interface circuit comprising a first node coupled to the data line, and a voltage keeper configured to control a voltage level at the first node, and a second interface circuit comprising a second node coupled with the data line, wherein the voltage keeper is configured to control a voltage level at the second node via the data line.

Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.

Abstract: A canary circuit with passgate transistor variation is described herein. The canary circuit includes a memory canary circuit that has a plurality of bitcells. Each bitcell has at least a passgate transistor that is driven by a wordline voltage. The canary circuit further includes a regulator circuit that outputs a wordline voltage that accounts for a predetermined offset of a threshold voltage of the passgate transistor. In an embodiment, the regulator circuit is a subtractor circuit that generates the wordline voltage from a reference voltage based in part on the threshold voltage variation of the passgate transistor.

Abstract: An interface circuit provided in a semiconductor device supplies an operation clock to an external memory device based on a clock signal and receives a data signal and a strobe signal from the external memory device. The interface circuit includes a delay circuit delaying the received strobe signal. The delay circuit includes a first adjustment circuit and a second adjustment circuit connected in series with the first adjustment circuit. The first adjustment circuit is capable of adjusting a delay amount of the strobe signal in a plurality of steps in accordance with the set frequency of the clock signal. The second adjustment circuit is capable of adjusting the delay amount of the strobe signal with a higher precision than the first adjustment circuit.

Abstract: A device for repairing a memory device using a test-bypass register associated with the memory device may include a comparator configured to compare a current address of the memory device with a faulty address and to generate a match signal when the current address matches the faulty address. A logic block may be coupled to the comparator and configured to generate one or more output signals in response to the match signal. The faulty address may be associated with a non-operational cell of the memory device. The one or more output signals may be coupled to one or more memory-bypass inputs of the test-bypass register. The one or more output signals may be configured to enable use of the test-bypass register instead of the non-operational cell of the memory device.

Abstract: Methods, apparatuses, and integrated circuits for measuring leakage current are disclosed. In one such example method, a word line is charged to a first voltage, and a measurement node is charged to a second voltage, the second voltage being less than the first voltage. The measurement node is proportionally coupled to the word line. A voltage on the measurement node is compared with a reference voltage. A signal is generated, the signal being indicative of the comparison. Whether a leakage current of the word line is acceptable or not can be determined based on the signal.

Abstract: A single-ended low-swing power-savings mechanism is provided. The mechanism comprises a precharge device that turns off in an evaluation phase and a first biasing device is always on. Within the mechanism, a strength of a keeper device is changed to a first level in response to an input of the second biasing device being at a first voltage level. Within the mechanism the strength of the keeper device is changed to a second level in response to the input of the second biasing device being at a second voltage level. Responsive to receiving a (precharged voltage level read data line signal, a precharged voltage level of the first node falls faster when the keeper device is weakened to a first level. The keeper device turns on in response to receiving a LOW signal and pulls up the voltage at the first node so that a HIGH signal is output.

Abstract: Apparatuses and methods for adjusting deactivation voltages are described herein. An example apparatus may include a voltage control circuit. The voltage control circuit may be configured to receive an address and to adjust a deactivation voltage of an access line associated with a target group of memory cells from a first voltage to a second voltage based, at least in part, on the address. In some examples, the first voltage may be lower than the second voltage.

Abstract: A semiconductor memory device includes a plurality of first regions formed in a line-type and extending in a first direction, and a plurality of second regions and a plurality of third regions arranged between adjacent first regions in a zigzag manner.

Abstract: Voltage control in integrated circuits include a first voltage divider coupled to receive a reference voltage and having an output providing an adjusted reference voltage; an operational amplifier having a first input coupled to receive the output of the first voltage divider, a second input coupled to receive a feedback voltage, and an output; a voltage generation circuit responsive to the output of the operational amplifier and having an output providing an output voltage; and a second voltage divider coupled to receive the output voltage and having an output providing the feedback voltage. The first voltage divider is responsive to first control signals to adjust a voltage level of the adjusted reference voltage. The second voltage divider is responsive to second control signals to adjust a voltage level of the feedback voltage.

Abstract: In various embodiments, a memory device includes at least one memory cell and at least one virtual supply line coupled to the at least one memory cell. The memory device is designed in such a way that a voltage potential present on the virtual supply line is altered after an active access to the memory cell by virtue of a charge stored within the memory device during the active access being re-stored in such a way that a state of the memory cell with a reduced leakage current consumption is achieved.