Abstract: A thin-film semiconductor substrate includes a top-gate first TFT, a top-gate second TFT, and a data line (source line), in which the first TFT has a first semiconductor layer, a first gate insulating film, a first gate electrode, a first source electrode, a first drain electrode, and a first protection layer, the second TFT has a second semiconductor layer, a second gate insulating film, a second gate electrode, a second source electrode, a second drain electrode, and a second protection layer, the data line is connected to the first source electrode, the first drain electrode is an extension of the second gate electrode, and the second gate electrode is thinner than the data line.

Abstract: An object is to provide a semiconductor device including an oxide semiconductor, which has stable electric characteristics and high reliability. In a transistor including an oxide semiconductor film, the oxide semiconductor film is subjected to dehydration or dehydrogenation performed by heat treatment. In addition, as a gate insulating film in contact with the oxide semiconductor film, an insulating film containing oxygen, preferably, a gate insulating film including a region containing oxygen with a higher proportion than the stoichiometric composition is used. Thus, oxygen is supplied from the gate insulating film to the oxide semiconductor film. Further, a metal oxide film is used as part of the gate insulating film, whereby reincorporation of an impurity such as hydrogen or water into the oxide semiconductor is suppressed.

Abstract: Manufactured is a transistor including an oxide semiconductor layer, a source electrode layer and a drain electrode layer overlapping with part of the oxide semiconductor layer, a gate insulating layer overlapping with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode overlapping with part of the oxide semiconductor layer with the gate insulating layer provided therebetween, wherein, after the oxide semiconductor layer which is to be a channel formation region is irradiated with light and the light irradiation is stopped, a relaxation time of carriers in photoresponse characteristics of the oxide semiconductor layer has at least two kinds of modes: ?1 and ?2, ?1<?2 is satisfied, and ?2 is 300 seconds or less. In addition, a semiconductor device including the transistor is manufactured.

Abstract: A device includes a semiconductor chip. An outline of a frontside of the semiconductor chip includes at least one of a polygonal line including two line segments joined together at an inner angle of greater than 90° and an arc-shaped line.

Abstract: An integrated circuit includes a number of lateral diffusion measurement structures arranged on a silicon substrate. A lateral diffusion measurement structure includes a p-type region and an n-type region which cooperatively span a predetermined initial distance between opposing outer edges of the lateral diffusion measurement structure. The p-type and n-type regions meet at a p-n junction expected to be positioned at a target junction location after dopant diffusion has occurred.

Abstract: A display panel includes gate lines extending in a first direction, a first column insulating layer between the gate lines, a gate electrode disposed on the first column insulating layer. The first column insulating layer, the gate lines, and the gate electrode are covered by a gate insulating layer. An active layer is disposed on the gate insulating layer. Source and drain electrodes are disposed above the active layer. Data lines are connected to the source electrode. A second column insulating layer is interposed between the data lines and includes a first contact hole to expose the drain electrode. A contact electrode is disposed in the first contact hole and connected to the drain electrode, a second contact hole is formed through a protective layer to correspond to the first contact hole, and a pixel electrode is connected to the contact electrode through the second contact hole.

Abstract: An array substrate for a liquid crystal display (LCD) device include: a substrate; a gate line formed in one direction on one surface of the substrate; a data line crossing the gate line to define a pixel area; a thin film transistor (TFT) configured at a crossing of the gate line and the data line; a pixel electrode formed at a pixel region of the substrate; an insulating film formed on the entire surface of the substrate including the pixel electrode and the TFT, including a first insulating film formed of a high temperature silicon nitride film and a second insulating film formed of a low temperature silicon nitride film, and having a contact hole having an undercut shape exposing the pixel electrode; a pixel electrode connection pattern formed within the contact hole having an undercut shape and connected with the pixel electrode and the TFT; and a plurality of common electrodes separately formed on the insulating film.

Abstract: The present invention proposes a TFT switch and a method for manufacturing the same. The TFT switch includes a gate, a drain, a source, a semiconductor layer and a fourth electrode. The drain is connected to a first signal, the gate is connected to a control signal to control the switch on or off. The source outputs the first signal when the switch turns on. The fourth electrode and the gate are respectively located at two sides of the semiconductor layer. The fourth electrode is conductive and is selectively coupled to different voltage levels, thereby reducing leakage current in a channel to improve switch characteristic when the switch turns off.

Abstract: A thin film transistor includes: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer; and a pair of source region and drain region formed by doping both sides of the first semiconductor layer and the second semiconductor layer with impurities, and the source region includes a first source layer on the same plane as the first semiconductor layer and a second source layer on the same plane as the second semiconductor layer, and the drain region includes a first drain layer on the same plane as the first semiconductor layer and a second drain layer on the same plane as the second semiconductor layer, and only one of the first semiconductor layer and the second semiconductor layer is a transistor channel layer.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, an insulating film, and a control electrode. The first semiconductor region includes a silicon carbide of a first conductivity type. The second semiconductor region is provided on the first semiconductor region, includes a silicon carbide of a second conductivity type, and has a first main surface. The third semiconductor region is provided on the second semiconductor region and includes the silicon carbide of the first conductivity type. The film is provided on the surface. The electrode is provided on the film, and has a first region close to the third semiconductor region side, and a second region closer to the first semiconductor region side than the first region. An effective work function of the first region is larger than an effective work function of the second region.

Abstract: A thin film transistor substrate includes a base substrate, an active pattern provided on the base substrate and including a source electrode, a drain electrode and a channel between the source electrode and the drain electrode, a gate insulation layer provided on the active pattern, a gate electrode which is provided on the active pattern and overlaps the channel, a first contact pad disposed on at least one of the source electrode and the drain electrode and including a first metal, and a first non-conductive metal oxide layer on the base substrate to cover the gate electrode and including the first metal.

Abstract: A method of manufacturing a TFT array substrate and a TFT array substrate and a display device are provided. During a pattern of a gate layer (2), a pattern of the gate insulating layer (3) and a pattern of the active layer are made, a gate layer (2) material, a gate insulating layer (3) material and an active layer material are deposited successively. The gate layer (2), the gate insulating layer (3) and the active layer are made through one patterning process. At least one mask process is saved and the process complexity is reduced.

Abstract: A flexible semiconductor device includes a wire embedded layer that has flexibility and has a first principal surface and a second principal surface, a thick wire embedded in the wire embedded layer so as to be substantially flush with the first principal surface of the wire embedded layer, and a thin film transistor element electrically connected to the thick wire. The thin film transistor element is disposed on the first principal surface of the wire embedded layer. The flexible semiconductor device is suitable for increasing the area and can be manufactured with a high productivity. A display device including the flexible semiconductor device and a method for manufacturing the flexible semiconductor device are also disclosed.

Abstract: A semiconductor device includes an active layer, at least one source electrode, at least one drain electrode, at least one gate electrode, a first insulating layer, a first source pad, a first drain pad, at least one source plug, and at least one drain plug. The source electrode and the drain electrode are both disposed on the active layer. Projections of the source electrode and the drain electrode on the active layer form a source region and a drain region, respectively. The first source pad and the first drain pad are both disposed on the first insulating layer. A projection of the first source pad on the active layer forms a source pad region. An area of an overlapping region between the source pad region and the drain region is smaller than or equal to 40% of an area of the drain region.

Abstract: A semiconductor device according to one embodiment includes an n-type first GaN-based semiconductor layer, a p-type second GaN-based semiconductor layer on the first GaN-based semiconductor layer. The second GaN-based semiconductor layer includes a low impurity concentration region and a high impurity concentration region. An n-type third GaN-based semiconductor layer is provided on the second GaN-based semiconductor layer. The device includes a gate electrode being located adjacent to the third GaN-based semiconductor layer, the low impurity concentration region, and the first GaN-based semiconductor layer intervening a gate insulating film. The device includes a first electrode on the third GaN-based semiconductor layer, a second electrode on the high impurity concentration region, and a third electrode on the opposite side of the first GaN-based semiconductor layer from the second GaN-based semiconductor layer.

Abstract: A light emitting diode structure comprising a substrate, a first semiconductor layer, an active layer, a second semiconductor layer, a current resisting layer, a current spreading layer, a first electrode and a second electrode is provided. The first semiconductor layer is formed on the substrate. The active layer covers a portion of the first semiconductor layer, and exposes another portion of the first semiconductor layer. The second semiconductor layer is formed on the active layer. The current resisting layer covers a portion of the second semiconductor layer, and exposes another portion of the second semiconductor layer. The current spreading layer covers the second semiconductor layer and the current resisting layer. The current spreading layer is formed with a reverse trapezoidal concave over the current resisting layer. The first electrode is disposed on the first semiconductor layer. The second electrode is disposed within the reverse trapezoidal concave.

Abstract: A group III nitride semiconductor multilayer substrate (100) includes a channel layer (5) which is a group III nitride semiconductor, a barrier layer (6) which is formed on the channel layer (5) to form a heterointerface in combination with the channel layer (5) and which is a group III nitride semiconductor, wherein in the barrier layer (6, 206), a Cu concentration in a region of 10 nm or less depths from its surface is 1.0×1010 (atomicity/cm2) or less.

Abstract: A laminate includes a surface on which a gate electrode is provided, and is made of a nitride semiconductor. The laminate includes a first layer having a first band gap, and a second layer provided between the first layer and the surface and having a second band gap which is larger than the first band gap. The first and second layers and form a joint surface by a hetero junction. The surface includes a surface defect density equal to or smaller than 1.7×106 cm?2.

Abstract: A heterostructure grown on a silicon substrate includes a single crystal rare earth oxide template positioned on a silicon substrate, the template being substantially crystal lattice matched to the surface of the silicon substrate. A heterostructure is positioned on the template and defines at least one heterojunction at an interface between a III-N layer and a III-III-N layer. The template and the heterostructure are crystal matched to induce an engineered predetermined tensile strain at the at least one heterojunction. A single crystal rare earth oxide dielectric layer is grown on the heterostructure so as to induce an engineered predetermined compressive stress in the single crystal rare earth oxide dielectric layer and a tensile strain in the III-III-N layer. The tensile strain in the III-III-N layer and the compressive stress in the REO layer combining to induce a piezoelectric field leading to higher carrier concentration in 2DEG at the heterojunction.

Abstract: A semiconductor device includes: a base; an electron transit layer layered on the base; an electron-supplying layer being configured by layering a plurality of AlN layers and GaN layers alternately on the electron transit layer and having an average Al composition x; an etching sacrificial layer layered on the electron-supplying layer and made of AlyGa1-yN (0<y<1) having an Al composition y; a field plate layer layered on the etching sacrificial layer and made of AlzGa1-zN (0?z<1, z<y) having an Al composition z; and an electrode connected to the etching sacrificial layer and being provided in an area in which a part of the field plate layer is removed until reaching the etching sacrificial layer.

Abstract: A semiconductor device according to an embodiment is at least partially arranged in or on a substrate and includes a recess forming a mesa, wherein the mesa extends along a direction into the substrate to a bottom plane of the recess and includes a semiconducting material of a first conductivity type, the semiconducting material of the mesa including at least locally a first doping concentration not extending further into the substrate than the bottom plane. The semiconductor device further includes an electrically conductive structure arranged at least partially along a sidewall of the mesa, the electrically conductive structure forming a Schottky or Schottky-like electrical contact with the semiconducting material of the mesa, wherein the substrate comprises the semiconducting material of the first conductivity type comprising at least locally a second doping concentration different from the first doping concentration along a projection of the mesa into the substrate.

Abstract: A Schottky barrier diode and a method of manufacturing the Schottky barrier diode are provided. The diode includes an n? type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate and having an upper surface, a lower surface, and an inclined surface that connects the upper surface and the lower surface. A p region is disposed on the inclined surface of the n? type epitaxial layer and a Schottky electrode is disposed on the upper surface of the n? type epitaxial layer and the p region. In addition, an ohmic electrode is disposed on a second surface of the n+ type silicon carbide substrate.

Abstract: According one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer of a first conductivity type provided between the first electrode and the second electrode, the first semiconductor layer including silicon carbide; a second semiconductor layer of the first conductivity type provided between the first semiconductor layer and the second electrode, the second semiconductor layer having a lower impurity concentration than the first semiconductor layer, and the second semiconductor layer including silicon carbide; a third semiconductor layer of a second conductivity type provided between the second semiconductor layer and the second electrode, and the third semiconductor layer including silicon carbide; and a plurality of insulating layers provided between the third semiconductor layer and the second electrode.

Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, and first, second, and third semiconductor regions. The first semiconductor region has a first conductivity type. The first electrode is provided above the first semiconductor region. The second semiconductor region has a second conductivity type and is provided between the first semiconductor region and the first electrode. The third semiconductor region is provided between the first semiconductor region and the first electrode, and has the second conductivity type. The third semiconductor region has an impurity concentration substantially equal to an impurity concentration of the second semiconductor region, and has first and second portions. The first and second portions constitute a concave-convex form on a side of the first semiconductor region of the third semiconductor region. The second electrode is provided above an opposite side of the first semiconductor region from the first electrode.

Abstract: An n-type SiC layer is formed on a front face of an n+-type SiC substrate and plural p-type regions are selectively formed inside the n-type SiC layer. A p-type SiC layer is formed covering the surfaces of the n-type SiC layer and the p-type regions. An n-type region is formed inside the p-type SiC layer to be connected to the n-type SiC layer. An n+-type source region and a p+-type contact region are formed inside the p-type SiC layer, positioned away from the n-type region and in contact with each other. The n-type region in the p-type SiC layer is formed such that the width LJFET of the n-type region is within a range from 0.8 ?m to 3.0 ?m and the impurity concentration of the n-type region is greater than 1.0×1016 cm?3 and less than or equal to 5.0×1016 cm?3.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, and a third semiconductor region. The first semiconductor region includes silicon carbide. A conductivity type of the first semiconductor region is a first conductivity type. The second semiconductor region includes silicon carbide. A conductivity type of the second semiconductor region is a second conductivity type. The third semiconductor region includes silicon carbide. A conductivity type of the third semiconductor is the second conductivity type. The third semiconductor region is provided between the first semiconductor region and the second semiconductor region. As viewed in a direction connecting the first semiconductor region and the second semiconductor region, an area of an overlapping region of the second semiconductor region and the third semiconductor region is smaller than an area of an overlapping region of the first semiconductor region and the second semiconductor region.

Abstract: A monolithic bidirectional switching device includes a drift layer having a first conductivity type and having an upper surface, and first and second vertical metal-oxide semiconductor (MOS) structures at the upper surface of the drift layer. The drift layer provides a common drain for the first and second vertical MOS structures. The first and second vertical MOS structures are protected by respective first and second edge termination structures at the upper surface of the drift layer. A monolithic bidirectional switching device according to further embodiments includes a vertical MOS structure at the upper surface of the drift layer, and a diode at the upper surface of the drift layer. The drift layer provides a drain for the vertical MOS structure and a cathode for the diode, and the vertical MOS structure and the diode are protected by respective first and second edge termination structures.

Abstract: The present invention relates to a method for separating epitaxial layers and growth substrates, and to a semiconductor device using same. According to the present invention, a semiconductor device is provided which comprises a supporting substrate and a plurality of semiconductor layers provided on the supporting substrate, wherein the uppermost layer of the semiconductor layers has a surface of non-uniform roughness.

Abstract: A semiconductor light emitting element include a semiconductor layer in which a first semiconductor layer, a second semiconductor layer, and a light emitting layer that is disposed between the first semiconductor layer and the second semiconductor layer are disposed. The first semiconductor layer has a step portion protruding more outwards than the light emitting layer and the second semiconductor layer. A plurality of first recesses is formed on side surfaces of the semiconductor layer not including the light emitting layer along a deposition direction of the semiconductor layer and along a direction intersecting with the deposition direction of the semiconductor layer and a plurality of second recesses is found on side surfaces of the semiconductor layer including the light emitting layer along the deposition direction of the semiconductor layer and along the direction intersecting with the deposition direction of the semiconductor layer.

Abstract: A stressor layer is applied to a semiconducting stack in order to separate the semiconducting stack at a predetermined depth. Tensile force is applied to the stressor layer, fracturing the semiconducting stack at the predetermined depth and allowing the resulting upper portion of the semiconducting stack to be used in manufacturing a semiconducting end-product (e.g., a light-emitting diode). The resulting lower portion of the semiconducting stack may be reused to grow a new semiconducting stack thereon.

Abstract: A method for wafer alignment includes forming a first alignment circuit within a first semiconductor wafer; the first alignment circuit is configured to emit an optical signal. Next, the first alignment circuit is activated upon receiving a first activation signal from a wafer bonding tool then the optical signal is sent to a second alignment circuit in a second semiconductor wafer in overlapping relation to the first semiconductor wafer. The second alignment circuit transmits a second activation signal to the wafer bonding tool and consequently the wafer bonding tool initiates an alignment technique between the first and second semiconductor wafers. The alignment technique uses the first and second alignment circuits for optical alignment.

Abstract: According to one embodiment, a photocoupler includes: an input terminal; a light emitting unit; a light receiving unit and an output terminal. An input electrical signal having a prescribed voltage is input into an input terminal. The light emitting unit is connected to the input terminal, includes a light emitting element configured to emit emission light, and is configured to drive the light emitting element under a constant voltage of the input electrical signal. The light receiving unit includes a light receiving element configured to receive the emission light and convert the emission light into an electrical signal. The output terminal is insulated from the input terminal and configured to output the electrical signal in accordance with the input electrical signal.

Abstract: A mounting member includes: an insulating substrate, a first die pad unit, first and second terminals. The insulating substrate has a rectangular first surface, a second surface, a first side surface, a second side surface, a third side surface, and a fourth side surface. A through hole is provided from the first surface to the second surface. The first die pad unit is provided on the first surface. The first terminal has a conductive region covering the first side surface, the first surface, and the second surface. The second terminal has a conductive region covering the second side surface and the second surface, connected to the first die pad unit by conductive material provided in the through hole or on a side wall of the through hole. The first die pad unit, the first terminal, and the second terminal are apart from one another.

Abstract: A semiconductor component includes an auxiliary semiconductor device configured to emit radiation. The semiconductor component further includes a semiconductor device. An electrical coupling and an optical coupling between the auxiliary semiconductor device and the semiconductor device are configured to trigger emission of radiation by the auxiliary semiconductor device and to trigger avalanche breakdown in the semiconductor device by absorption of the radiation in the semiconductor device. The semiconductor device includes a pn junction between a first layer of a first conductivity type buried below a surface of a semiconductor body and a doped semiconductor region of a second conductivity type disposed between the surface and the first layer.

Abstract: A light-emitting device module includes a substrate and a light-emitting device disposed on the substrate. The light-emitting device may have a first pad and a second pad disposed thereon. A coating layer may cover the light-emitting device. The coating layer has a first via hole and a second via hole configured to respectively expose the first pad and the second pad therethrough. Wirings configured to be electrically connected to the first pad and the second pad through the first via hole and the second via hole are disposed on the coating layer.

Abstract: Provided is a display panel including a base substrate provided with a plurality of thin film transistors, the base substrate including a plurality of transmission regions and a light-blocking region adjacent to the transmission regions, the thin film transistors overlapping the light-blocking region, a plurality of pixel electrodes overlapping the transmission regions, respectively, the pixel electrodes being connected to a corresponding one of the thin film transistors, and an insulating layer interposed between the pixel electrodes and the base substrate to include at least one staircase portion, each of which overlaps the transmission regions, respectively.

Abstract: An omnidirectional lighting unit is disclosed, which includes a light-emitting chip, a spherical package member, a diffusion layer, and two conductive structures. The light-emitting chip has a positive electrode and a negative electrode. The spherical package member encapsulates the light-emitting chip, and the diffusion layer covers an outer surface of the spherical package member. The two conductive structures are electrically connected to the positive and negative electrodes, respectively, and each of the two conductive structures penetrates through the spherical package member and the diffusion layer outwardly, such that a portion of each conductive structure is exposed the exterior of the diffusion layer.

Abstract: Provided is a light emitting diode package including: a molded portion having a housing; a plurality of light emitting chips housed in the housing; a plurality of main lead portions on which the plurality of light emitting chips is mounted, respectively; at least one sub-lead portion formed spaced from the main lead portions and electrically connected to at least any one of the plurality of main lead portions and the plurality of light emitting chips with wires for electrically connecting the plurality of light emitting chips each other; first space maintaining portions formed such that the plurality of light emitting chips respectively on the plurality of main lead portions are opposite to one another with one of the first space maintaining portions disposed therebetween; and second space maintaining portions formed on both sides of each of the first space maintaining portions.

Abstract: The present invention provides a method of manufacturing an electronic display. The exemplary method includes depositing a first conductive medium within a plurality of cavities of a substrate to form a plurality of first conductors. A plurality of electronic components in a suspending medium are then deposited within the plurality of cavities, and the plurality of electronic components are oriented using an applied field, followed by a bonding of the plurality of electronic components to the plurality of first conductors. A second, transmissive conductive medium is then deposited and bonded to the plurality of electronic components.

Abstract: A phosphor-converted light emitting device includes a light emitting diode (LED) on a substrate, where the LED comprises a stack of epitaxial layers comprising a p-n junction. A wavelength conversion material is in optical communication with the LED. According to one embodiment of the phosphor-converted light emitting device, a selective filter is adjacent to the wavelength conversion material, and the selective filter comprises a plurality of nanoparticles for absorbing light from the LED not down-converted by the wavelength conversion material. According to another embodiment of the phosphor-converted light emitting device, a perpendicular distance between a perimeter of the LED on the substrate and an edge of the substrate is at least about 24 microns. According to another embodiment of the phosphor-converted light emitting device, the LED comprises a mirror layer on one or more sidewalls thereof for reducing light leakage through the sidewalls.

Abstract: A method of forming a light sheet includes printing a layer of inorganic LEDs on a first conductive surface of a substrate, depositing a first dielectric layer, and depositing a second conductor layer over the LEDs so that the LEDs are connected in parallel. At least one of the first conductive surface or the second conductor layer is transparent to allow light to escape. A phosphor layer may be formed over the light sheet so that the LED light mixed with the phosphor light creates white light. The flat light sheet is then folded, such as by molding, to form a three-dimensional structure with angled light emitting walls and reflective surfaces to control a directionality of the emitted light and improve the mixing of light. The folds may form rows of angled walls or polygons.

Abstract: A light-emitting structure includes a substrate and a light-emitting unit. The substrate has a first meander conductive track and a second meander conductive track. Each first chip-mounting area of the first meander conductive track has at least two first chip-mounting lines. Each second chip-mounting area of the second meander conductive track has at least two second chip-mounting lines. The light-emitting unit includes first light-emitting groups and second light-emitting groups. Each first light-emitting group includes at least one or a plurality of first LED chips disposed on the same first chip-mounting line of the corresponding first chip-mounting area, and each second light-emitting group includes at least one or a plurality of second LED chips disposed on the same second chip-mounting line of the corresponding second chip-mounting area. The first and the second chip-mounting areas are arranged alternately, thus the first and the second light-emitting groups are arranged alternately.

Abstract: Light emitting systems and method of fabricating the same are disclosed. The light emitting system includes two or more monolithically integrated luminescent elements. Each luminescent element includes an electroluminescent device and a dedicated switching circuit for driving the electroluminescent device. At least one luminescent element includes a potential well for down converting light emitted by the electroluminescent device in the luminescent element.

Abstract: A blue LED device has a transparent substrate and a reflector structure disposed on the backside of the substrate. The reflector structure includes a Distributed Bragg Reflector (DBR) structure having layers configured to reflect yellow light as well as blue light. In one example, the DBR structure includes a first portion where the thicknesses of the layers are larger, and also includes a second portion where the thicknesses of the layers are smaller. In addition to having a reflectance of more than 97.5 percent for light of a wavelength in a 440 nm-470 nm range, the overall reflector structure has a reflectance of more than 90 percent for light of a wavelength in a 500 nm-700 nm range.

Abstract: A LED package is formed of a substrate, an LED chip, an insulated layer, and a fluorescent adhesive layer. The substrate includes a positive contact and a negative contact. The LED chip is fixed to the substrate and includes a positive terminal and a negative terminal, the former of which is electrically connected with the positive contact and latter is electrically connected with the negative contact. The insulated layer is mounted to the surface of the substrate and surrounds the LED chip. The fluorescent adhesive layer is mounted to a surface of the insulated layer and covers the LED chip. In this way, the LED package can reduce the production cost and the whole size.

Abstract: A semiconductor light emitting device according to an embodiment includes a semiconductor layer, a first resin layer provided on the semiconductor layer, first fluorescer particles disposed in the first resin layer, and a second resin layer provided on the first resin layer to contact the first resin layer. Recesses are made in a surface of the first resin layer contacting the second resin layer. The recesses are filled with portions of the second resin layer.

Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a sealing member configured to cover a lower surface of the semiconductor layer and a side surface of the semiconductor layer to protrude to be higher than an upper surface of the semiconductor layer at a side of the semiconductor layer, a fluorescer layer provided above the semiconductor layer and the sealing member, and an insulating film provided between the sealing member and the semiconductor layer and between the sealing member and the fluorescer layer. A corner of a protruding portion of the sealing member is rounded.

Abstract: A light-emitting diode (LED) assembly includes an aluminum substrate, a silver layer, a distributed Bragg reflector (DBR) and an LED device. The aluminum substrate has a top surface whose length and width are each more than once centimeter. The silver layer is disposed over the entire top surface of the aluminum substrate. The DBR is disposed over the entire upper surface of the silver layer. The DBR includes an upper reflector layer and a lower reflector layer. The lower reflector layer contacts the upper surface of the silver layer. The Led device is attached to the upper reflector layer of the DBR, but the LED device is not disposed over the entire upper reflector layer. In one embodiment, the silver layer is deposited on the substrate using physical vapor deposition. In another embodiment, multiple pairs of lower reflector and higher reflector layers are included.

Abstract: A method for fabricating an LED/phosphor structure is described where an array of blue light emitting diode (LED) dies are mounted on a submount wafer. A phosphor powder is mixed with an organic polymer binder, such as an acrylate or nitrocellulose. The liquid or paste mixture is then deposited over the LED dies or other substrate as a substantially uniform layer. The organic binder is then removed by being burned away in air, or being subject to an 02 plasma process, or dissolved, leaving a porous layer of phosphor grains sintered together. The porous phosphor layer is impregnated with a sol-gel (e.g., a sol-gel of TEOS or MTMS) or liquid glass (e.g., sodium silicate or potassium silicate), also known as water glass, which saturates the porous structure. The structure is then heated to cure the inorganic glass binder, leaving a robust glass binder that resists yellowing, among other desirable properties.

Abstract: Provided is a light emitting diode having a nanostructure capping pattern and a method of manufacturing the same. A light-emitting structure including a first semiconductor layer, a second semiconductor layer, and an active layer between the first and second semiconductor layers is provided. A nanostructure is provided on the light-emitting structure and a nanostructure capping pattern covering the nanostructure is provided. A refractive index of the nanostructure capping pattern is higher than that of air and lower than that of the nanostructure.