Abstract: A light emitting diode (LED) package includes a substrate, a first electrode and a second electrode mounted on opposite sides of the substrate, an LED chip mounted on a top surface of one of the electrodes and electrically connecting the first electrode and the second electrode by wire bonding, and a reflecting cup enclosing an outer periphery of the first electrode and the second electrode to expose top surfaces of the first electrode and the second electrode and bottom surfaces of the first electrode and the second electrode.

Abstract: Disclosure has LED assemblies and related LED light bulbs. An LED assembly comprises a flexible, transparent substrate, an LED chip on the first surface and electrically connected to two adjacent conductive sections, and a first wavelength conversion layer, formed on the first surface to substantially cover the LED chip. The flexible, transparent substrate comprises first and second surfaces opposite to each other, and several conductive sections, which are separately formed on the first surface.

Abstract: The light-emitting diode includes first and second layers of semiconductor material, having opposite conductivity types, an active light-emitting area located between the first and second layers of semiconductor material, an electrode arranged on the first layer of semiconductor material and a photonic crystal formed in the first layer of semiconductor material. The photonic crystal and the electrode are separated by a distance optimized to simultaneously promote the electric injection and minimize the light absorption in the LED.

Abstract: A light emitting diode and a method of fabricating the same, the light emitting diode including a substrate, a semiconductor layer formed on one surface of the substrate, and an anti-reflection element formed on the other surface of the substrate and including a nano-pattern. The anti-reflection element is interposed between the substrate and air.

Abstract: A light emitting device package is disclosed. The light emitting device package includes a package body, a heat radiating member disposed in the package body, a light emitting device disposed on the heat radiating member, a bonding member disposed between the light emitting device and the heat radiating member, and a bonding member fixing layer disposed around the bonding member, wherein the bonding member fixing layer has at least one through region.

Abstract: A light emitting diode includes a substrate, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode, and a second electrode. The first semiconductor layer, the active layer, and the second semiconductor layer are orderly stacked on the substrate. The first electrode is electrically connected to the first semiconductor layer. The second electrode electrically is connected to the second semiconductor layer. The first semiconductor layer has a number of three-dimensional nano-structures, and each of the number of three-dimensional nano-structures has a stepped structure.

Abstract: The present invention discloses an integral LED component which integrates LED epitaxial structure electrodes and interconnects with a package substrate together and an integral manufacturing process thereof. The integral LED component can be made with multiple epitaxial structures or with just a single epitaxial structure. The integral LED component can be mounted into a hollow carrier. And by having support by the hollow carrier, the package substrate can be mounted and contacted with a heat conductive or a dissipation device. The integral LED component is fabricated by wafer level process and cut from the wafer as an independent component. By different manufacturing process, the integral LED component can be made as Vertical LED structure or Lateral LED structure.

Abstract: A light-reflective anisotropic conductive adhesive is used for anisotropic conductive connection of a light-emitting element to a wiring board. The adhesive includes a thermosetting resin, conductive particles, and light-reflective acicular insulating particles. The conductive particles comprise a core particle coated with a metal particle or a metal material, and a light reflective layer formed on a surface of the core particle. The light reflective layer comprises inorganic particles selected from any one of titanium oxide particles, zinc oxide particles or aluminum oxide particles until the entire conductive particle appears a color in a range from white to gray.

Abstract: A light-emitting device which is thin and lightweight and has high flexibility, impact resistance, and reliability is provided. Further, a light-emitting device which is thin and lightweight and has high flexibility, impact resistance, and hermeticity is provided. In the light-emitting device in which a light-emitting region including a transistor and a light-emitting element is sealed between a first flexible substrate and a second flexible substrate, an opening is provided in the second flexible substrate around a region overlapping with the light-emitting region, the opening is filled with frit glass containing low-melting glass and bonding the first flexible substrate and the second flexible substrate, and the fit glass is provided so as to be in contact with an insulating layer provided over the first flexible substrate. The second flexible substrate may include an opening in a region overlapping with the light-emitting region.

Abstract: The present disclosure provides a light emitting module including a substrate, a light emitting diode, a first adhesive glue, and a second adhesive glue. The substrate has a first electrode and a second electrode. The light emitting diode is disposed on the substrate and has a third electrode and a fourth electrode. The first adhesive glue is located between the first electrode and the second electrode so as to enable the first electrode to be electrically connected to the second electrode. The second adhesive glue is located between the third electrode and the fourth electrode, so as to enable the third electrode to be electrically connected to the fourth electrode. The first adhesive glue includes a first conductive body and a first insulation body surrounding the first conductive body. The second adhesive glue includes a second conductive body and a second insulation body surrounding the second conductive body.

Abstract: An LED chip is disclosed. The LED chip includes a substrate and a semiconductor element formed on the substrate. A recess is formed on the semiconductor element so as to expose a first-type of semiconductor layer thereof to the environment. The LED chip also includes a conductive layer disposed on a second-type semiconductor layer of the semiconductor element, a first electrode disposed in the recess and electrically connected to the first-type of semiconductor layer, and a second electrode disposed on the conductive layer. In addition, the LED chip includes a first circular electrode disposed on the conductive layer and extending along an edge of the substrate and electrically connected to the second electrode.

Abstract: A lighting device may include a mounting board with first and second opposed faces and vias extending therethrough, one or more light radiation sources mounted on the first face of the mounting board, drive circuitry for the light radiation source mounted on the second face of the mounting board, with electrically conductive lines between the light radiation source and the drive circuitry passing through said vias, a vat-like holder housing the mounting board with the light radiation source and the drive circuitry mounted thereon. The holder has cavities for receiving therein the drive circuitry with the first face of the mounting board and the light radiation source mounted thereon facing outwardly of the holder. Over the first face of the mounting board at least one sealing layer is applied, which ensures an IP grade protection of device.

Abstract: A flexible substrate member which can prevent breakage due to bending, regardless of a shape of a metal pattern, and a light emitting device which employs the flexible substrate. The flexible substrate member includes a plurality of metal wirings disposed on an insulating substrate which are spaced apart from each other via a groove portion. The groove portion includes an intersection region where a first groove portion and a second groove portion are intersected. The metal wirings includes a first metal wiring and a second metal wiring which are demarcated via the first groove portion in the intersection region, and a third metal wiring which is demarcated via the second groove portion with respect to the first metal wiring and the second metal wiring. The third metal wiring includes a projection which projects on an extension line of the first groove portion.

Abstract: A light emitting device package includes: first and second electrodes, at least a portion of a lower surface thereof being exposed; a light emitting device disposed on an upper surface of at least one of the first and second electrodes; a reflection wall disposed on the upper surface of the first and second electrodes and surrounding the light emitting device to form a mounting part therein; and a fluorescent film disposed on the reflection wall to cover an upper portion of the mounting part. The mounting part is filled with air.

Abstract: Disclosed are a heat dissipation material comprising a metallic glass and an organic vehicle and a light emitting diode package including at least one of a junction part, wherein the junction part includes a heat dissipation material including a metallic glass.

Abstract: A curable silicone composition comprising: (A) (A1) an organopolysiloxane having at least two alkenyl groups in a molecule and free of silicon-bonded hydroxyl groups or silicon-bonded hydrogen atoms, or a mixture of said component (A1) and (A2) a branched chain organopolysiloxane represented by an average unit formula; (B) an organopolysiloxane having at least two silicon-bonded hydrogen atoms in a molecule; (C) a diorganodialkoxysilane represented by a general formula; (D) a straight chain organosiloxane oligomer having at least one silicon-bonded hydroxyl group in a molecule and free of silicon-bonded hydrogen atoms; and (E) a hydrosilylation catalyst, can form a cured product which exhibits excellent initial adhesive properties and transparency and exhibits excellent adhesive durability and retention of transparency under conditions of high temperature and high humidity.

Abstract: An epoxy resin composition according to an embodiment of the present invention comprises an epoxy resin, 0.05-190 parts by weight, based on 10 parts by weight of the epoxy resin, of a polyester-based curing agent, wherein the epoxy resin comprises a triazine derivative epoxy compound and a siloxane compound containing an alicyclic epoxy group and a siloxane group.

Abstract: A tunnel field transistor (TFET) device includes a fin structure that protrudes from a substrate surface. The fin structure includes a base portion proximate to the substrate surface, a top portion, and a first pair of sidewalls extending from the base portion to the top portion. The first pair of sidewalls has a length corresponding to a length of the fin structure. The fin structure also includes a first doped region having a first dopant concentration at the base portion of the fin structure. The fin structure also includes a second doped region having a second dopant concentration at the top portion of the fin structure. The TFET device further includes a gate including a first conductive structure neighboring a first sidewall of the first pair of sidewalls. A dielectric layer electrically isolates the first conductive structure from the first sidewall.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate in which a recess is provided on a back surface thereof, and a shape of the recess is reflected on a surface of a metal film which is also provided on the back surface of the semiconductor substrate.

Abstract: In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type having first and second faces, and a second semiconductor layer of a second conductivity type disposed above the first face of the first semiconductor layer. The device further includes control electrodes facing the first and second semiconductor layers via insulating layers, and extending to a first direction parallel to the first face of the first semiconductor layer, and third semiconductor layers of the first conductivity type and fourth semiconductor layers of the second conductivity type alternately disposed along the first direction above the second semiconductor layer. The device further includes fifth semiconductor layers of the first conductivity type disposed below the second semiconductor layer or disposed at positions surrounded by the second semiconductor layer, the fifth semiconductor layers being arranged separately from one another along the first direction.

Abstract: This device includes a first base layer of a first conduction type. A second base-layer of a second conduction type is provided above the first base-layer. A first semiconductor layer of the first conduction type is above an opposite side of the second base-layer to the first base-layer. A second semiconductor layer of the second conduction type is above an opposite side of the first base-layer to the second base-layer. A plurality of first electrodes are provided at the first semiconductor layer and the second base-layer via first insulating films. A second electrode is provided between adjacent ones of the first electrodes and provided at the first semiconductor layer and the second base-layer via a second insulating film. A resistance of the first base-layer above a side of the second electrode is lower than a resistance of the first base-layer above a side of the first electrodes.

Abstract: First and second n-type field stop layers in an n? drift region come into contact with a p+ collector layer. The first n-type field stop layer has an impurity concentration reduced toward an n+ emitter region at a steep gradient. The second n-type field stop layer has an impurity concentration distribution in which impurity concentration is reduced toward the n+ emitter region at a gentler gradient than that in the first n-type field stop layer and the impurity concentration of a peak position is less than that in the impurity concentration distribution of the first n-type field stop layer. The impurity concentration distributions of the first and second n-type field stop layers have the same peak position. The first and second n-type field stop layers are formed using annealing and first and second proton irradiation processes which have the same projected range and different acceleration energy levels.

Abstract: Exemplary embodiments provide a substrate for mounting multiple power transistors. The substrate has a first metallization on which the power transistors are mountable with an associated collector or emitter, and which extends in at least one line on the substrate. A second metallization extends in an area next to the at least one line of the first metallization, for connection to the remaining ones of the emitters or collectors of the power transistors. A third metallization allows connection to gate contact pads of the power transistors. The third metallization includes a gate contact and at least two gate metallization areas, which are interconnectable. The gate metallization areas are arranged in parallel to the at least one line and spaced apart in a longitudinal direction of the at least one line. At least one gate metallization area is provided as a gate island surrounded on the substrate by the second metallization.

Abstract: A lateral bipolar transistor with deep emitter and deep collector regions is formed using multiple epitaxial layers of the same conductivity type. Deep emitter and deep collector regions are formed without the use of trenches. Vertically aligned diffusion regions are formed in each epitaxial layer so that the diffusion regions merged into a contiguous diffusion region after annealing to function as emitter or collector or isolation structures. In another embodiment, a lateral trench PNP bipolar transistor is formed using trench emitter and trench collector regions. In yet another embodiment, a lateral PNP bipolar transistor with a merged LDMOS transistor is formed to achieve high performance.

Abstract: A layer of a silicon germanium alloy containing 30 atomic percent or greater germanium and containing substitutional carbon is grown on a surface of a semiconductor layer. The presence of the substitutional carbon in the layer of silicon germanium alloy compensates the strain of the silicon germanium alloy, and suppresses defect formation. Placeholder semiconductor fins are then formed to a desired dimension within the layer of silicon germanium alloy and the semiconductor layer. The placeholder semiconductor fins will relax for the most part, while maintaining strain in a lengthwise direction. An anneal is then performed which may either remove the substitutional carbon from each placeholder semiconductor fin or move the substitutional carbon into interstitial sites within the lattice of the silicon germanium alloy. Free-standing permanent semiconductor fins containing 30 atomic percent or greater germanium, and strain in the lengthwise direction are provided.

Abstract: Embodiments of mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stacks. The semiconductor device structure includes doped regions formed in the substrate. The semiconductor device structure also includes a strained source and drain (SSD) structure adjacent to the gate spacers, and the doped regions are adjacent to the SSD structure. The semiconductor device structure includes SSD structure has a tip which is closest to the doped region, and the tip is substantially aligned with an inner side of gate spacers.

Abstract: A transistor includes a gate terminal, a source terminal and a drain terminal. At least one of the source and drain terminals has a layered configuration that includes a terminal layer and an intervening layer. The terminal layer has a top surface and a bottom surface. The intervening layer is located within the terminal layer, between and spaced from the top and bottom surfaces, is oriented to be perpendicular to current flow, and is less than one tenth the thickness of the terminal layer. The terminal layer and the intervening layer include a common semiconductive compound and a common dopant, with a concentration of the dopant in the intervening layer being over ten times an average concentration of the dopant in the terminal layer.

Abstract: In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type or an intrinsic type. The device further includes a second semiconductor layer of the first conductivity type or the intrinsic type disposed above the first semiconductor layer. The device further includes a third semiconductor layer of a second conductivity type including a first upper portion in contact with the first semiconductor layer, a second upper portion located at a lower position than the first upper portion, a first side portion located between the first upper portion and the second upper portion, and a second side portion located at a lower position than the first side portion.

Abstract: According to one embodiment, a semiconductor device includes a nitride semiconductor layer, a first electrode provided on the layer, a second electrode provided on the layer, a insulating film provided on the layer, a first control electrode provided on the film, and a conductor provided on the film. The first control electrode includes a first edge, and a second edge. The first edge is provided between the second edge and the first electrode. The conductor includes a first portion and a third edge positioned between the first portion and the first electrode. An electric field strength at a first region is substantially equal to an electric field strength at a second region. The first region overlaps the first edge when projected onto a plane perpendicular to a stacking direction. The second region overlaps the third edge when projected onto the plane.

Abstract: An integrated circuit device includes a plurality of basic cells that each have a first transistor pair including two p-channel transistors of a first-type and a second transistor pair including two p-channel transistors of a second-type. The second-type transistors are configured to consume less power and operate more slowly than the first-type transistors. The basic cell further includes a third transistor pair of two n-channel transistors of a third-type. The third transistor pair is disposed between the first and second transistor pairs. Gate electrodes are separately provided for each transistor in the first, second, and third transistor pairs. The basic cell thus formed can be used to fabricate various circuit elements by making wiring connections between various transistor pairs and/or basic cells.

Abstract: A solid-state imaging device includes a pixel having a photoelectric conversion element which generates a charge in response to incident light, a first transfer gate which transfers the charge from the photoelectric conversion element to a charge holding section, and a second transfer gate which transfers the charge from the charge holding section to a floating diffusion. The first transfer gate includes a trench gate structure having at least two trench gate sections embedded in a depth direction of a semiconductor substrate, and the charge holding section includes a semiconductor region positioned between adjacent trench gate sections.

Abstract: The present invention is notably directed to an electromechanical switching device having: two electrodes, including: a first electrode, having layers of a first 2D layered material, which layers exhibit a first surface; and a second electrode, having layers of a second 2D layered material, which layers exhibit a second surface vis-à-vis said first surface; and an actuation mechanism, where: each of the first and second 2D layered materials is electrically conducting; and at least one of said two electrodes is actuatable by the actuation mechanism to modify a distance between the first surface and the second surface, such as to modify an electrical conductivity transverse to each of the first surface and the second surface and thereby enable current modulation between the first electrode and the second electrode.

Abstract: Techniques are disclosed for transistor fabrication including a sacrificial protective layer for source/drain (S/D) regions to minimize contact resistance. The sacrificial protective layer may be selectively deposited on S/D regions after such regions have been formed, but prior to the deposition of an insulator layer on the S/D regions. Subsequently, after contact trench etch is performed, an additional etch process may be performed to remove the sacrificial protective layer and expose a clean S/D surface. Thus, the sacrificial protective layer can protect the contact locations of the S/D regions from contamination (e.g., oxidation or nitridation) caused by insulator layer deposition. The sacrificial protective layer can also protect the S/D regions from undesired insulator material remaining on the S/D contact surface, particularly for non-planar transistor structures (e.g., finned or nanowire/nanoribbon transistor structures).

Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material, wherein a bottom portion of the upper portion comprises a dopant with a first peak concentration; a middle portion between the lower portion and upper portion, wherein the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; and an isolation structure surrounding the fin structure, wherein a portion of the isolation structure adjacent to the bottom portion of the upper portion comprises the dopant with a second peak concentration equal to or greater than the first peak concentration.

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The channel region is separated a first distance from a first portion of the first type region. The semiconductor device includes a gate region surrounding the channel region. A first portion of the gate region is separated a second distance from the first portion of the first type region. The second distance is greater than the first distance.

Abstract: Backside illuminated sensors and methods of manufacture are described. Specifically, a backside illuminated sensor with a dipole modulating layer near the photodiode is described.

Abstract: According to one embodiment, a solid-state imaging device includes a photodiode includes an N-type region and a P-type region, a floating diffusion region, and a transfer transistor. The N-type diffusion region of the photodiode comprises a first semiconductor region and a second semiconductor region formed shallower than the first semiconductor region. An end portion of the first semiconductor region is positioned on the floating diffusion region side rather than an end portion of a gate electrode of the transfer transistor. An end portion of the second semiconductor region is set in substantially the same position as that of the end portion of the gate electrode of the transfer transistor.

Abstract: A MOS solid-state imaging device is provided in which withstand voltage and 1/f noise of a MOS transistor are improved. In the MOS solid-state imaging device whose unit pixel has at least a photoelectric converting portion and a plurality of field effect transistors, the thickness of gate insulating film in a part of the field effect transistors is different from the thickness of gate insulating film in the other field effect transistors among the plurality of the field effect transistors.

Abstract: According to an embodiment, semiconductor device includes a semiconductor substrate, first and second isolation regions provided in the semiconductor substrate, extending in a first direction, and adjacent to each other, first and second word lines provided in the semiconductor substrate, extending in a second direction crossing the first direction, and adjacent to each other, first and second upper insulating regions provided on the first and second word lines, extending in the second direction, and adjacent to each other, a source/drain diffusion region provided in a surface area of the semiconductor substrate and between the first and second isolation regions, and including a portion positioned between the first and second upper insulating regions, and a first conductive portion provided in the source/drain diffusion region and formed of a material containing metal.

Abstract: According to one embodiment, a magnetic memory includes a cell transistor including a first source/drain diffusion layer and a second source/drain diffusion layer, a first contact on the first source/drain diffusion layer, a memory element on the first contact, and a second contact on the second source/drain diffusion layer, the second contact including a first plug on the second source/drain diffusion layer, and a second plug on the first plug.

Abstract: Disclosed herein is an apparatus that includes a ferrocapacitor having a sidewall. An etch stopping film is disposed along the sidewall of the ferrocapacitor, with a hydrogen barrier film disposed between the etch stopping film and the sidewall of the ferrocapacitor.

Abstract: Some embodiments include a DRAM array layout. Wordlines extend along a first direction, and bitlines extend along a second direction that crosses the first direction. Cell active material structures are at intersections of the wordlines and bitlines. The cell active material structures have a first side coupled to a bitline and a second side coupled to a capacitor. The second side is on an opposite side of a wordline passing through a cell active material structure relative to the first side. Each cell active material structure has a connection to a bitline which is not shared with any other cell active material structures. Some embodiments include DRAM arrays and semiconductor constructions.

Abstract: A single-poly NVM cell includes a substrate having an isolation region separating a first OD region from a second OD region, a read transistor within the first OD region, and a coupling capacitor within the second OD region. A first ion well completely overlaps with the first oxide define region. The read transistor includes a drain region, a source region, a channel region, a single-poly floating gate overlying the channel region, and a gate dielectric layer between the floating gate and the channel region. The coupling capacitor includes a shallow ion well, a heavily-doped, ultra-shallow dopant region in the shallow ion well, a single-poly charge-storage floating gate overlying the heavily-doped, ultra-shallow dopant region, and a gate dielectric layer under the charge storage floating gate. The shallow ion well has a junction depth that is substantially equal to or shallower than a trench depth of the isolation region.

Abstract: A semiconductor device includes stacked groups each including interlayer insulating patterns and conductive patterns and stacked in at least two tiers, wherein the insulating patterns and the conductive patterns are alternately stacked over a substrate and separated by slits, and a support body including holes and formed between the stacked groups.

Abstract: A semiconductor device includes memory cell units, each including memory cell transistors, a first transistor at a first end of the memory cell transistors, and a second transistor at a second end of the memory cell transistors. The memory cell units are arranged so that adjacent memory cell units have first transistors thereof facing each other or second transistors thereof facing each other, and so that a distance between the first transistors of the adjacent memory cell units is larger than a distance between the second transistors of the adjacent memory cell units. The semiconductor device further includes a first silicon nitride layer covering a first diffusion layer of the first transistors, a second silicon nitride layer covering a second diffusion layer of the second transistors. A thickness of the second silicon nitride layer is smaller than a thickness of the first silicon nitride layer.

Abstract: A non-volatile memory device includes an isolation layer formed over a substrate to define an active region, a floating gate formed over the substrate, a selection gate formed over the substrate on one side of the floating gate and formed to be adjacent to the floating gate with a first gap from the floating gate, a control plug formed over the isolation layer on the other side of the floating gate and formed to be adjacent to the floating gate with a second gap from the floating gate, and a charge blocking layer formed to gap-fill the first gap and the second gap.

Abstract: A semiconductor memory device according to an embodiment includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a plurality of first electrodes provided on the first insulating film, a second insulating film provided on a side surface of the first electrodes and on an upper surface of the first electrodes, and a second electrode insulated from the first electrodes by the second insulating film. The second electrode includes an interconnect portion provided on the second insulating film, and a downward-extending portion extending into a space between the first electrodes from the interconnect portion. A lower end portion of the downward-extending portion is not covered with the second insulating film.

Abstract: According to one embodiment, a memory cell transistor is obtained by forming a first gate insulating film, a first conductive film of a first conductivity type, a first inter-electrode insulating film, and a second conductive film of the first conductivity type, in this order, and a peripheral transistor which is obtained by forming a second gate insulating film, a third conductive film of the second conductivity type opposite to the first conductivity type, the inter-electrode insulating film, a fourth conductive film in which the first conductivity type dopant is doped, a barrier film, and a fifth conductive film in which the second conductivity type dopant is doped, in which in the peripheral transistor, an opening is formed on the barrier film, the fourth conductive film, and the inter-electrode insulating film, and the fifth conductive film is formed so as to come in contact with the third conductive film through the opening.

Abstract: According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality of conductive films stacked on the second layer, and a semiconductor pillar which penetrates the stacked body and the second layer and reaches the first layer. The semiconductor pillar includes a semiconductor film formed along an extending direction of the semiconductor pillar, and a memory film which covers a periphery of the semiconductor film. The memory film includes a first portion formed between the stacked body and the semiconductor film and a second portion formed between the second layer and the semiconductor film. An outer periphery of the second portion in a plane perpendicular to the extending direction is wider than an outer periphery of the first portion on a second layer side of the stacked body.

Abstract: Methods and related structures are disclosed for forming contact landing regions in split-gate NVM (non-volatile memory) systems. A dummy select gate structure is formed while also forming select gates for split-gate NVM cells. A control gate layer is formed over the select gates and the dummy select gate structure, as well as an intervening charge storage layer. The control gate material will fill in gaps between the select gate material and the dummy select gate material. A non-patterned spacer etch is then used to etch the control gate layer to form a contact landing region associated with the dummy select gate structure while also forming spacer control gates for the split-gate NVM cells. The disclosed embodiments provide improved (e.g., more planar) contact landing regions without requiring additional processing steps and without increasing the pitch of the resulting NVM cell array.