Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.

Abstract: According to one embodiment, a method of manufacturing a magneto-resistive element, includes forming a first ferromagnetic layer on a substrate, forming a tunnel barrier layer on the first ferromagnetic layer, forming a second ferromagnetic layer containing B on the tunnel barrier layer, exposing a laminate of the first ferromagnetic layer, the tunnel barrier layer, and the second ferromagnetic layer under a pressurized atmosphere, and annealing the laminate while being exposed to the pressurized atmosphere, thereby promoting the orientation of the second magnetic layer.

Abstract: According to one embodiment, a method of manufacturing a magnetoresistive element includes forming a first ferromagnetic layer on a base substrate, forming a tunnel barrier layer on the first ferromagnetic layer, forming a second ferromagnetic layer containing B on the tunnel barrier layer, and performing annealing in a gas-phase atmosphere including a gas, after formation of the second ferromagnetic layer, the gas producing a reaction product with B, the reaction product having a melting point lower than a treatment temperature.

Abstract: According to one embodiment, magneto-resistive element, includes a first ferromagnetic layer formed on an underlying substrate, a tunnel barrier layer formed on the first ferromagnetic layer, a second ferromagnetic formed on the tunnel barrier layer and a cap layer formed on the second ferromagnetic layer, and a surface tension of the cap layer is equal to or less than that of the second ferromagnetic layer.

Abstract: According to one embodiment, a semiconductor device includes a MRAM chip including a semiconductor substrate and a memory cell array area includes magnetoresistive elements which are provided on the semiconductor substrate, and a magnetic shield layer separated from the MRAM chip, surrounding the memory cell array area in a circumferential direction of the MRAM chip, and having a closed magnetic path.

Abstract: According to one embodiment, a magnetic memory device includes a semiconductor substrate, a memory cell array area on the semiconductor substrate, the memory cell array area including magnetoresistive elements, each of the magnetoresistive elements having a reference layer with an invariable magnetization, a storage layer with a variable magnetization, and a tunnel barrier layer therebetween, a magnetic field generating area which generates a first magnetic field cancelling a second magnetic field applying from the reference layer to the storage layer, and which is separated from the magnetoresistive elements, and a closed magnetic path area functioning as a closed magnetic path of the first magnetic field, and surrounding the memory cell array area and the magnetic field generating area.

Abstract: According to one embodiment, a magnetic memory includes a magnetoresistive effect element provided in a memory cell, the magnetoresistive effect element including a multilayer structure including a first magnetic layer, a second magnetic layer, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer, a first electrode provided on an upper portion of the multilayer structure and including a first material, and a first film provided on a side surface of the first electrode and including a second material which is different from the first material of the first electrode.

Abstract: According to one embodiment, a magnetoresistive element includes a storage layer having a variable magnetization direction, a reference layer having an invariable magnetization direction, a tunnel barrier layer formed between the storage layer and the reference layer, and a heater layer formed on an opposite side to the tunnel barrier layer of the storage layer. The storage layer includes a first layer formed on a side of the heater layer, and a second layer formed on the side of the tunnel barrier layer and having a Curie temperature higher than that of the first layer.

Abstract: According to one embodiment, a first magnetic layer, a first nonmagnetic layer on the first magnetic layer, a second magnetic layer on the first nonmagnetic layer, a second nonmagnetic layer on the second magnetic layer, and a third magnetic layer on the second nonmagnetic layer, the third magnetic layer having a sidewall includes a material which is included in the second nonmagnetic layer.

Abstract: According to one embodiment, a magnetoresistive element is disclosed. The element includes a lower electrode, a stacked body provided on the lower electrode and including a first magnetic layer, a tunnel barrier layer and a second magnetic layer. The first magnetic layer is under the tunnel barrier layer, the second magnetic layer is on the tunnel barrier layer. The first magnetic layer includes a first region and a second region outside the first region to surround the first region. The second region includes an element in the first region and other element being different from the element.

Abstract: According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer. The reference layer includes a first region, and a second region provided outside the first region to surround the same. The second region contains an element contained in the first region and another element being different from the element. The magnetoresistive element further includes a storage layer, and a tunnel barrier layer provided between the reference layer and the storage layer. The storage layer is free from the another element.

Abstract: According to one embodiment, a magnetic memory device includes a magnetoresistance effect element having a structure in which a first magnetic layer, a nonmagnetic layer, a second magnetic layer, and a third magnetic layer are stacked, wherein the third magnetic layer comprises a first region and a plurality of second regions, and each of the second regions is surrounded by the first region, has conductivity, and has a greater magnetic property than the first region.

Abstract: According to one embodiment, a magnetic memory is disclosed. The magnetic memory includes a substrate, and a magnetoresistive element provided on the substrate. The magnetoresistive element includes a first magnetic layer, a tunnel barrier layer on the first magnetic layer, and a second magnetic layer on the tunnel barrier layer. The first magnetic layer or the second magnetic layer includes a first region, second region, and third region whose ratios of crystalline portion are higher in order closer to the tunneling barrier.

Abstract: According to one embodiment, a magnetic memory is disclosed. The memory includes a conductive layer containing a first metallic material, a stacked body formed above the conductive layer and including a first magnetic layer containing a second metallic material, a second magnetic layer, and a tunnel barrier layer formed between the first magnetic layer and the second magnetic layer, and an insulating layer formed on a side face of the stacked body and containing an oxide of the first metallic material. A standard electrode potential of the first metallic material is lower than the standard electrode potential of the second metallic material.

Abstract: According to one embodiment, a magnetic memory includes first and second magnetoresistive effect elements neighboring in a first direction in a cell array of a substrate, each of the first and second magnetoresistive effect elements including a first magnetic layer with an invariable direction of magnetization, a second magnetic layer with a variable direction of magnetization, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer. Directions of magnetization of the first magnetic layers of the first and second magnetoresistive effect elements are different from each other.

Abstract: According to one embodiment, a magnetic memory is disclosed. The magnetic memory includes a substrate, a first magnetoresistive element provided on the substrate. A second magnetoresistive element which is provided on the substrate and is arranged next to the first magnetoresistive element. Each of the first and second magnetoresistive elements includes a first magnetic layer, a tunnel barrier layer and a second magnetic layer. The tunnel barrier layer is provided on the first magnetic layer, the second magnetic layer is provided on the tunnel barrier layer. A first stress member having a tensile stress as an internal stress is provided on an area including a side face of the stacked body.

Abstract: According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer, a tunnel barrier layer, a storage layer. The storage layer includes a first region and a second region provided outside the first region to surround the first region, the second region including element included in the first region and another element being different from the element. The magnetoresistive element further includes a cap layer including a third region and a fourth region provided outside the third region to surround the third region, the fourth region including an element included in the third region and the another element.

Abstract: According to one embodiment, a magnetic memory is disclosed. The memory includes a conductive layer containing a first metal material, a stacked body above the conductive layer, and including a first magnetization film containing a second metal material, a second magnetization film, and a tunnel barrier layer between the first magnetization film and the second magnetization film, and an insulating layer on a side face of the stacked body, and containing an oxide of the first metal material. The first magnetization film and/or the second magnetization film includes a first region positioned in a central portion, and a second region positioned in an edge portion and containing As, P, Ge, Ga, Sb, In, N, Ar, He, F, Cl, Br, I, Si, B, C, O, Zr, Tb, S, Se, or Ti.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a magnetoresistive element formed on a semiconductor substrate, a first contact plug which extends through an interlayer dielectric film formed on the semiconductor substrate and immediately below the magnetoresistive element, has a bottom surface in contact with an upper surface of the semiconductor substrate, and is adjacent to the magnetoresistive element, and an insulating film formed between the magnetoresistive element and the first contact plug and on the interlayer dielectric film, wherein the insulating film includes a first region positioned on a side of the interlayer dielectric film, and a second region positioned in the insulating film and on an upper surface of the first region, the insulating film is made of SiN, and the first region is a nitrogen rich film compared to the second region.

Abstract: Magnetic memory devices and methods of manufacturing the same are disclosed. A method may include forming a magnetic tunnel junction layer on a substrate, forming mask patterns on the magnetic tunnel junction layer, and sequentially performing a plurality of ion implantation processes using the mask patterns as ion implantation masks to form an isolation region in the magnetic tunnel junction layer. The isolation region may thereby define magnetic tunnel junction parts that are disposed under corresponding ones of the mask patterns. A magnetic memory device may include a plurality of magnetic tunnel junction parts electrically and magnetically isolated from each other through the isolation region.

Abstract: A device and a method of forming a device are presented. A substrate is provided. Front end of line processing is performed to form circuit component on the substrate and back end of line processing is performed to include the uppermost inter level dielectric (ILD) layer. The uppermost ILD layer includes first and second interconnects. A pad level is formed over the uppermost ILD layer. A storage unit of a memory cell is provided in the pad level. The storage unit is coupled to the first interconnect of the uppermost ILD layer. A cell interconnect and a pad interconnect are formed in the pad level. The cell interconnect is formed on top of and coupled to the storage unit and the pad interconnect is coupled to the second interconnect in the uppermost ILD layer.

Abstract: A method of forming a line of magnetic tunnel junctions includes forming magnetic recording material over a substrate, non-magnetic material over the recording material, and magnetic reference material over the non-magnetic material. The substrate has alternating outer regions of reactant source material and insulator material along at least one cross-section. The reference material is patterned into a longitudinally elongated line passing over the alternating outer regions. The recording material is subjected to a set of temperature and pressure conditions to react with the reactant of the reactant source material to form regions of the dielectric material which longitudinally alternate with the recording material along the line and to form magnetic tunnel junctions along the line which individually comprise the recording material, the non-magnetic material, and the reference material that are longitudinally between the dielectric material regions.

Abstract: A vertical Hall Effect sensor is provided having a high degree of symmetry between its bias modes, can be adapted to exhibit a small pre-spinning systematic offset, and complies with the minimal spacing requirements allowed by the manufacturing technology (e.g., CMOS) between the inner contacts. These characteristics enable the vertical Hall Effect sensor to have optimal performance with regard to offset and sensitivity.

Abstract: Solid-state imaging devices, methods to produce the solid-state imaging devices, and electronic apparatuses including the solid-state imaging devices, where the solid-state imaging devices include a semiconductor substrate including a light receiving surface; a plurality of photoelectric conversion parts provided within the semiconductor substrate; and a plurality of reflection portions provided in the semiconductor substrate on a side of the photoelectric conversion parts that is opposite from the light receiving surface; where each of the reflection portions includes a reflection plate and a plurality of metal wirings, and where the plurality of metal wirings are disposed in a same layer of the semiconductor substrate as the reflection plate.

Abstract: A novel germanium (Ge) photodetector is disclosed, containing a stripe layer including Ge, a substrate supporting the stripe layer, and P and N regions, which are located inside the substrate and near opposite sides of the stripe. The stripe layer containing Ge for light absorption is operated in a slow-light mode by adding combinations of a gradual taper indent structure and a periodic indent structure to reduce light scatterings and to control light group velocity inside the stripe. Due to the slower light traveling velocity inside the stripe, the absorption coefficient of the stripe containing Ge is upgraded to be 1 to 2 orders of magnitude larger than that of a traditional bulk Ge at L band, and so the absorption coefficient reaches more than 1 dB/?m at the wavelength of 1600 nm.

Abstract: According to one embodiment, a photodiode includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, and a film. The second semiconductor layer is provided in the first semiconductor layer. The third semiconductor layer is provided in the first semiconductor layer so as to surround the second semiconductor layer. Each of one ends of the second and third semiconductor layers is located at an upper surface of the first semiconductor layer. The first to third semiconductor layers include first to third impurity concentrations respectively. The second and third impurity concentrations are higher than the first impurity concentration. The film is provided above the third semiconductor layer, and blocks light to enter into a neighborhood of the third semiconductor layer.

Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate and a memory array. The semiconductor substrate has a first face. The memory array region is provided on the first face and includes a plurality of semiconductor pillars. The semiconductor pillars extend in a first direction perpendicular to the first face. Each of the semiconductor pillars includes a plurality of memory cells connected in series. Each of the semiconductor pillars is disposed at the nodes of a honeycomb shape when viewed in the first direction. When the semiconductor pillars are projected onto a first plane along the first and second directions perpendicular to the first direction, a component in the second direction of an interval between the semiconductor pillars has first and second intervals repeated alternately. The second interval is an integer multiple of the first interval greater than or equal to 2.

Abstract: According to one embodiment, a semiconductor memory device includes: a first semiconductor region extending in a first direction; second semiconductor regions extending in a second direction crossing the first direction from the first semiconductor region and arranged in the first direction; and a first element isolation region provided between the second semiconductor regions. A width of the first semiconductor region in the second direction is wider than a width of the second semiconductor region in the first direction.

Abstract: An integrated circuit structure includes a two-tier die including a first tier and a second tier over and bonded to the first tier. The first tier includes a first substrate including a semiconductor material, an active device at a surface of the first substrate, and a first interconnect structure over the first substrate, wherein the first tier is free from passive devices therein. The second tier includes a second substrate bonded to and in contact with the first interconnect structure, and a second interconnect structure over the second substrate, wherein metal lines in the second interconnect structure are electrically coupled to the first interconnect structure. The second tier further includes a plurality of through-vias penetrating through the second substrate, wherein the plurality of through-vias lands on metal pads in a top metal layer of the first interconnect structure, and a passive device in the second interconnect structure.

Abstract: According to a structure herein, a silicon substrate has an active device in the silicon substrate. A dielectric film is on the active device. An isolation trench is in the dielectric film surrounding the active device. The trench extends through the dielectric film and at least partially into the silicon substrate. A core is in the isolation trench. The core comprises material having thermal conductivity greater than silicon dioxide and electrical conductivity approximately equal to silicon dioxide.

Abstract: A semiconductor package is provided that has a transformer formed within a multilayer dielectric laminate substrate. The transformer has a first inductor coil formed in one or more dielectric laminate layers of the substrate, a second inductor coil formed in one or more dielectric laminate layers of the substrate, and an isolation barrier comprising two or more dielectric laminate layers of the multilayer substrate positioned between the first inductor coil and the second inductor coil. The transformer may be mounted on a lead frame along with one or more integrated circuits and molded into a packaged isolation device.

Abstract: A capacitor structure is provided, which includes a conductive substrate, a first dielectric layer, and a first metal layer. The conductive substrate includes a first surface and at least one first concave located on the first surface. The first dielectric layer covers the first surface and the first concave. The first metal layer covers the first dielectric layer, wherein the first dielectric layer and the first metal layer respectively have concave structures corresponding to the first concave. A stack-type capacitor structure is also provided.

Abstract: A novel integrated circuit and method thereof are provided. The integrated circuit includes a plurality of first interconnect pads, a plurality of second interconnect pads, a first inter-level dielectric layer, a thin film resistor, and at least two end-caps. The end-caps, which are connectors for the thin film resistor, are positioned at the same level with the plurality of second interconnect pads. Therefore, an electrical connection between the end-caps and the plurality of second interconnect pads can be formed by directly connection of them. An integrated circuit with a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

Abstract: A nitride semiconductor growth apparatus of the present invention comprises a chamber into which a reactive gas containing nitrogen is to be introduced as a material gas and a reaction part which is placed in the chamber and in which the material gas is brought into reaction to grow a nitride semiconductor. In the nitride semiconductor growth apparatus, in a region which includes a reaction part and part of an upstream side from a reaction part with respect to a flow of a material gas, portions to be in contact with the material gas (a gas introducing part, a current introducing part and a view port part and the like) are made from non-copper material (i.e., material containing no copper).

Abstract: A method includes providing a semiconductor wafer including multiple semiconductor chips, forming a first scribe line on a frontside of the semiconductor wafer, wherein the first scribe line has a first width and separates semiconductor chips of the semiconductor wafer, forming a second scribe line on the frontside of the semiconductor wafer, wherein the second scribe line has a second width and separates semiconductor chips of the semiconductor wafer, wherein the first scribe line and the second scribe line intersect in a crossing area which is greater than a product of the first width and the second width, and plasma etching the semiconductor wafer in the crossing area.

Abstract: A wafer includes a first interposer having a first patterned metal layer and a second interposer having a second patterned metal layer. The wafer includes a metal connection in a scribe region of the wafer that electrically couples the first patterned metal layer of the first interposer with the second patterned metal layer of the second interposer forming a global wafer network. The wafer further includes a probe pad located in the scribe region that is electrically coupled to the global wafer network.

Abstract: Consistent with an example embodiment, there is a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side. The method comprises pre-grinding the backside of a wafer substrate to a thickness. The front-side of the wafer is mounted onto a protective foil. A laser is applied to the backside of the wafer, at first focus depth to define a secondary modification zone in saw lanes. To the backside of the wafer, a second laser process is applied, at a second focus depth shallower than that of the first focus depth, in the saw lanes to define a main modification zone, the secondary modification defined at a pre-determined location within active device boundaries, the active device boundaries defining an active device area. The backside of the wafer is ground down to a depth so as to remove the main modification zone. The IC device die are separated from one another by stretching the protective foil.

Abstract: Semiconductor devices with air gaps around the through-silicon via are formed. Embodiments include forming a first cavity in a substrate, filling the first cavity with a sacrificial material, forming a second cavity in the substrate, through the sacrificial material, by removing a portion of the sacrificial material and a portion of the substrate below the sacrificial material, filling the second cavity with a conductive material, removing a remaining portion of the sacrificial material to form an air gap between the conductive material and the substrate, and forming a cap over the air gap.

Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.

Abstract: A method of etching a trench in a substrate is provided. The method repeatedly alternates between using a fluorine-based plasma to etch a trench, which has trench sidewalls, into a selected region of the substrate; and using a fluorocarbon plasma to deposit a liner on the trench sidewalls. The liner, when formed and subsequently etched, has an exposed sidewall surface that includes scalloped recesses. The trench, which includes the scalloped recesses, is then bombarded with a molecular beam where the molecules are directed on an axis parallel to the trench sidewalls to reduce the scalloped recesses.

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of pillars vertically extending from the semiconductor substrate, each pillar including a groove formed in an upper surface thereof, a salicide layer formed to cover the upper surface and a lateral circumference of an upper end of each pillar and a lower electrode formed to cover an upper surface and a lateral surface of the salicide layer.

Abstract: Provided are a III nitride semiconductor device which can be operated at a lower voltage can be provided, in which device a good ohmic contact is achieved between the (000-1) plane side of the III nitride semiconductor layer and the electrode and a method of producing the III nitride semiconductor device. A III nitride semiconductor device of the present invention includes a plurality of protrusions rounded like domes in a predetermined region on the (000-1) plane side of the III nitride semiconductor layer; and an electrode on the upper surface of the predetermined region.

Abstract: A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. A first extension line from a first bottom edge intersects with a second extension line from a second bottom edge to form a first base point. A first projection line is formed on the first surface, an extension line of the first projection line intersects with the second bottom edge to form a first intersection point, a second projection line is formed on the first surface, and an extension line of the second projection line intersects with the first bottom edge to form a second intersection point. A zone by connecting the first base point, the first intersection point and the second intersection point is the first anti-stress zone.

Abstract: A semiconductor device includes a first passivation layer including a first passivation portion and a second passivation portion substantially diametrically opposite the first passivation portion. The semiconductor device includes a first corner of the first passivation portion separated a first distance from a second corner of the second passivation portion. A third corner of the first passivation portion is separated a second distance from a fourth corner of the second passivation portion.

Abstract: A method of manufacturing a semiconductor device includes: forming a first electrode on a first semiconductor substrate; coating the semiconductor substrate with an insulating material having a first viscosity at a first temperature, having a second viscosity lower than the first viscosity at a second temperature higher than the first temperature, and having a third viscosity higher than the second viscosity at a third temperature higher than the second temperature; and forming a first insulating film by curing the insulating material. In this method, the forming the first insulating film includes: bringing the insulating material to the second viscosity by heating the insulating material under a first condition; and bringing the insulating material to the third viscosity by heating the insulating material under a second condition. The first condition and the second condition are different in their temperature rising rate.

Abstract: Presented is an integrated circuit packaged at the wafer level wafer (also referred to as a wafer level chip scale package, WLCSP), and a method of manufacturing the same. The WLCSP comprises a die having an electrically conductive redistribution layer, RDL, formed above the upper surface of the die, the RDL defining a signal routing circuit. The method comprises the steps of: depositing the electrically conductive RDL so as to form an electrically conductive ring surrounding the signal routing circuit; and coating the side and lower surfaces of the die with an electrically conductive shielding material.

Abstract: A novel radiation hardened chip package technology protects microelectronic chips and systems in aviation/space or terrestrial devices against high energy radiation. The proposed technology of a radiation hardened chip package using rare earth elements and mulitlayered structure provides protection against radiation bombardment from alpha and beta particles to neutrons and high energy electromagnetic radiation.

Abstract: A semiconductor device includes a semiconductor element in a frame body. The semiconductor element includes a first electrode electrically connected to an electrode block provided on a first side of the semiconductor element. A connection element, which in some embodiments may be a portion of the electrode block, connects the electrode block to the frame body. The semiconductor element is sealed within an enclosure formed at least in part by the frame body, the connection element, and the electrode block. The connection element includes a fragile portion which has a resistance to increases in pressure or temperature that is less than other portions of the connection element. That is, in general, the fragile portion will fail before other portions of the connection element when pressure or temperature increases, which may occur when, for example, the semiconductor element breaks down.

Abstract: A power semiconductor device comprises a lead frame unit, a control die, a first MOSFET die and a second MOSFET die, wherein the lead frame unit comprises at least a die paddle for mounting the first and second MOSFET dies, a first pin and a second pin for connecting to top electrodes of the first and second MOSFET dies, a first row of carrier pins and a second row of carrier pins disposed in-line with the first and second pins respectively for the control die to mount thereon.