Abstract: A pulse generation circuit includes a control unit configured to activate one or more of control clocks among a plurality of control clocks, and to activate one or more of select signals among a plurality of select signals, in response to one or more of sequence signals; a plurality of shifting units each configured to generate one or more of output signals, and to sequentially activate the one or more of output signals by shifting an input pulse when a corresponding control clock among the plurality of control clocks is activated; and a signal transfer unit configured to transfer one or more of output signals of a shifting unit corresponding to an activated select signal among the plurality of shifting units, as one or more of pulses.

Abstract: A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple clock domains. Each clock domain includes a clock signal and a control signal. The clock signal is configurably selected from one of the multiple clock sources. The control signal is synchronized to the clock signal. The IC also includes multiple configurable circuits. A configurable circuit can configurably operate in one of the clock domains by selecting and using the control signal and the clock signal of the clock domain.

Abstract: Methods, devices, and systems for determining location of error detection data are described. One method for operating a memory unit having a bad group of memory cells includes determining a location of where to store error detection data for data to be stored across a plurality of memory units, including the memory unit having the bad group, based at least partially on a location of the bad group and storing the error detection data in the determined location.

Abstract: A first SS (storage system) provides a first SA (storage area), a second SS provides a second SA, and first and second HSs (host systems) are coupled to the first and second SSs. First and second paths connect the first HS to the first and second SAs. Third and fourth paths connect the second HS to the first and second SAs. When the first path has a higher priority than the second path after recovery where a WR (write request) is permitted to be transmitted to the first SS, if the first SA which is a write destination for the received WR is a target in a data mirroring process, the first SS transmits a notification to stop the process. The second SS performs control such that a WR specifying the second SA as a write destination fails, and then the second HS transmits the WR using the third path.

Abstract: Aspects of the subject matter described herein relate to database connectivity behavior. In aspects, an entity seeking to access data that is replicated via instances of a database follows a plan. The plan provides information as to which instance(s) the entity is to attempt to access the data from. The plan may include connection data that indicates parameters the entity is to use in connecting to the instance(s). The plan may also indicate one or more other instances from which the entity may attempt to access the data if the client is not able to access the data from initial instance(s).

Abstract: A method begins by a dispersed storage (DS) processing module determining storage device failure information for a plurality of storage devices within a maintenance free storage container, wherein the maintenance free storage container allows for multiple storage devices of the plurality of storage devices to be in a failure mode without replacement and wherein the storage device failure information indicates storage devices of the plurality of storage devices that are in the failure mode. The method continues with the DS processing module maintaining a dynamic container address space of the maintenance free storage container based on the storage device failure information. The method continues with the DS processing module managing mapping of container addresses of the dynamic container address space to dispersed storage network (DSN) addresses of an assigned DSN address range.

Abstract: Computer program product and system to limit core file generation in a massively parallel computing system comprising a plurality of compute nodes each executing at least one task, of a plurality of tasks, by: upon determining that a first task executing on a first compute node has failed, performing an atomic load and increment operation on a core file count; generating a first core file upon determining that the core file count is below a predefined threshold; and not generating the first core file upon determining that the core file count is not below the predefined threshold.

Abstract: A method and system for checkpointing at least one application in an application group. At least one full checkpoint and at least one incremental checkpoint are created for the application in the application group. The at least one incremental application checkpoint is merged against the at least one full application checkpoint, and checkpointing across all applications in the application group is synchronized. A storage checkpoint is taken for at least one of the full checkpoint and the incremental checkpoint, and memory and storage checkpoints are synchronized and consistent.

Abstract: The data transfer control device of the present invention is capable of improving data transfer efficiency while discarding error data, a DMA parameter storing control unit (1112) temporarily stores parameters to a store resource; a data processing unit (1201) performs error detection processing for data that is transferred; a DMA parameter return control unit (1122) causes parameters used at transfer time of data for which the processing result in the error detection processing was an error to be returned as parameters for subsequent data transfer use from the store resource; and a completion notification delay control unit (1121), with regard to the parameters, causes the completion notification to a host system that indicates that data transfer has completed normally for each of the parameters to wait for normal completion of data transfer that uses parameters that had been set earlier than each of the first-mentioned parameters.

Abstract: Files related to shipping transactions are received from participants. Each of the files are processed in a first stage of a multi-stage process that includes attempting to translate the files to generate a translated file and storing an error status for each file in which the translation experienced an error. For those files that are successfully translated, they are processed in subsequent stage(s) including applying application rule(s) to those files and storing an error status for those translated files resulting in an error. A participant may view a summary of those translated files that are associated with an error status. The participant may further view details of an error to be displayed and retrieve the underlying file. The participant may edit the file to correct the issue and republish the modified file to be reprocessed in the stage of the multi-stage process that identified the error.

Abstract: Test data generation and scale up for database testing using unique common factor sequencing can include selecting a column of a table for which test data is needed and generating test data for the column that replicates cardinality characteristics of an existing production dataset and that includes a local predicate of a workload.

Abstract: A system and method for discovering fault conditions such as conflicts between applications and an operating system, driver, hardware, or a combination thereof, installed in mobile computing devices uses a mobile device running a diagnostic application. A list of applications that were launched or installed during a time period prior to an operational disruption is retrieved. A data table of combinations of incompatible programs and drivers is used to analyze the list of the applications that were launched or installed to create a list of potential fault-causing interactions due to software incompatibilities of software installed in the mobile computing device. A knowledge database is updated with data identifying at least one of the potential fault-causing interactions.

Abstract: Systems and methods are described herein for validating operation of a centrally managed network. A central controller is configured to manage a network, and an emulator configured to emulate one or more nodes in the network is connected to the central controller. The emulator determines a state value for one or more nodes in the network, and the state value represents whether the respective node is in error. The emulator receives a first plurality of policies including instructions for the nodes in the network, and whether the policies are consistent with one another is identified.

Abstract: An information processing apparatus includes an external tool unit configured to provide a man-machine interface to a debugging user; and a microcontroller. The microcontroller includes: a CPU section configured to execute a program as a debugging target in a response to a first clock signal, wherein a clock rate of the first clock signal is changed in response to an instruction from the CPU section; a first transmitting section configured to transmit debugging data to the external tool unit in response to the first clock signal; a second transmitting section configured to transmit the debugging data to the external tool unit in response to a second clock signal which is different from the first clock signal; and a receiving section configured to receive data transmitted from the external tool unit.

Abstract: A method and system for providing a self-test configuration in a device is disclosed. The method and system comprise providing a self-test mechanism in a kernel space of a memory and enabling a hook in a user space of the memory, wherein the hook is in communication with the self-test mechanism. The method and system also include running the self-test driver and utilizing the results.

Abstract: The technology disclosed relates to implementing a novel architecture of a finite state machine (abbreviated FSM) that can be used for testing. In particular, it can be used for testing communications devices and communication protocol behaviors.

Abstract: Testing a system under test includes intercepting, within a proxy system, a request from a client system sent to the system under test. The request is analyzed within the proxy system and sent to the system under test. Within the proxy system, a response from the system under test sent to the client system is intercepted. The response is instrumented creating a modified response indicating test coverage according to the request. The modified response is sent to the client system.

Abstract: A method of determining whether a set of constraints is satisfiable may include identifying a set of constraints associated with a software module. The method may also include modeling a string associated with a string constraint of the set of constraints as a parameterized array. Further, the method may include determining the satisfiability of the set of constraints based on a representation of the string constraint as a quantified expression. The satisfiability of the set of constraints may also be based on elimination of a quantifier associated with the quantified expression such that the string constraint is represented as a numeric constraint. The representation of the string constraint as a quantified expression may be based on the parameterized array that is associated with the string.

Abstract: A processor includes an execution unit, a fault mask coupled to the execution unit, and a suppress mask coupled to the execution unit. The fault mask is to store a first plurality of bit values to indicate which elements of a multi-element vector have an associated fault generated in response to execution of an instruction on the element in the execution unit. The suppress mask is to store a second plurality of bit values to indicate which of the elements are to have an associated fault suppressed. The processor also includes counter logic to increment a counter in response to an indication of a first fault associated with the first element and received from the fault mask, and an indication of a first suppression associated with the first element and received from the suppress mask. Other embodiments are described as claimed.

Abstract: A monitoring device including: a receiving unit configured to receive a malfunction notice of a data processing device, the data processing device being connected to the monitoring device which monitors running condition through a network; a malfunction device identification unit configured to identify a data processing device that is malfunctioning based on the received malfunction notice; a data obtaining unit configured to obtain running data and device data of the data processing device that is malfunctioning and an another data processing device; and a malfunction cause identification unit configured to identify a cause of the malfunction, based on the obtained running data and the obtained device data.

Abstract: An approach is described for managing error logs and corresponding error descriptors among a plurality of controller nodes of a distributed network fabric. According to such approach, an error log may include output from a runtime code trace. The runtime code trace may include storing trace statements from a currently running process in one or more of a plurality of trace buffers. The trace buffers may be memory-mapped circular buffers. Additionally, an error descriptor may be created from the error log. A globally unique identifier may be assigned to the error descriptor, and both the error descriptor and the globally unique identifier may be broadcast to each other controller node among the plurality of controller nodes.

Abstract: Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a set of transaction control registers to receive a sequence of transaction control sets that collectively describe a data transfer to be processed by the DMA controller. A bus controller reads and writes to memory while the DMA controller executes a first transaction control set to accomplish part of the data transfer described in the sequence of transaction control sets. An integrity checker determines an actual error detection code based on data or an address actually processed by the DMA controller during execution of the first transaction control set. The integrity checker also selectively flags an error based on whether the actual error detection code is the same as an expected error detection code contained in a second transaction control set of the sequence of transaction control sets.

Abstract: An electronic control device includes: a processing unit that performs a predetermined process in accordance with a program; a watchdog timer that includes a time counter reset by a pulse signal output at a given period from the processing unit and outputs a signal having levels inverted depending on whether an overflow occurs; and a latch circuit that latches the signal output from the watchdog timer and outputs a signal obtained through the latching as a first output enable signal. The processing unit stops the output of the pulse signal, when diagnosing a malfunction of the watchdog timer, and diagnoses the malfunction of the watchdog timer based on the first output enable signal output from the latch circuit, after stopping the output of the pulse signal.

Abstract: A computing device for indicating a physical layer error is described. The computing device includes a processor and instructions stored in memory that is in electronic communication with the processor. The computing device generates a command for a testing device. The command includes a directive to capture at least one physical layer signal corresponding to a communications interface between a first electronic device and a second electronic device. The computing device also obtains data representing the at least one physical layer signal. The computing device additionally stores the data in a storage device to obtain stored data. The stored data indicates any physical layer error.

Abstract: A management system includes a plurality of analyzers; and a computer system connected to the analyzers via a network, wherein each of the analyzers comprises: a data transmitter for transmitting data produced by the analyzer to the computer system via the network, and wherein the computer system includes a memory under control of a processor, the memory storing instructions enabling the processor to carry out operations, comprising: (a) receiving a plurality of data transmitted from the data transmitters of the plurality of analyzers; (b) generating an aggregate result used for determining a determination condition for making a determination as to whether or not a notification to a user of the analyzer is required based on the plurality of received data; and (c) outputting the aggregate result. A computer system and a method of providing information are also disclosed.

Abstract: A computer system records screenshots associated with a user session. In response to an error in a user application that has occurred during the user session, the computer system terminates the recording and creates a video file from the recorded screenshots. While notifying the user about the error, the computer system allows the user to select an option to play back the created video. In response to a user selection, the computer system plays back the video from a local store.

Abstract: The invention relates to an electrical or electronic system, and more specifically, to a system with a bus, and a method to transmit data, in particular error data over a bus system. According to an embodiment, a method to transmit error data over a bus system that connects a plurality of modules/components/elements of an electronic system in a chain-like structure comprises in a first phase, transmitting information regarding what kinds of errors have occurred in the system, and in a second phase, transmitting information regarding where in the system an error has occurred.

Abstract: Embodiments are directed to establishing a model for testing cloud components and to preventing cascading failures in cloud components. In one scenario, a computer system models identified cloud components (including cloud hardware components and/or cloud software components) as health entities. Each health entity is configured to provide state information about the cloud component. The computer system establishes declarative safety conditions which declaratively describe cloud computing conditions that are to be maintained at the identified cloud components. The computer system then tests against the declarative safety conditions to determine which cloud components are or are becoming problematic. Upon determining that an error has occurred, the computer system notifies users of the error and the component at which the error occurred. Guarded interfaces are established to ensure that actions taken to fix the error do not cause further failures.

Abstract: An identification code generation method and a management method for a non-volatile memory, and a controller and a storage system using the same are provided, and the non-volatile memory has a plurality of physical blocks. The identification code generation method includes testing the physical blocks to obtain an availability state of the physical blocks and identifying a plurality of good physical blocks or bad physical blocks among the physical blocks according to the availability state. The identification code generation method also includes generating a memory identification code corresponding to the non-volatile memory according to the good physical blocks or the bad physical blocks. Thereby, in the present invention, a unique memory identification code is generated and is prevented from being stolen.

Abstract: A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine receives a command to cause it to generate transactions to implement a memory test. The command identifies the test to implement, and the test engine generates one or more memory access transactions to implement the test on the memory device. The test engine passes the transactions to the memory controller, which can schedule the commands with its scheduler. Thus, the transactions cause deterministic behavior in the memory device because the transactions are executed as provided, while at the same time testing the actual operation of the device.

Abstract: A method and apparatus for operation of a memory module for storage of a data word is provided. The apparatus includes a memory module having a set of paired memory devices including a first memory device to store a first section of a data word and a second memory device to store a second section of the data word when used in failure free operation. The apparatus may further include a first logic module to perform a write operation by writing the first and second sections of the data word to both the first memory device and the second memory device upon the determination of certain types of failure. The determination may include that a failure exists in the word section storage of either the first or second memory devices but that no failures exist in equivalent locations of word section storage in the two memory devices.

Abstract: A method of correcting stored data includes reading data stored in a portion of a nonvolatile memory. The method includes, for each particular bit position of the read data, updating a count of data error instances associated with the particular bit position in response to detecting that the read data differs from a corresponding reference value of the particular bit position. The reading of the first portion and the updating of the counts of data error instances are performed for a particular number of repetitions. The method includes identifying each bit position having an associated count of data error instances equal to the particular number of repetitions as a recurring error bit position.

Abstract: An embodiment of a circuit includes a data latch and a plurality of cascaded latches, wherein a first of the plurality of cascaded latches is configured to receive a first signal from the data latch and each subsequent cascaded latch is configured to receive a data output signal of a preceding cascaded latch, and an error-detection circuit configured to receive the respective data output signals and detect error in operation of the cascaded latches based thereon.

Abstract: An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.

Abstract: A system includes a controller configured for executing the test of the digital circuit, a memory configured for storing a status of the digital circuit, and a state machine configured for controlling, before the execution of the test, the storage into the memory of the status of the digital circuit and configured for controlling, after the execution of the test, restoring the status of the digital circuit based on the status stored in the memory.

Abstract: A semiconductor integrated circuit has: N input terminals; N output terminals; a plurality of flip-flops including N flip-flops and R redundant flip-flops; a selector section configured to select N selected flip-flops from the plurality of flip-flops depending on reconfiguration information and to switch data flow such that data input to the N input terminals are respectively output to the N output terminals by the N selected flip-flops; and an error detection section. At a test mode, the N flip-flops form a scan chain and a scan data is input to the scan chain. The error detection section detects an error flip-flop included in the N flip-flops based on scan input/output data respectively input/output to/from the N flip-flops at the test mode and further generates the reconfiguration information such that the detected error flip-flop is excluded from the N selected flip-flops.

Abstract: Background scan cells are selected from scan cells in a circuit based on specified bit distribution information for a plurality of test cubes generated for testing the circuit. A main portion and a background portion are then determined for each test cube in the plurality of test cubes. The background portion corresponds to the background scan cells. Test cubes in the plurality of test cubes that have compatible main portions are merged into test cube groups. Each test cube group in the test cube groups comprises a main test cube and background test cubes. A main test cube, supplied by a tester or a decompressor, may be shifted into the scan chains. A background test cube may be shifted into background chains and be inserted into the main test cube in the scan chains based on control signals.

Abstract: An apparatus comprising a test circuit and a protocol circuit. The test circuit may be configured to generate a plurality of control signals in response to one or more read data signals. The protocol circuit may be configured to generate a plurality of interface signals in response to the plurality of control signals. The protocol engine suspends a refresh operation during a normal operation of the apparatus.

Abstract: A Voltage regulator includes a first input terminal configured to receive an input supply voltage, includes a second input terminal configured to receive a regulated output supply voltage as a function of the input supply voltage or to receive a test supply voltage and comprises a power transistor including an input terminal configured to receive the input supply voltage and including an output terminal configured to generate the regulated output supply voltage.

Abstract: In a client-server game system, or in accordance with a computer-readable program stored on a non-transitory computer-readable medium, a client participates in a game with other clients by performing an in-game simulation. Based on results of the in-game simulation, the client sends error-checking data to a server. The server analyzes the error-checking data to determine whether a simulation error has been caused by at least one of the clients. Upon determining that the simulation error has been caused, the server causes a reference simulation to be performed. Based on the results of the reference simulation, the server identifies the client(s) that caused the simulation error. The server then sends a patch to the client(s) that caused the simulation error. The client applies the patch to correct and reset the in-game simulation.

Abstract: This disclosure relates to network data communication. Some embodiments include initiating a network connection between an original source and an ultimate destination, transmitting a block of data from the original source to the ultimate destination on the network, requesting retransmission of lost blocks from the ultimate destination to the source and retransmitting the lost blocks from source to the ultimate destination. These embodiments further include measuring round-trip time of a retransmit request, the round-trip time measured from a time of transmission of a retransmit request from the ultimate destination to a time of reception at the ultimate destination after retransmission from the original source and setting the round-trip time as a minimum retransmission request time for the network connection, wherein the round-trip time includes latencies of the network connection and in data processes at the original source and at the ultimate destination.

Abstract: A method and apparatus are described including receiving content, applying fountain codes to symbols of the content to generate fountain encoded symbols at one of a transport layer and an application layer and transmitting the generated fountain encode symbols via a mobile network that uses a multi-link delivery system. Also described are a method and apparatus including receiving data packets of fountain encoded symbols via a mobile network that uses a multi-link delivery system, decoding the received data packets of fountain encoded symbols to content data, attempting to recover any corrupted content data and determining if the content data was recovered.

Abstract: A method generating program data to be stored in a nonvolatile memory device comprises randomizing the program data, and processing the randomized program data to reduce a frequency of at least one data state among the randomized program data.

Abstract: Methods and apparatus for tail termination are provided that include a decoder that includes a processor configured to a forward state metric and a backward state metric wherein each iteration of an initial state of the backward state metric is fetched from a memory and is pre-computed without feedback from a decoding iteration. Each decoding iteration is substantially identical, and the backward state metric that is pre-computed is used for a subsequent iteration. The decoder may include a turbo decoder or a radix-4 decoder.

Abstract: Method and system encodes a signal according to a code rate that includes a ratio of uncoded bits to coded bits. An outer encoder encodes the signal into code words. An interleaver converts the code words into a byte sequence for wireless transmission. An inner encoder executes a convolutional code to generate an encoded signal. The encoded signal is transmitted over a plurality of subcarriers associated with a wide bandwidth channel having a spectral efficiency associated with the code rate. The outer encoder includes a Reed-Solomon encoder having a rate that increases the code rate of uncoded bits to coded bits.

Abstract: A method includes receiving a representation of a set of single error detection (SED) parity bits and a representation of data. The data includes an error correction coding (ECC) codeword including information bits and ECC parity bits. Each SED parity bit of the set of SED parity bits indicates a parity value for a corresponding portion of the data. The method includes, in response to determining that a particular portion of the representation of the data includes a single erasure bit, selectively modifying a bit value of the single erasure bit based on the representation of the SED parity bit that corresponds to the particular portion and generating an updated representation of the ECC codeword when the bit value of the single erasure bit corresponds to the ECC codeword and has been modified. The method may include initiating an ECC decode operation of the updated representation of the ECC codeword.

Abstract: A memory device includes but is not limited to a non-volatile memory array and control logic integrated with and distributed over the non-volatile memory array. The control logic can be operable to maintain a plurality of copies of data in the non-volatile memory array and detect errors by comparison of selected ones of the plurality of copies.

Abstract: The present disclosure includes systems and techniques relating to decoding signals produced within a storage device. A described technique includes retrieving a first codeword from a storage medium, decoding the first codeword, performing a retry process when the decoding was not successful, and retrieving one or more second codewords from the storage medium during the retry process to at least maintain a drive throughput. The retry process can include identifying one or more data chunks within the first codeword having potential defects, generating an erasure mask based on the one or more data chunks, applying, based on a window, one or more erasures within one or more different regions of the first codeword based on one or more corresponding regions of the erasure mask to produce one or more versions of the first codeword, and decoding the one or more versions of the first codeword.

Abstract: Exemplary embodiments of the present invention disclose a method and system for monitoring a first Error Correcting Code (ECC) device for failure and replacing the first ECC device with a second ECC device if the first ECC device begins to fail or fails. In a step, an exemplary embodiment detects that a specified number of correctable errors is exceeded. In another step, an exemplary embodiment detects the occurrence of an uncorrectable error. In another step, an exemplary embodiment performs a loopback test on an ECC device if a specified number of correctable errors is exceeded or if an uncorrectable error occurs. In another step, an exemplary embodiment replaces an ECC device that fails the loopback test with an ECC device that passes a loopback test.

Abstract: A method for detecting a defect in a portion of a storage device is disclosed. Reference data and data read from the portion are compared to determine a number of error bits and a number of error symbols. An error ratio is computed, wherein the error ratio comprises a ratio of the number of error bits to the number of error symbols. A defect is detected based on whether the error ratio exceeds a threshold. In some embodiments, the reference data and the read data are compared to determine an error vector, wherein a bit in the error vector with a value one indicates a bit error in the read data. For each of a plurality of windows of the error vector, a corresponding number of error bits is determined. A defect is detected based on whether any of the numbers of error bits exceeds a threshold.