Abstract: The present invention discloses a LED backlight module, which comprises a backplane; a side-type backlight source, which comprises a backlight source substrate and multiple light emitting diodes provided on the backlight light source substrate; a reflector, which is provided on the backplane; multiple light guides provided on the reflector in parallel, each light guide being provided with at least one light-incident surface and one light-emitting surface, the light-incident surface of the light guide being opposite to the LED; diffusers provided on the multiple light guides, which are opposite to the light-emitting surface of the light guide; and an optical film set, which is located above the diffuser. The embodiment of the present invention further discloses the corresponding liquid crystal display. According to the embodiment of the present invention, it can save the amount of LEDs, which is beneficial for the narrow frame of the liquid crystal display panel.

Abstract: A light source module includes a plurality of light emitting units, and each of the light emitting units includes a reflection plate, a light extraction plate, a sidewall structure, a light source, and a diffusion plate. The light extraction plate has a plurality of first holes, and the light extraction plate and the reflection plate are opposite to each other. The sidewall structure having a plurality of second holes is located between the reflection plate and the light extraction plate, and the reflection plate, the light extraction plate, and the sidewall structure together constitute a first light guiding cavity. The light source is located in the first light guiding cavity and adjoins the sidewall structure. The diffusion plate is located above the light extraction plate, and a second light guiding cavity is formed between the light extraction plate and the diffusion plate.

Abstract: A light guide plate disclosed in the present disclosure includes a board body, a prism component and at least one optical microstructure. The prism component is disposed on at least one surface of the board body. The at least one optical microstructure is disposed on a top end of the prism component. The optical microstructure includes a first light guiding unit and at least two second light guiding units. A first angle is formed between two inclined surfaces of the first light guiding unit, and the first angle is substantially between 45˜60 degrees. The second light guiding units are symmetrically disposed on opposite sides of the first light guiding unit. A second angle is formed between an inclined surface and a bottom surface of each second light guiding unit, and the second angle is substantially between 10˜60 degrees.

Abstract: A backlight assembly includes a light source, a circuit board on which the light source is disposed, a light guide plate having a light incident surface and a light emitting surface, a bottom case accommodating the light guide plate, a fixing frame coupled to the bottom case and fixing the circuit board, and a heat dissipation apparatus disposed between the light source and the light guide plate and including a light-transmitting unit that transmits light.

Abstract: A light emitting device mounting structural body includes a wiring substrate having wirings disposed on a base member and a light emitting device having a resin molded body mounted on the wiring substrate. The wiring substrate has a recess in its periphery. The resin molded body has a lower surface and a side surface. The lower surface has an arrangement portion and a projecting portion, the arrangement portion has an outer lead electrically connected to the wiring portion disposed beneath the arrangement portion, and the projecting portion is projected further downward relative to the arrangement portion. The side surface has an opening with a light emitting element mounted thereon, the opening is expanded in the projecting portion, and at least a portion of the opening is housed in the recess of the wiring substrate.

Abstract: Disclosed is a light guide plate including a base sheet and a first light transmissive adhesive layer disposed on a surface of the base sheet. The first light transmissive adhesive layer together with the base sheet define a light entrance portion. The thickness of the first light transmissive adhesive layer becomes gradually smaller from the light entrance portion toward a center portion of the base sheet. A backlight assembly includes the light guide plate.

Abstract: A method of controlling a phase-shift full-bridge (PSFB) converter in a light load operation is provided to switch control modes of the PSFB converter by detecting magnetizing current of a transformer thereof. The method includes following steps: First, the PSFB converter is operated in an extended PSFB control mode when the magnetizing current is larger. Afterward, the PSFB converter is operated in a modified PSFB control mode when the magnetizing current is gradually reduced and electric charges transported by the residual magnetizing current near to or less than a half of the DC input voltage. Finally, the optimal degree of soft switching of the PSFB converter is implemented when the PSFB converter is operated at the modified PSFB control mode. Accordingly, it is to improve overall efficiency, reduce switching losses, and achieve electromagnetic compatibility.

Abstract: An apparatus and system for arc fault protection during power conversion. In one embodiment, the apparatus comprises a power converter comprising a first and a second pair of DC input terminals, coupled in series, for coupling to a first and a second DC source, respectively; an input bridge; an inductor; a first and a second arc fault protection capacitor, wherein (i) the series combination of the first and the second pair of DC input terminals is coupled across the input bridge, (ii) a first terminal of the inductor is coupled between the first and the second pair of DC input terminals, (iii) a second terminal of the inductor is coupled between switches on one leg of the input bridge, and (iv) the first and the second arc fault protection capacitors are coupled across the first and the second pair of DC input terminals, respectively.

Abstract: A method and an apparatus for transferring electric power to an electrical load (105); the method comprising steps of: converting a direct electric current into an electric tension wave, applying the electric tension wave in inlet to at least a couple of electric capacitors (125, 130); supplying the electrical load (105) with the electric tension in outlet from the capacitors (125, 130).

Abstract: A second control circuit is configured to switch a pulse signal to a level which turns off a second switching transistor when a coil current that flows through a primary winding reaches a predetermined threshold current. The second control circuit is configured to start a switching operation when a power supply for an electronic device is turned on, to set the threshold current to a first value when an intermediate voltage is higher than a predetermined level, and to set the threshold current to a second value that is lower than the first value when the intermediate voltage is lower than a predetermined level. A first control circuit is configured to start a switching operation upon receiving an instruction from a microcontroller to start operating.

Abstract: A controller for use with a power converter and method of operating the same. In one embodiment, the controller includes a gate drive terminal configured to provide a gate drive signal to enable conductivity of a power switch during a first portion of a switching interval and to disable conductivity of the power switch during a second portion of the switching interval. The controller also includes a current sense terminal configured to receive a power switch signal indicative of a current in the power switch during the first portion of the switching interval, and receive a control signal to operate the power converter or provide a status signal indicative of an operating condition of the power converter during the second portion of the switching interval.

Abstract: A power source apparatus comprises: a transformer that insulates a primary system and a secondary system and uses primary/secondary windings to transform an input voltage into an output voltage; a switching control device that is disposed in the primary system to drive the primary winding, and an output monitor device that is disposed in the secondary system to monitor the output voltage. The transformer includes a first auxiliary winding disposed in the primary system and a second auxiliary winding disposed in the secondary system. The output monitor device drives the second auxiliary winding to generate an induced voltage in the first auxiliary winding when the output voltage becomes smaller than a predetermined threshold voltage. The switching control device temporarily stops driving of the first winding upon detecting a light load state and resumes the driving of the first winding upon detecting the induced voltage in the first auxiliary winding.

Abstract: A controller for adjusting an output voltage of a power converter includes a gate control signal generation circuit, a feedback signal detection module, and a reference voltage generation module. The gate control signal generation circuit generates a gate control signal to a power switch of a primary side of the power converter according to a reference voltage and a plurality of signals corresponding to the primary side and a secondary side of the power converter. The feedback signal detection module generates a logic signal according to a combination corresponding to the plurality of signals. The reference voltage generation module generates the reference voltage to the gate control signal generation circuit according to the logic signal. The power switch adjusts the output voltage of the secondary side of the power converter according to the gate control signal.

Abstract: Power converter modules and parallel conversion systems are presented in which the modules are provided in a rollable enclosure having AC and DC electrical connections, and an interior including a switching circuit with switching devices individually connected between a corresponding AC node and a corresponding DC node for operation as either a rectifier or an inverter and an internal filter circuit with inductors individually connected between a corresponding AC node of the switching circuit and a corresponding AC electrical connection, with a built-in blower or fan to cool the filter circuit during operation.

Abstract: A converter circuit with short-circuit protection can include a plurality of phase legs having a series connection of normally-on switches, between voltage rails of a DC voltage link, a DC link capacitor, and AC voltage connection points between the normally-on switches. A phase-to-phase short-circuit protection circuit includes a parallel connection of a resistive component and a controllable switch. The phase-to-phase short-circuit protection circuit including a first terminal connected to an AC voltage connection point and a second terminal forms an input or an output of the converter circuit; and a controllable switch is connected in series with the DC link capacitor. Upon lack of control of the normally-on switches the controllable switch of the at least one phase-to-phase short-circuit protection circuit and the controllable switch of the phase leg short-circuit protection circuit are adapted to be controlled to a non-conductive state.

Abstract: A power converter including at least one switching device is presented. The power converter is configured to convert an input parameter to an output parameter by periodically activating and deactivating the switching device. The switching device includes: (i) a chamber including an ionizable gas; (ii) a cathode and an anode defining a discharge gap disposed in the chamber; (iii) a magnet assembly configured to generate a first magnetic field such that a plasma is maintained in the discharge gap; and (iv) an electromagnet configured to generate, in response to a deactivation signal, a second magnetic field such that at least a portion of the plasma in the discharge gap is disrupted to deactivate the switching device. A method of power conversion and a switching device are also presented.

Abstract: A plurality of memory mats classified into groups selected by bits of a row address, a main word driver for selecting a main word line based on bits of the row address, an FX driver for selecting a word driver selecting line based on bits regardless of the bits of the row address, and a plurality of sub-word drivers selected by the main word line and the word driver selecting line to drive the corresponding sub-word line are arranged.

Abstract: A nonvolatile semiconductor memory device comprises: a memory cell array including first interconnections, second interconnections intersecting the first interconnections, and memory cells having a variable resistance element and being provided at respective intersections of the first interconnections and the second interconnections, the memory cell array being divided into bays including a predetermined number of the memory cells; and a control circuit configured to execute a first write step and a second write step executed after the first write step at a data writing operation, wherein the control circuit is configured to change over the number of simultaneously selected bits and/or the number of simultaneously selected bays depending upon whether a write step is the first write step or the second write step.

Abstract: A semiconductor memory device includes a first memory region, a second memory region suitable for storing the same data as the first memory region, and a ray detection circuit suitable for detecting an incident ray to the first memory region, wherein a data stored in the second memory region is copied into the first memory region when the incident ray is detected.

Abstract: A ferroelectric memory device includes a memory array including a plurality of ferroelectric memory cells, a code generating circuit configured to multiply write data and a parity generator matrix to generate check bits, thereby producing a Hamming code having information bits and the check bits arranged therein, the information bits being the write data, and a driver circuit configured to write the Hamming code to the memory array, wherein the parity generator matrix has a plurality of rows, and a number of “1”s in each of the rows is an even number.

Abstract: A resistive memory apparatus includes a memory unit including a resistive memory cell array, a voltage generation unit suitable for receiving a radio frequency (RF) signal, and converting the RF signal into a direct current (DC) voltage, and a control unit suitable for controlling a refresh operation to be performed on the resistive memory cell array, wherein the boosted DC voltage is used as an operation voltage for the refresh operation.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a control circuit configured to cause data to be stored in a memory cell by setting the memory cell to be included in one of resistance value distributions. The control circuit is configured to set a first resistance value distribution and a second resistance value distribution, the second resistance value distribution having a resistance value larger than that of the first resistance value distribution, and to set a second width to be larger than a first width, the second width being a width between a second upper limit value of the second resistance value distribution and a second lower limit value of the second resistance value distribution, and the first width being a width between a first upper limit value of the first resistance value distribution and a first lower limit value of the first resistance value distribution.

Abstract: Memory cells and operation methods thereof are provided. A memory device includes a number of memory cells. Each of the memory cells includes a first transistor, a switch and a capacitor. The first transistor has a drain connected to a corresponding bit-line. The switch has a first terminal connected to a source of the first transistor and a second terminal coupled to a reference voltage. The capacitor has a first plate and a second plate, and the first plate of the capacitor is electrically connected to a gate of the first transistor. The second plate of the capacitor is connected to a corresponding word line. The switch is turned off when the memory cell is not selected to perform a write operation or a read operation.

Abstract: A method and apparatus for operating a memory device with wider difference in array and periphery voltage is presented. The memory device includes a bit line, a complementary bit line, a memory cell, a first pre-charge circuit, and a second pre-charge circuit. The memory cell, the first pre-charge circuit, and the second pre-charge circuit are coupled between the bit line and the complementary bit line. The first pre-charge circuit is configured to pre-charge the bit line and the complementary bit line to a first voltage level. The second pre-charge circuit is configured to pre-charge the bit line and the complementary bit line to a second voltage level that is different than the first voltage level. In some examples, two precharge circuits are configured to operate such that memory access is ensured to be static noise margin safe even under wider difference between two voltage levels.

Abstract: The disclosed invention provides an SRAM capable of stably generating a PUF-ID without having to be powered on/off under control. The SRAM including a plurality of write ports is provided with a plurality of word lines, each transferring write data from each of the write ports to one memory cell. Timing to negate at least two word lines (AWL, BWL), respectively coupled to two write ports, among the word lines is synchronized. Because synchronicity of writing different values to the memory cell is assured, by using a large number of such memory cells, it is possible to stably generate a PUF-ID without power on/off control.

Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.

Abstract: An apparatus includes a semiconductor transistor structure. The semiconductor transistor structure includes dielectric material, a channel region, a gate, a source overlap region, and a drain overlap region. The source overlap region is biasable to cause a first voltage difference between the source overlap region and the gate to exceed a breakdown voltage of the dielectric material. The drain overlap region is biasable to cause a second voltage difference between the drain overlap region and the gate to exceed the breakdown voltage. The apparatus includes a well line coupled to a body of the semiconductor transistor. The apparatus includes circuitry configured to apply a voltage to the well line to prevent a breakdown condition between the channel region and the gate.

Abstract: A method that may be performed in a data storage device includes selecting a writing order for data to be written to a set of word lines of a block of a non-volatile memory. The data is organized in pages that are ordered according to a logical page address order. The writing order is selected from at least a first order or a second order that is distinct from the first order. Stored data in the non-volatile memory written according to the first order has logical page addresses that decrease with increasing values of word line physical addresses. The method also includes writing the data to the set of word lines according to the selected writing order and storing a flag value that indicates the selected writing order.

Abstract: A method includes, in a memory device, receiving a command that specifies a peak power consumption that is not to be exceeded by the memory device. A memory of the memory device is configured in accordance with the peak power consumption specified in the command. A data storage operation in the configured memory is performed, while complying with the specified peak power consumption.

Abstract: According to one embodiment, a non-volatile semiconductor memory device includes a memory cell array and a row decoder. The memory cell array has NAND strings as a physical block, and word lines respectively connected to memory cells included in the NAND strings. The row decoder includes latch circuits and a drive circuit. When a failure exists within a corresponding first logical block, the latch circuits store a flag indicating the failure. The drive circuit inhibits driving of the word lines belonging to the first logical block when the flag is stored in the latch circuit corresponding to the first logical block to which the selected word lines belong, and allows the driving of the word lines belonging to the physical block including the first logical block when the flag is not stored in the latch circuit corresponding to the first logical block to which the selected word lines belong.

Abstract: A three-dimensional integrated circuit non-volatile memory array includes a memory array with first and second NAND memory cell string stacks having opposite orientations, where each NAND memory cell string includes a plurality of transistors and a source line contact connected in series between a bit line and string extension region which extends from the source line contact and past a first self-aligned SSL gate electrode located on a peripheral end of the NAND memory cell string, and also includes a string select transistor formed with a second self-aligned SSL connected in series between the bit line and the plurality of transistors, where the first and second self-aligned SSL gate electrodes are shared between adjacent NAND memory cell strings having opposite orientations.

Abstract: A method transfers read data from a flash memory to a controller synchronously with respect to a data strobe signal during a read data transfer period. During an initial control period of the read data transfer period, the cycle of the data strobe signal is expanded such that a pulse width of the resulting cycle-controlled data strobe signal is greater than a pulse width of the data strobe signal.

Abstract: Memory devices and methods for operating a memory include filtering a histogram of sensed data of the memory, and adjusting a parameter used to sense the memory using the filtered histogram. Filtering can be accomplished by averaging or summing, and may include weighting the sums or averages.

Abstract: In an embodiment, a method of generating strobe signals includes generating a first strobe signal in a first mode by operating a multiplexer with a clock signal to select between a first input signal and a second input signal, the first input signal having a static first signal level and the second input signal corresponding to a control signal. In a second mode, the method includes generating a second strobe signal by operating the multiplexer with the clock signal to select between the first input signal and the second input signal, the first input signal corresponding to the control signal inverted and delayed and the second input signal having a static second signal level.

Abstract: A non-volatile memory apparatus and a data verification method thereof are provided. The non-volatile memory apparatus includes a plurality of memory cells, a page buffer, a write circuit, a sense amplifier, and a sense and compare circuit. The page buffer stores a plurality of buffered data and programs the plurality of memory cells according to the plurality of buffered data. The write circuit receives a program data or a rewrite-in data and writes the program data or the rewrite-in data to the page buffer. The sense amplifier senses data read from the memory cells for generating a read-out data. The sense and compare circuit reads the buffered data, and compares the read-out data and a compared buffered data to generate a rewrite-in data. The sense and compare circuit determines the rewrite-in data to be the buffered data or an inhibiting data according to the compared result.

Abstract: A sensing amplifier comprising a clamp circuit is provided. The clamp circuit is coupled between a first node and a second node. The clamp circuit comprises a first P-type transistor having a first terminal, a second terminal and a control terminal receiving a first bias signal, the first terminal and the second terminal of the first P-type transistor are coupled to the first node and the second node, respectively, and a sensing current from the memory cell flows into the second node via the first node during a sensing time period.

Abstract: A method includes determining a plurality of first current values of a first current to be sunk by a tracking cell of a tracking circuit in response to a plurality of first voltage values of a first voltage applied to the tracking cell. Each first current value of the plurality of first current values thereby corresponds to a first voltage value of the plurality of first voltage values. A second current value of a second current is determined. The second current value corresponds to a second voltage value of a second voltage of a memory cell of a plurality of memory cells. A third voltage value is selected based on the second current value, a first current value of the plurality of first current values, and a first voltage value corresponding to the first current value.

Abstract: A semiconductor chip includes an internal voltage generation circuit suitable for generating an internal voltage having a predetermined level, a target internal circuit suitable for performing a predetermined operation using the internal voltage, and a control circuit suitable for checking operating speed of the target internal circuit based on an operation result signal generated from the target internal circuit, and generating the control signal based on the checked operating speed, wherein a voltage level of the internal voltage for target internal circuit is controlled based on the control signal.

Abstract: Disclosed herein is a semiconductor memory device using a pre-fetch method and a semiconductor system including the same. The semiconductor memory device may include a memory bank having an odd-numbered array region suitable for inputting/outputting data through N first local lines in response to an odd-numbered column address, and an even-numbered array region suitable for inputting/outputting data through N second local lines in response to an even-numbered column address, N being a positive integer, a column address generation unit suitable for consecutively generating the odd-numbered column address and the even-numbered column address whose generation sequence is controlled depending on whether an external column address has an even-numbered value or an odd-numbered value, and N global lines coupled in common to the N first local lines and the N second local lines, suitable for inputting/outputting data.

Abstract: A semiconductor device includes a pipe latch suitable for sequentially latching data in response to a pipe input control signal and sequentially outputting data in response to a pipe output control signal, a pipe latch control unit suitable for generating the pipe input/output control signals in response to a command signal and latency information, and resetting the pipe input/output control signals in response to a pipe reset signal, and an error detection unit suitable for receiving the pipe input control signal and the pipe output control signal, detecting a latency error, and generating the pipe reset signal

Abstract: A semiconductor memory device may include: a memory cell array; a first address controller configured to receive a first command and a first address and generate a first control signal in response to the first command; and a second address controller configured to receive a second address and a second command inputted at the same time as the first command, and generate a second control signal in response to the second command.

Abstract: Apparatuses and methods are disclosed herein, including those, performed by a memory die, that operate to detect that a command on a bus connected to the memory die is addressed to another memory die responsive to a chip select signal, and to change the impedance of an on-die termination circuit of the memory die responsive to the detecting.

Abstract: A semiconductor memory device includes: a memory cell array region having a plurality of normal cell lines and a plurality of repair cell lines; a plurality of normal cell line selection units suitable for selecting the plurality of normal cell lines, respectively, in response to a local address; a plurality of repair cell line selection units suitable for selecting the plurality of repair cell lines, respectively, in place of normal cell line selection units corresponding to fail information of the local address; a fuse driving unit comprising a fuse array in which the fail information is programmed, suitable for disabling the normal cell line selection units corresponding to the fail information, and enabling normal cell line selection units unrelated to the fail information; and an address determination unit suitable for controlling the plurality of repair cell line selection units based on the fail information.

Abstract: An operation method of a memory device includes entering a repair mode, changing an input path of setting data from a set path to a repair path in response to the entering of the repair mode, receiving the setting data together with a setting command, ending the repair mode after the receiving is repeated a set number of times, changing the input path of the setting data from the repair path to the set path in response to the ending of the repair mode, and programming a repair address for a defective memory cell of the memory device to a nonvolatile memory using the setting data.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a cell array including first to Nth word lines, where the N is an integer equal to or larger than 2, first to Nth memory sets respectively corresponding to the first to Nth word lines, and an activation number updating block configured to, when a Kth word line of the word lines is activated, initialize a value stored in a Kth memory set and increase values stored in memory sets corresponding to adjacent word lines of the Kth word line, among the memory sets, wherein the K is an integer equal to or larger than 1 and equal to or smaller than N.

Abstract: A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.

Abstract: Disclosed are methods, circuits, apparatuses and systems for providing power to a dynamic load such as a non-volatile memory array. According to embodiments, a voltage source may be adapted to generate and output a supply current at substantially a target voltage through a regulating transistor whose channel is in series between an output terminal of said charge pump and an input terminal of said NVM array. A discharge circuit branch coupled to an output terminal of the regulating transistor may be adapted to drain away current from the regulating transistor output terminal when a voltage at the regulating transistor output terminal exceeds a first defined threshold voltage. A bulk regulating circuit branch coupled to a bulk of the regulating transistor may be adapted to reduce a bulk-voltage of the regulating transistor when a voltage at the regulating transistor output terminal exceeds a defined threshold voltage.

Abstract: The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information for each phase in a combination of phases of a command, and authorizing execution of at least one of the phases in the combination based, at least partially, on the power consumption information determined for the at least one of the phases.

Abstract: Embodiments relate to systems and methods for simplified addressing of a memory device whose total memory capacity is extendible by an additional memory capacity or a factor to a total extended memory capacity, the method comprising dividing the additional memory capacity into a set of binary memory fractions of the total memory capacity such that a sum of all binary memory fractions equals the additional memory capacity, and addressing each one of the binary memory fractions by a binary based addressing scheme.

Abstract: A semiconductor integrated circuit includes a plurality of semiconductor chips. Each of the plurality of semiconductor chips includes a chip selection unit suitable for generating an internal chip selection signal in response to one or more selective chip selection signals and transferring the selective chip selection signals to an adjacent semiconductor chip of the plurality of semiconductor chips, a selective setting unit suitable for generating a selective internal signal, selectively activated in each semiconductor chip, in response to the internal chip selection signal and an external setting signal, and a common setting unit suitable for generating a common internal signal, activated in common in the plurality of semiconductor chips, in response to the setting signal and an external common chip selection signal.