Abstract: A light-emitting element includes a reflective electrode, a light-transmitting electrode disposed opposite the reflective electrode, a light-emitting layer emitting blue light disposed between the reflective electrode and the light-transmitting electrode, and a functional layer disposed between the reflective electrode and the light-emitting layer. The optical thickness of the functional layer is no less than 428.9 nm and no more than 449.3 nm.

Abstract: A light-emitting device is provided that aims not to affect a service life and characteristics of light emission and includes two electrodes formed on the upper surface of a substrate with a gap at a central portion of the upper surface of the substrate between the two electrodes, a first light-emitting diode element mounted on the first electrode, and a second light-emitting diode element mounted on the second electrode. The first light-emitting diode element includes a pair of element electrodes on an upper surface of the first light-emitting diode element and the second light-emitting diode element includes a pair of element electrodes on an upper surface of the second light-emitting diode element. The first light-emitting diode element is connected by a wire to the first electrode and/or the second electrode. The second light-emitting diode element is connected by a wire to the first electrode and/or the second electrode.

Abstract: A display panel includes: a substrate on which a plurality of feed terminals corresponding to a plurality of pixels are provided; a plurality of pixel electrodes corresponding to the respective pixels; a common electrode common to the pixels; and a plurality of light-emitting layers corresponding to the respective pixels and provided between the pixel electrodes and the common electrode. In plan view, within each of the pixels, the light-emitting layer and the feed terminal do not overlap, feed terminals of each column of pixels are provided in a column, and the common electrode is electrically connected to conductive layers, the conductive layers each having a shape of a line that overlaps a corresponding one of the columns of feed terminals. Accordingly, the display panel achieves a high aperture ratio even with the conductive layers formed therein.

Abstract: A light-emitting device includes a substrate (4), a light-emitting element (10) mounted on the substrate (4), a first resin (12) disposed to cover an upper portion of the light-emitting element (10), a second resin (14) disposed to cover a lower portion of the light-emitting element (10), a first phosphor (18) contained in the first resin (12), and a second phosphor (20) contained in the second resin (14). The first phosphor (18) converts light emitted directly from the light-emitting element (10) into a first phosphor-converted light having a wavelength longer than that of the light emitted directly from the light-emitting element (10) and emits the first phosphor-converted light, and the second phosphor (20) converts the light emitted directly from the light-emitting element (10) into a second phosphor-converted light having a wavelength longer than that of the first phosphor-converted light and emits the second phosphor-converted light.

Abstract: An organic light-emitting device including a substrate, an anode layer on the substrate, the anode layer including WOxNy (2.2?x?2.6 and 0.22?y?0.26), an emission structure layer on the anode layer, and a cathode layer on the emission structure layer.

Abstract: A semiconductor light-emitting device according to the present invention is a semiconductor light-emitting device 10 including a solid-state light-emitting element 11 and a wavelength converter 12 that converts primary light emitted by the solid-state light-emitting element 11 into light having a longer wavelength, wherein the wavelength converter 12 includes a wavelength converting layer 12a made from a translucent inorganic formed body containing phosphors, and a binder layer 12b; the wavelength converter 12 is disposed on a main light extraction surface 11a of the solid-state light-emitting element 11; and the binder layer 12b is disposed along an emission direction of light emitted from the main light extraction surface 11a.

Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a first electrode, a second electrode, a first insulating film, a first interconnection layer, a second interconnection layer, a first metal pillar, a second metal pillar, a second insulating film and a fluorescent material layer. The first electrode is provided in an emitting region of the semiconductor layer. The first electrode, the first insulating film, the first interconnection layer, the second interconnection layer, and the second insulating layer are configured to transmit radiated light of the light emitting layer.

Abstract: In one aspect, there is an apparatus that comprises a plurality of light emitting chips that each have active areas that have elongated aspect ratios. This chips are mounted in a generally rectangular package. The chips are each arranged around a periphery of the package so that each narrow side of each chip abuts either a sidewall forming the periphery of the package or a long side another of the chips. Some of the chips receive a biasing voltage through one or more other of the chips.

Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, an inorganic insulating film, a p-side interconnection portion, an n-side interconnection portion, and an organic insulating film. The organic insulating film is provided on the inorganic insulating film, at least on a portion between the p-side interconnection portion and the n-side interconnection portion. An end portion of the p-side interconnection portion on the n-side interconnection portion side and an end portion of the n-side interconnection portion on the p-side interconnection portion side override the organic insulating film.

Abstract: A luminophore composition comprising amorphous aluminoborate powders is disclosed. The composition is obtainable by preparing an aluminoborate resin by a wet chemical route based on precursors solutions substantially free from monovalent and divalent cations; drying the resin to obtain a solid; grinding the solid to obtain a powder; pyrolyzing the powder at a pyrolysis temperature lower than the crystallization temperature of the composition; and calcinating the powder so pyrolyzed at a calcination temperature lower than the crystallization temperature of the composition. Furthermore, a process for the preparation of said composition is disclosed. The composition is particularly suitable for use in solid-state lighting, and for example for converting UV light into warm white visible light.

Abstract: An n-type layer, an active layer, and a p-type layer are grown on a growth substrate. Portions of the p-type layer and active layer are etched away to expose the n-type layer, and an n-electrode is formed over the exposed portions of the n-type layer. A first dielectric layer is formed over the n-electrodes. A transparent conductor layer is formed over the p-type layer and the first dielectric layer. A p-electrode is formed over the transparent conductor layer. A transparent bonding layer is deposited over the transparent conductor layer and the p-electrode. A transparent support substrate is bonded to the p-type layer via the bonding layer. The growth substrate is then removed to expose the n-type layer, and the layers are etched to expose the n and p electrodes for connection to a power source. A reflector layer is formed on the bottom surface of the substrate.

Abstract: Provided is a highly-reliable organic electroluminescence element in which loss of light due to surface plasmons generated on a metal surface is suppressed, the efficiency of light extraction to outside the element, and short circuits are unlikely to occur. The organic electroluminescence element includes a metal layer (1), on a surface of which a nanosize uneven structure is provided by a nanoparticle arrangement structure (6) in which nanoparticles (6a) are arranged in a planar fashion, and an organic layer (3) disposed on the uneven surface of the metal layer (1) and constituted by a plurality of layers including a light-emitting layer (31). Each interface between the plurality of layers of the organic layer (3) is flatter than the uneven surface of the metal layer (1).

Abstract: A light emitting diode (LED) carrier assembly includes an LED die mounted on a silicon submount, a middle layer that is thermally conductive and electrically isolating disposed below the silicon submount, and a printed circuit board (PCB) disposed below the middle layer. The middle layer is bonded with the silicon submount and the PCB.

Abstract: An exemplary embodiment of the present invention provides an organic light emitting diode, comprising a substrate, a first electrode, an organic material layer, and a second electrode, wherein a trench comprising a concave part and a convex part is provided on the substrate, the first electrode is provided on the substrate on which the trench is formed by being deposited, and an auxiliary electrode is provided on the first electrode. The organic light emitting diode according to the exemplary embodiment of the present invention may increase surface areas of the first electrode and the auxiliary electrode formed on the substrate, thereby implementing a low resistance electrode. In addition, since a line width of the electrode is not increased, it is possible to prevent a decrease of an opening ratio of the organic light emitting diode.

Abstract: An organic light emitting diode (OLED) lighting apparatus includes a light emitting panel including an organic light emitting diode, a housing for housing the light emitting panel, a cover coupled to the housing and covering a front-side edge of the light emitting panel, a plurality of pins disposed between the housing and the light emitting panel and supporting an edge of the light emitting panel, and at least one contact bar disposed between the plurality of pins and a back-side edge of the light emitting panel.

Abstract: A housing for an optoelectronic component including a main housing body formed by a first plastics material, and which has a recess, and a coating formed by a second plastics material, and which, at least in a region of the recess, connects at least in places to the main housing body and is in direct contact with the main housing body, wherein the first plastics material is different from the second plastics material, and the first plastics material and the second plastics material differ from one another with regard to at least one of the following material properties: temperature resistance with regard to discoloration, temperature resistance with regard to deformation, temperature resistance with regard to destruction, and resistance to electromagnetic radiation.

Abstract: An optoelectronic device comprising a substrate; a first window layer on the substrate, having a first sheet resistance, a first thickness, and a first impurity concentration; a second window layer having a second sheet resistance, a second thickness, and a second impurity concentration; and a semiconductor system between the first window layer and the second window layer; wherein the second window layer comprises a semiconductor material different from the semiconductor system, and the second sheet resistance is greater than the first sheet resistance.

Abstract: A light-emitting diode (LED), including a first semiconductor layer defining several light-emitting regions and non-light-emitting regions; an active layer and a second semiconductor layer sequentially formed over the first semiconductor layer in the light-emitting regions; a transparent conductive layer formed over the second semiconductor layer; a Bragg reflector structure formed over the transparent conductive layer and including several first via holes; a metal layer formed over the Bragg reflector structure and connected to the transparent conductive layer through the first via holes; a passivation layer covering the metal layer and including several second via holes; several third via holes exposing the first semiconductor layer in the non-light-emitting regions; several first electrodes filling the third via holes and connected to the first semiconductor layer; and several second electrodes filling the second via holes and connected to the metal layer.

Abstract: Disclosed are a light emitting device. The light emitting device includes a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer, an electrode connected to the first conductive semiconductor layer. First to third conductive layers are disposed under the second conductive semiconductor layer. A protective layer is disposed outward further than the first conductive layer. A support member is disposed under the third conductive layer. A buffer layer is disposed between protective layer and the third conductive layer. The protective layer includes a first opening, a first portion, and a second portion. The second portion of the protective layer and the buffer layer is overlapped with the third conductive layer and is disposed outwardly further than a lateral surface of the first conductive layer.

Abstract: An organic light-emitting display and methods of manufacturing the same are disclosed. In one aspect, an organic light-emitting apparatus includes a substrate, a display unit on the substrate, a step compensation layer formed on the display unit and supplementing a step on a surface of the display unit, a first intermediate layer formed on the step compensation layer, and an encapsulation layer formed on the first intermediate layer and sealing the display unit.

Abstract: A nitride semiconductor light emitting device includes: an uneven substrate having an uneven structure in which recesses are formed; a first nitride semiconductor layer of a first conductive type formed on the uneven structure; a first light emitting layer formed on the first nitride semiconductor layer; and a second nitride semiconductor layer of a second conductive type formed on the light emitting layer, wherein each protrusion has a bottom made of a material or composition having a thermal expansion coefficient larger than the thermal expansion coefficient of the material or composition of the first nitride semiconductor layer.

Abstract: Disclosed are a nitride semiconductor light-emitting element and a method for manufacturing the same. The nitride semiconductor light-emitting element according to the present invention comprises: a current blocking part disposed between a substrate and an n-type nitride layer; an activation layer disposed on the top surface of the n-type nitride layer; and a p-type nitride layer disposed on the top surface of the activation layer, wherein the current blocking part is an AlxGa(1-x)N layer, and the Al content x times layer thickness (?m) is in the range of 0.01-0.06. Accordingly, the nitride semiconductor light-emitting element can increase the luminous efficiency by having a current blocking part which prevents current leakage from occurring.

Abstract: Between a back surface electrode and an electrode, a first thyristor is formed of fifth and seventh semiconductor regions, a substrate region, first and second semiconductor regions and a third semiconductor region, and a second thyristor is formed of the second and first semiconductor regions, the substrate region, the seventh and fifth semiconductor regions and a sixth semiconductor region. Depths from the surface of the semiconductor substrate to bottom surfaces of the third and fourth semiconductor regions are 20 ?m or more. The second semiconductor region with a high impurity concentration is enclosed by the first semiconductor region with a low impurity concentration, and a difference between a depth from the surface of the semiconductor substrate to the bottom of the second semiconductor region and a depth from the surface of the semiconductor substrate to the bottom of the first semiconductor region is less than 10 ?m.

Abstract: Apparatus and methods for monolithic data conversion interface protection are provided herein. In certain implementations, a protection device includes a first silicon controlled rectifier (SCR) and a first diode for providing protection between a signal node and a power high supply node, a second SCR and a second diode for providing protection between the signal node and a power low supply node, and a third SCR and a third diode for providing protection between the power high supply node and the power low supply node. The SCR and diode structures are integrated in a common circuit layout, such that certain wells and active regions are shared between structures. Configuring the protection device in this manner enables in-suit input/output interface protection using a single cell. The protection device is suitable for monolithic data conversion interface protection in sub 3V operation.

Abstract: Protection circuit architectures with integrated supply clamps and methods of forming the same are provided herein. In certain implementation, an integrated circuit interface protection device includes a first diode protection structure and a first thyristor protection structure electrically connected in parallel between a signal pin a power high supply. Additionally, the protection device includes a second diode protection structure and a second thyristor protection structure electrically connected in parallel between the signal pin and a power low supply. Furthermore, the protection device includes a third diode protection structure and a third thyristor protection structure electrically connected in parallel between the power high supply and the power low supply.

Abstract: Device structures and design structures that include a silicon controlled rectifier, as well as fabrication methods for such device structures. A well is formed in the device layer of a silicon-on-insulator substrate. A silicon controlled rectifier is formed that includes an anode in the well. A deep trench capacitor is formed that includes a plate coupled with the well. The plate of the deep trench capacitor extends from the device layer through a buried insulator layer of the silicon-on-insulator substrate and into a handle wafer of the silicon-on-insulator substrate.

Abstract: A semiconductor device includes a link portion that connects a second heat sink to a third heat sink via a solder. The solder is arranged on a connecting surface of a base portion of the link portion, which is orthogonal to a plate thickness direction of the base portion, in a direction perpendicular to first and second surfaces. The link portion has a rib that protrudes from the base portion in a direction orthogonal to the first and second surfaces, and a thickness of a portion where the rib is provided is equal to or less than the thickness of the corresponding heat sink. The rib is provided across an entire length of a first region that is sealed by a sealing resin body and that is between the second and the third heat sinks, in an alignment direction of a first heat sink and the third heat sink.

Abstract: Semiconductor trilayer structures that are doped and strained are provided. Also provided are mechanically flexible transistors, including radiofrequency transistors, incorporating the trilayer structures and methods for fabricating the trilayer structures and transistors. The trilayer structures comprise a first layer of single-crystalline semiconductor material, a second layer of single-crystalline semiconductor material and a third layer of single-crystalline semiconductor material. In the structures, the second layer is in contact with and sandwiched between the first and third layers and the first layer is selectively doped to provide one or more doped regions in the layer.

Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material having the first lattice constant; a middle portion between the lower portion and upper portion, wherein the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; and a pair of notches extending into opposite sides of the middle portion; and an isolation structure surrounding the fin structure, wherein a top surface of the isolation structure is higher than a top surface of the pair of notches.

Abstract: A semiconductor device includes a nitride semiconductor stacked structure including a carrier transit layer and a carrier supply layer; a p-type nitride semiconductor layer provided over the nitride semiconductor stacked structure and including an active region and an inactive region; an n-type nitride semiconductor layer provided on the inactive region in the p-type nitride semiconductor layer; and a gate electrode provided over the active region in the p-type nitride semiconductor layer.

Abstract: A method of forming an integrated circuit structure includes providing a substrate, and epitaxially growing a first semiconductor layer over the substrate. The first semiconductor layer includes a first III-V compound semiconductor material formed of group III and group V elements. The method further includes forming a gate structure on the first semiconductor layer, and forming a gate spacer on at least one sidewall of the gate structure. After the step of forming the gate structure, a second semiconductor layer including a second III-V compound semiconductor material is epitaxially grown on the first semiconductor layer.

Abstract: A semiconductor device including a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first lattice dimension III-V semiconductor layer, and the second lattice dimension III-V semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension III-V semiconductor layer, wherein the channel portion of second lattice dimension III-V semiconductor layer has the compressive strain. A source region and a drain region are present on opposing sides of the channel portion of the second lattice dimension III-V semiconductor layer.

Abstract: According to one embodiment a nitride semiconductor device includes a first, a second and a third semiconductor layer, a first and a second main electrode and a control electrode. The first layer made of a nitride semiconductor of a first conductivity type is provided on a substrate. The second layer made of a nitride semiconductor of a second conductivity type is provided on the first layer. The third layer made of a nitride semiconductor is provided on the second layer. The first electrode is electrically connected with the second layer. The second electrode is provided at a distance from the first electrode and electrically connected with the second layer. The control electrode is provided within a first trench via an insulating film. The first trench is disposed between the first and the second main electrodes, penetrates the third and the second layers, and reaches the first layer.

Abstract: A non-inverted P-channel III-nitride field effect transistor with hole carriers in the channel comprising a nitrogen-polar III-Nitride first material, a barrier material layer, a two-dimensional hole gas in the barrier layer, and wherein the nitrogen-polar III-Nitride material comprises one or more III-Nitride epitaxial material layers grown in such a manner that when GaN is epitaxially grown the top surface of the epitaxial layer is nitrogen-polar. A method of making a P-channel III-nitride field effect transistor with hole carriers in the channel comprising selecting a face or offcut orientation of a substrate so that the nitrogen-polar (001) face is the dominant face, growing a nucleation layer, growing a GaN epitaxial layer, doping the epitaxial layer, growing a barrier layer, etching the GaN, forming contacts, performing device isolation, defining a gate opening, depositing and defining gate metal, making a contact window, depositing and defining a thick metal.

Abstract: An object of the present invention is to provide a GaN-based light emitting diode element having a great emission efficiency and suitable for an excitation light source for a white LED. The GaN-based light emitting diode element includes an n-type conductive m-plane GaN substrate, a light emitting diode structure which is formed of a GaN-based semiconductor, on a front face of the m-plane GaN substrate, and an n-side ohmic electrode formed on a rear face of the m-plane GaN substrate, wherein a forward voltage is 4.0 V or less when a forward current applied to the light emitting diode element is 20 mA.

Abstract: A stacking structure in which a stacked body (21) including a first conductive layer (13), a semiconductor layer (17), and a second conductive layer (18) and an interlayer insulating film (16) are alternately stacked in parallel to a substrate, a plurality of columnar electrodes (12) arranged so as to penetrated through the stacking structure in a stacking direction, a variable resistance layer (14) which is disposed between the columnar electrode (12) and the first conductive layer (13) and which has a resistance value that reversibly changes according to an application of an electric signal are included. The variable resistance layer (14) is formed by oxidizing part of the first conductive layer (13). The variable resistance layer (14) and an insulating film for electrically separating the semiconductor layer (17) and the second conductive layer (18) from the columnar electrode (12) are simultaneously formed in a single oxidation process.

Abstract: An integrated circuit with electrically programmable fuse circuitry coupled to a programming transistor is provided. The programming transistor may be a metal-oxide-semiconductor transistor that is separated from other circuitry in an integrated circuit substrate with shallow trench isolation. The electrically programmable fuse circuitry may be formed in a second layer above the integrated circuit substrate using a conductive material which may be tungsten-based. This second layer may further include interconnect wires made from the same conductive material. The electrically programmable fuse may be coupled to the programming transistor through vias and routing paths in a fourth layer above the integrated circuit substrate. The routing paths in the fourth layer may be made from a conductive material which may be different than the fuse conductive material used to form the programmable fuse circuitry.

Abstract: A memory cell is provided that includes a diode and a resistance-switching material layer coupled in series with the diode. The resistance-switching material layer has a thickness between 20 and 65 angstroms. Other aspects are also provided.

Abstract: A method manufactures a sensor device for sensing a gaseous substance and includes a thin film transistor, which includes a source electrode, a drain electrode and a gate electrode; and an element sensitive to the gaseous substance. In particular, the method includes: forming a first metallic layer on a substrate; defining and patterning the first metallic layer for realizing the gate electrode; depositing a dielectric layer above the gate electrode; depositing a second metallic layer above the layer of dielectric material, defining and patterning the second metallic layer for realizing the source electrode and the drain electrode, and forming the sensitive element by filling a channel region of the thin film transistor with an active layer sensitive to the gaseous substance.

Abstract: A micro-electro-mechanical system (MEMS), methods of forming the MEMS and design structures are provided. The method includes forming a coplanar waveguide (CPW) comprising a signal electrode and a pair of electrodes on a substrate. The method includes forming a first sacrificial material over the CPW, and a wiring layer over the first sacrificial material and above the CPW. The method includes forming a second sacrificial material layer over the wiring layer, and forming insulator material about the first sacrificial material and the second sacrificial material. The method includes forming at least one vent hole in the insulator material to expose portions of the second sacrificial material, and removing the first and second sacrificial material through the vent hole to form a cavity structure about the wiring layer and which exposes the signal line and pair of electrodes below the wiring layer. The vent hole is sealed with sealing material.

Abstract: A semiconductor device includes a trench transistor cell array in a silicon semiconductor body with a first main surface and a second main surface opposite to the first main surface. A main lateral face of the semiconductor body between the first main surface and the second main surface has a first length along a first lateral direction parallel to the first and second main surfaces. The first length is equal or greater than lengths of other lateral faces of the semiconductor body. The trench transistor cell array includes predominantly linear gate trench portions. At least 50% of the linear gate trench portions extend along a second lateral direction or perpendicular to the second lateral direction. An angle between the first and second lateral directions is in a range of 45°±15°.

Abstract: Radio frequency and microwave devices and methods of use are provided herein. According to some embodiments, the present technology may comprise an ohmic layer for use in a field effect transistor that includes a plurality of strips disposed on a substrate, the plurality of strips comprising alternating source strips and drain strips, with adjacent strips being spaced apart from one another to form a series of channels, a gate finger segment disposed in each of the series of channels, and a plurality of gate finger pads disposed in an alternating pattern around a periphery of the plurality of strips such that each gate finger segment is associated with two gate finger pads.

Abstract: A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region. The source includes a GaN-layer coupled to an InGaN layer. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.

Abstract: A method of forming a semiconductor device is provided that includes forming a first metal semiconductor alloy on a semiconductor containing surface, forming a dielectric layer over the first metal semiconductor alloy, forming an opening in the dielectric layer to provide an exposed surface the first metal semiconductor alloy, and forming a second metal semiconductor alloy on the exposed surface of the first metal semiconductor alloy. In another embodiment, the method includes forming a gate structure on a channel region of a semiconductor substrate, forming a dielectric layer over at least a source region and a drain region, forming an opening in the dielectric layer to provide an exposed surface the semiconductor substrate, forming a first metal semiconductor alloy on the exposed surface of the semiconductor substrate, and forming a second metal semiconductor alloy on the first metal semiconductor alloy.

Abstract: Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.

Abstract: An insulating layer is provided with a projecting structural body, and a channel formation region of an oxide semiconductor layer is provided in contact with the projecting structural body, whereby the channel formation region is extended in a three dimensional direction (a direction perpendicular to a substrate). Thus, it is possible to miniaturize a transistor and to extend an effective channel length of the transistor. Further, an upper end corner portion of the projecting structural body, where a top surface and a side surface of the projecting structural body intersect with each other, is curved, and the oxide semiconductor layer is formed to include a crystal having a c-axis perpendicular to the curved surface.

Abstract: A method for fabricating a semiconductor device is provided herein and includes the following steps. First, a first interlayer dielectric is formed on a substrate. Then, a gate electrode is formed on the substrate, wherein a periphery of the gate electrode is surrounded by the first interlayer dielectric. Afterwards, a patterned mask layer is formed on the gate electrode, wherein a bottom surface of the patterned mask layer is leveled with a top surface of the first interlayer dielectric. A second interlayer dielectric is then formed to cover a top surface and each side surface of the patterned mask layer. Finally, a self-aligned contact structure is formed in the first interlayer dielectric and the second interlayer dielectric.

Abstract: A semiconductor device includes at least two fin-shaped structures, a gate structure, at least two epitaxial structures and a silicon cap. The fin-shaped structures are disposed on a substrate and are covered by the gate structure. The epitaxial structures are disposed at one side of the gate structure and respectively directly contact each fin-shaped structure, wherein the epitaxial structures are spaced apart from each other. The silicon cap simultaneously surrounds the epitaxial structures.

Abstract: According to one embodiment, a solid-state image sensing device includes a semiconductor substrate having a first and second surface, an insulating film covering an element on the first surface, a pixel array including pixels configured to photoelectrically convert light applied on the side of the second surface, contact regions in the semiconductor substrate, one or more through-electrodes respectively provided in the contact regions, and first pads provided on the side of the second surface to correspond to the respective contact regions. The first pad extends in a first direction from the contact regions toward the pixel array.

Abstract: Disclosed herein is an apparatus that includes a ferrocapacitor having a sidewall. An etch stopping film is disposed along the sidewall of the ferrocapacitor, with a hydrogen barrier film disposed between the etch stopping film and the sidewall of the ferrocapacitor.