Abstract: A method for contacting MOS devices. First openings in a photosensitive material are formed over a substrate having a top dielectric in a first die area and a second opening over a gate stack in a second die area having the top dielectric, a hard mask, and a gate electrode. The top dielectric layer is etched to form a semiconductor contact while etching at least a portion the hard mask layer thickness over a gate contact area exposed by the second opening. An inter-layer dielectric (ILD) is deposited. A photosensitive material is patterned to generate a third opening in the photosensitive material over the semiconductor contact and a fourth opening inside the gate contact area. The ILD is etched through to reopen the semiconductor contact while etching through the ILD and residual hard mask if present to provide a gate contact to the gate electrode.

Abstract: A semiconductor nanowire is formed integrally with a wraparound semiconductor portion that contacts sidewalls of a conductive cap structure located at an upper portion of a deep trench and contacting an inner electrode of a deep trench capacitor. The semiconductor nanowire is suspended from above a buried insulator layer. A gate dielectric layer is formed on the surfaces of the patterned semiconductor material structure including the semiconductor nanowire and the wraparound semiconductor portion. A wraparound gate electrode portion is formed around a center portion of the semiconductor nanowire and gate spacers are formed. Physically exposed portions of the patterned semiconductor material structure are removed, and selective epitaxy and metallization are performed to connect a source-side end of the semiconductor nanowire to the conductive cap structure.

Abstract: One embodiment of a semiconductor device includes a fin on a first side of a semiconductor body. The semiconductor device further includes a body region of a second conductivity type in at least a part of the fin. The semiconductor device further includes a drain extension region of a first conductivity type, a source and a drain region of the first conductivity type, and a gate structure adjoining opposing walls of the fin. The body region and the drain extension region are arranged one after another between the source region and the drain region.

Abstract: In general, according to one embodiment, a nonvolatile semiconductor memory device includes a memory cell region and a peripheral region. The memory cell region includes first element isolation regions, first semiconductor regions, a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate electrode. The first element isolation regions separate a semiconductor layer and include a first insulating film. The first semiconductor regions are separated by the first element isolation regions. The peripheral region includes a second element isolation region a second insulating film. Each of the first element isolation regions includes a first and a second portion. A step is present between the first and the second portion. At least part of a side surface and a lower end of the second element isolation region are surrounded by the semiconductor layer.

Abstract: A nonvolatile memory device includes gate structures formed over a substrate, each gate structure including a tunnel insulating layer, a floating gate, an inter-gate dielectric layer, and a control gate that are sequentially stacked, a protective layer formed on sidewalls of the floating gate, and a second insulating layer covering the gate structures and having an air gap formed between the gate structures, wherein an adhesive strength between the second insulating layer and the protective layer is smaller than an adhesive strength between the second insulating layer and the gate structure.

Abstract: A semiconductor memory device includes a substrate including a cell region and a peripheral region, word lines on the substrate of the cell region, each of the word lines including a charge storing part and a control gate electrode sequentially stacked, and a peripheral gate pattern on the substrate of the peripheral region. Each of the control gate electrode and the peripheral gate pattern includes a high-carbon semiconductor pattern and a low-carbon semiconductor pattern, the low-carbon semiconductor pattern being on the high-carbon semiconductor pattern.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a silicon-containing substrate, a plurality of memory cells, and an insulating film. The substrate includes silicon. The plurality of memory cells is provided on the substrate with a spacing therebetween. The insulating film is provided on a sidewall of the memory cell. The insulating film includes a protrusion protruding toward an adjacent one of the memory cells above a void portion is provided between the memory cells.

Abstract: A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack. The gate stack may include a first dielectric layer over the channel region, a first diffusion barrier layer over the first dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second dielectric layer over the first electrically conductive layer, a second diffusion barrier layer over the second dielectric layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.

Abstract: A semiconductor device comprising four semiconductor pillars extending in a direction perpendicular to a substrate, a connection channel formed on the substrate and connected to one ends of the four semiconductor pillars, a source line connected to the other ends of first and second semiconductor pillars adjacent to each other among the four semiconductor pillars, a bit line connected to the other ends of third and fourth semiconductor pillars among the four semiconductor pillars, first to fourth stack structures, which are formed along the first to fourth semiconductor pillars, respectively, between the source and bit lines and the substrate, and each includes a pass word line, at least one word line and a select line which are stacked over the substrate, and a memory layer interposed between the word line and each of the first to fourth semiconductor pillars.

Abstract: An insulated gate field effect transistor configured to reduce the occurrence of a short-circuit fault, and a method of manufacturing the insulated gate field effect transistor are provided. A FET includes a semiconductor substrate, a gate insulator, a gate electrode, and a conductive member. The semiconductor substrate has an insulation groove that splits a channel region into a first channel region on a drain region side and a second channel region on a source region side. The conductive member is supported by a drain-side end face and a source-side end face of the insulation groove. When the temperature of the conductive member is equal to or higher than a predetermined temperature, the conductive member is cut.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type which is formed on a first main surface of the semiconductor substrate, a second well region of a second conductivity type which is formed to surround a cell region of the drift layer, and a source pad for electrically connecting the second well regions and a source region of the cell region through a first well contact hole provided to penetrate a gate insulating film on the second well region, a second well contact hole provided to penetrate a field insulating film on the second well region and a source contact hole.

Abstract: A transistor includes a semiconductor body; a body region of a first conductivity type formed in the semiconductor body; a gate electrode formed partially overlapping the body region and insulated from the semiconductor body by a gate dielectric layer; a source diffusion region of a second conductivity type formed in the body region on a first side of the gate electrode; a trench formed in the semiconductor body on a second side, opposite the first side, of the gate electrode, the trench being lined with a sidewall dielectric layer; and a doped sidewall region of the second conductivity type formed in the semiconductor body along the sidewall of the trench where the doped sidewall region forms a vertical drain current path for the transistor.

Abstract: An electronic device can include a semiconductor layer overlying a substrate and having a primary surface and a thickness, wherein a trench extends through at least approximately 50% of the thickness of semiconductor layer to a depth. The electronic device can further include a conductive structure within the trench, wherein the conductive structure extends at least approximately 50% of the depth of the trench. The electronic device can still further include a vertically-oriented doped region within the semiconductor layer adjacent to and electrically insulated from the conductive structure; and an insulating layer disposed between the vertically-oriented doped region and the conductive structure. A process of forming an electronic device can include patterning a semiconductor layer to define a trench extending through at least approximately 50% of the thickness of the semiconductor layer and forming a vertically-oriented doped region after patterning the semiconductor layer to define the trench.

Abstract: A trench-gate device with lateral RESURF pillars has an additional implant beneath the gate trench. The additional implant reduces the effective width of the semiconductor drift region between the RESURF pillars, and this provides additional gate shielding which improves the electrical characteristics of the device.

Abstract: A semiconductor device includes: a semiconductor substrate formed with an element region; a first conductive type first region formed in the element region and located on a surface side of the semiconductor substrate; a second conductive type second region located in a deeper position than the first region in the element region and contacting the first region; a first conductive type third region located in a deeper position than the second region in the element region, contacting the second region, and separated from the first region by the second region; and a gate disposed in a trench extending from the surface to reach the third region, and contacting a range of the second region via the insulation film.

Abstract: In one implementation, a power semiconductor device includes an active region and a termination region. A depletion trench finger extends from the active region and ends in the termination region. An arched depletion trench surrounds the depletion trench finger in the termination region, the arched depletion trench enables one or both of an increased breakdown voltage and a reduced on-resistance in the power semiconductor device.

Abstract: A MOS device with an isolated drain includes: a semiconductor substrate having a first conductivity type; a first well region embedded in a first portion of the semiconductor substrate, having a second conductivity type; a second well region disposed in a second portion of the semiconductor substrate, overlying the first well region and having the first conductivity type; a third well region disposed in a third portion of the semiconductor substrate, overlying the first well region having the second conductivity type; a fourth well region disposed in a fourth portion of the semiconductor substrate between the first and third well regions, having the first conductivity type; a gate stack formed over the semiconductor substrate; a source region disposed in a portion of the second well region, having the second conductivity type; and a drain region disposed in a portion of the fourth well region, having the second conductivity type.

Abstract: The present disclosure relates to an SRAM memory cell. The SRAM memory cell has a semiconductor substrate with an active area and a gate region positioned above the active area. A butted contact extends along a length (i.e., the larger dimension of the butted contact) from a position above the active area to a position above the gate region. The butted contact contains a plurality of distinct regions having different widths (i.e., the smaller dimensions of the butted contact), such that a region spanning the active area and gate region has width less than the regions in contact with the active area or gate region. By making the width of the region spanning the active area and gate region smaller than the regions in contact with the active area or gate, the etch rate is reduced at a junction of the gate region with the active area, thereby preventing etch back of the gate material and leakage current.

Abstract: A radiation hardened static memory cell, methods of manufacture and design structures are provided. The method includes forming one or more first gate stacks and second gate stacks on a substrate. The method further includes providing a shallow implant process for the one or more first gate stacks such that diffusion regions of the one or more first gate stacks are non-butted junction regions. The method further includes providing a deep implant process for the one or more second gates stack such that diffusions regions of the one or more second gate stacks are butted junction regions.

Abstract: A display device includes a first electrode, a second electrode, an organic light emitting layer, a first transistor, and a second transistor. The first transistor includes a first semiconductor layer, a first conductive unit, a second conductive unit, a first gate electrode, and a first gate insulating film. The second transistor includes a second semiconductor layer, a third conductive unit, a fourth conductive unit, a second gate electrode, and a second gate insulating film. An amount of hydrogen included in the first gate insulating film is larger than an amount of hydrogen included in the second gate insulating film.

Abstract: Among other things, a semiconductor device comprising an aligned gate and a method for forming the semiconductor device are provided. The semiconductor device comprises a gate formed according to a multi-gate structure, such as a gate-all-around structure. A first gate portion of the gate is formed above a first channel of the semiconductor device. A second gate portion of the gate is formed below the first channel, and is aligned with the first gate portion. In an example of forming the gate, a cavity is etched within a semiconductor layer formed above a substrate. A dielectric layer is formed around at least some of the cavity to define a region of the cavity within which the second gate portion is to be formed in a self-aligned manner with the first gate portion. In this way, the semiconductor device comprises a first gate portion aligned with a second gate portion.

Abstract: Provided is a semiconductor device having high ESD tolerance. A first via (16) is used for electrically connecting a pad (22) to a drain of an NMOS transistor of an ESD protective circuit. The first vias (16) are formed under the pad (22) only on one side of a rectangular ring-shaped intermediate metal film (17) and on another side thereof opposed to the one side. In other words, all the first vias (16) for establishing an electrical connection to the drains are present substantially directly under the pad (22). Consequently, a surge current caused by ESD and applied to the pad (22) is more likely to flow uniformly among all the drains. Then, respective channels of the NMOS transistor of the ESD protective circuit are more likely to uniformly operate, and hence the ESD tolerance of the semiconductor device is increased.

Abstract: Provided is a semiconductor device having high ESD tolerance. A first via (16) is used for electrically connecting a pad to a drain of an NMOS transistor of an ESD protection circuit. The first via (16) is arranged directly above the drain and present substantially directly under the pad. Consequently, a surge current caused by ESD and applied to the pad is more likely to flow uniformly among all the drains. Then, respective channels of the NMOS transistor of the ESD protection circuit are more likely to uniformly operate, and hence the ESD tolerance of the semiconductor device increases.

Abstract: A high-voltage MEMS system compatible with low-voltage semiconductor process technology is disclosed. The system comprises a MEMS device coupled to a high-voltage bias generator employing an extended-voltage isolation residing in a semiconductor technology substrate. The system avoids the use of high-voltage transistors so that special high-voltage processing steps are not required of the semiconductor technology, thereby reducing process cost and complexity. MEMS testing capability is addressed with a self-test circuit allowing modulation of the bias voltage and current so that a need for external high-voltage connections and associated electro-static discharge protection circuitry are also avoided.

Abstract: A bipolar transistor includes a substrate having a semiconductor surface, a first trench enclosure and a second trench enclosure outside the first trench enclosure both at least lined with a dielectric extending downward from the semiconductor surface to a trench depth, where the first trench enclosure defines an inner enclosed area. A base and an emitter formed in the base are within the inner enclosed area. A buried layer is below the trench depth including under the base. A sinker diffusion includes a first portion between the first and second trench enclosures extending from a topside of the semiconductor surface to the buried layer and a second portion within the inner enclosed area, wherein the second portion does not extend to the topside of the semiconductor surface.

Abstract: A semiconductor device fabrication process includes forming insulating mandrels over replacement metal gates on a semiconductor substrate with first gates having sources and drains and at least one second gate being isolated from the first gates. Mandrel spacers are formed around each insulating mandrel. The mandrels and mandrel spacers include the first insulating material. A second insulating layer of the second insulating material is formed over the transistor. One or more first trenches are formed to the sources and drains of the first gates by removing the second insulating material between the insulating mandrels. A second trench is formed to the second gate by removing portions of the first and second insulating materials above the second gate. The first trenches and the second trench are filled with conductive material to form first contacts to the sources and drains of the first gates and a second contact to the second gate.

Abstract: A semiconductor device includes a first transistor positioned in and above a first semiconductor region, the first semiconductor region having a first upper surface and including a first semiconductor material. The semiconductor device further includes first raised drain and source portions positioned on the first upper surface of the first semiconductor region, the first drain and source portions including a second semiconductor material having a different material composition from the first semiconductor material. Additionally, the semiconductor device includes a second transistor positioned in and above a second semiconductor region, the second semiconductor region including the first semiconductor material. Finally, the semiconductor device also includes strain-inducing regions embedded in the second semiconductor region, the embedded strain-inducing regions including the second semiconductor material.

Abstract: A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves forming a shallow-trench-isolation oxide (STI) isolating the n-type device from the p-type device. The method further involves adjusting the shallow-trench-isolation oxide corresponding to at least one of the n-type device and the p-type device such that a thickness of the shallow-trench-isolation oxide adjacent to the n-type device is different from a thickness of the shallow-trench-isolation oxide adjacent to the p-type device, and forming a strain layer over the semiconductor substrate.

Abstract: A complementary metal oxide semiconductor structure including a scaled 0 and a scaled pFET which do not exhibit an increased threshold voltage and reduced mobility during operation is provided. The method includes forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. The pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack can also be plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion contains up to 15 atomic % N2 and an nFET threshold voltage adjusted species, while the plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion contains up to 15 atomic % N2 and a pFET threshold voltage adjusted species.

Abstract: An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates.

Abstract: In a semiconductor substrate of a semiconductor device, a drift layer, a body layer, an emitter layer, and a trench gate electrode are formed. When the semiconductor substrate is viewed in a plane manner, the semiconductor substrate is divided into a first region covered with a heat dissipation member, and a second region not covered with the heat dissipation member. A density of trench gate electrodes in the first region is equal to a density of trench gate electrodes in the second region. A value obtained by dividing an effective carrier amount of channel parts formed in the first region by an area of the first region is larger than a value obtained by dividing an effective carrier amount of channel parts formed in the second region by an area of the second region.

Abstract: A semiconductor device includes a plurality of semiconductor chips in a stack structure and a through-silicon via suitable for passing through the chips and transfer a signal from or to one or more of the chips. Each of the chips includes a buffering block disposed in path of the through-silicon via, and suitable for buffering the signal, an internal circuit, and a delay compensation block suitable for applying delay corresponding to the buffering blocks of the chips to the signal, wherein the delay compensation blocks of the chips compensates for delay difference of the signal transferred to and from the internal circuit of the chip, due to operations of the buffering block, based on stack information for distinguishing the chips.

Abstract: A dual port SRAM has two data storage nodes, a true data and complementary data. A first pull down transistor has an active area that forms the drain region of the first transistor and the true data storage node that is physically isolated from all other transistor active areas of the memory cell. A second pull down transistor has an active area that forms the drain region of a second transistor that is the complementary data node that is physically isolated from all other transistor active areas of the memory cell.

Abstract: A Fin Field-Effect Transistor (FinFET) includes a semiconductor layer over a substrate, wherein the semiconductor layer forms a channel of the FinFET. A first silicon germanium oxide layer is over the substrate, wherein the first silicon germanium oxide layer has a first germanium percentage. A second silicon germanium oxide layer is over the first silicon germanium oxide layer. The second silicon germanium oxide layer has a second germanium percentage greater than the first germanium percentage. A gate dielectric is on sidewalls and a top surface of the semiconductor layer. A gate electrode is over the gate dielectric.

Abstract: A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×1019 atoms/cm3, or alternatively, less than one-quarter the dopant concentration of the source and the drain.

Abstract: A method to prevent movable structures within a MEMS device, and more specifically, in recesses having one or more dimension in the micrometer range or smaller (i.e., smaller than about 10 microns) from being inadvertently bonded to non-moving structures during a bonding process. The method includes surface preparation of silicon both structurally and chemically to aid in preventing moving structures from bonding to adjacent surfaces during bonding, including during high force, high temperature fusion bonding.

Abstract: A MEMS device, a method of making a MEMS device and a system of a MEMS device are shown. In one embodiment, a MEMS device includes a first polymer layer, a MEMS substrate disposed on the first polymer layer and a MEMS structure supported by the MEMS substrate. The MEMS device further includes a first opening disposed in the MEMS substrate and a second opening disposed in the first polymer layer.

Abstract: This document refers to apparatus and methods for a device layer of a microelectromechanical system (MEMS) sensor having vias with reduced shunt capacitance. In an example, a device layer can include a substrate having a pair of trenches separated in a horizontal direction by a portion of the substrate, wherein each trench of the pair of trenches includes first and second vertical layers including dielectric, the first and second vertical layers separated by a third vertical layer including polysilicon.

Abstract: In a sensor module for accommodating a pressure sensor chip and for installation into a sensor housing, a module wall is connected monolithically to the module bottom and surrounds the pressure sensor chip. Multiple connecting elements which are conducted through the module wall to the outside run straight at least in the entire outside area. Furthermore, the connecting elements are exposed on their top and bottom sides for affixing and electrically connecting at least one electrical component and for electrically integrating the sensor module into the sensor housing. In this way, a two-sided use of a sensor module having an identical external geometry and identical connectors is possible.

Abstract: A nonvolatile magnetic memory device using a magnetic tunneling junction (MTJ) uses as a data storage unit an MTJ including a pinned magnetic layer, a nonmagnetic insulating layer, and a free magnetic layer which are sequentially stacked. The free magnetic layer includes at least one soft magnetic amorphous alloy layer in which zirconium (Zr) is added to a soft magnetic material formed of cobalt (Co) or a Co-based alloy.

Abstract: This invention comprises a method to make small MTJ element using hybrid etching and oxygen plasma immersion ion implantation. The method has no removal of the magnetic free layer (or memory layer) and hence prevents any possible physical damage near the free layer edges. After photolithography patterning, alternative Ta, Ru, Ta etchings are performed before it stops on an MgO intermediate layer above the free layer. Then an oxygen plasma immersion ion implantation is performed to completely oxidize the exposed portion of the free layer, leaving the hard mask covered portion unchanged which define the lateral width of the MTJ element.

Abstract: A motion sensing device for sensing infrared rays includes a substrate; an optical module, including a first spacer layer, coupled to the substrate; a first glass layer, formed on the first spacer layer; a second spacer layer, formed on the first glass layer; a second glass layer, formed on the second spacer layer; a third spacer layer, formed on the second glass layer; a first lens, bonding on a first side of the second glass layer; and a second layer, bonding on a second side relative to the first side of the second glass layer; and a coating layer, covered on the optical layer for shielding the infrared rays, wherein the coating layer does not cover the first lens.

Abstract: A stand-alone device comprising a silicon wafer having its front surface including a first layer of a first conductivity type and a second layer of a second conductivity type forming a photovoltaic cell; first vias crossing the wafer from the rear surface of the first layer and second vias crossing the wafer from the rear surface of the second layer; metallization levels on the rear surface of the wafer, the external level of these metallization levels defining contact pads; an antenna formed in one of the metallization levels; and one or several chips assembled on said pads; the metallization levels being shaped to provide selected interconnects between the different elements of the device.

Abstract: Disclosed herein is a solid-state imaging element including: a transfer section configured to transfer charge generated simultaneously by a photoelectric conversion section in all pixels to a memory section and have a metal gate; and a light-shielding section formed by filling a metal into a groove portion formed by digging an interlayer insulating film around the transfer section.

Abstract: A photodetector disclosed herein comprises an avalanche transistor having a reference junction structure in which temperature characteristics of a current amplification factor are about the same as those of an avalanche photodiode and which is reverse-biased, and a current injection junction structure which injects a reference current to the reference junction structure and which is forward-biased. Voltages to be applied to the avalanche photodiode and the reference junction structure are controlled so that the amplification factor of the reference current amplified in the reference junction structure is retained at a predetermined value, whereby the temperature characteristics of the photodetector utilizing an avalanche effect can be stabilized.

Abstract: An APD is provided with the semi-insulating substrate, a first mesa having a first laminate constitution in which a p-type electrode layer, a p-type light absorbing layer, a light absorbing layer with a low impurity concentration, a band gap inclined layer, a p-type electric field control layer, an avalanche multiplier layer, an n-type electric field control layer, and an electron transit layer with a low impurity concentration are stacked in this order on a surface of the semi-insulating substrate, a second mesa having an outer circumference provided inside an outer circumference of the first mesa as viewed from the laminating direction and having a second laminate constitution in which an n-type electrode buffer layer and an n-type electrode layer are stacked in this order on a surface on the electron transit layer side, and a depletion control region that is provided in layers on the second mesa side relative to the p-type electric field control layer, formed in an encircling portion provided inside an out

Abstract: There is provided a solid-state image pickup element including a pixel array part in which a plurality of pixels are arranged on a silicon substrate in arrays, and a drive part driving the pixel. The pixel includes a photoelectric conversion part formed near a second face of the silicon substrate opposite to a first face on which a wiring layer is laminated, for generating a charge corresponding to incident light, an overflow part formed in contact with the second face and fixed to a predetermined voltage, and a potential barrier part formed to be connected with the photoelectric conversion part and the overflow part, for serving as a barrier against a charge overflowed from the photoelectric conversion part on the overflow part.

Abstract: To provide a thermal electromagnetic wave detection element, a method for producing a thermal electromagnetic wave detection element, a thermal electromagnetic wave detection device, and an electrical apparatus, which are highly reliable and make it possible to prevent damage or deformation in the vicinity of the corner parts of a void, a thermal electromagnetic wave detection element includes: a semiconductor substrate; a support member provided on the semiconductor substrate; a detection unit that is provided on the support member and is able to extract from a pair of electrodes an electrical signal corresponding to a received amount of electromagnetic waves; and a pair of electrically conductive vias that perforate through the semiconductor substrate and are electrically connected to the pair of electrodes, a void that opens on the support member side being provided between the pair of vias of the semiconductor substrate.

Abstract: An IR sensor includes a suspended micro-platform having a support layer and a device layer disposed thereon. IR absorbers are disposed in or on the device layer. IR radiation received by the IR absorbers heats an on-platform junction of each of a plurality of series-connected thermoelectric devices operating in a Seebeck mode, the devices producing a voltage indicative of the received IR. Other thermoelectric devices are used to cool the platform, and a pressure sensing arrangement is used to detect loss of vacuum or pressure leaks.

Abstract: In a Schottky diode having an n+-type substrate, an n-type epitaxial layer, at least two p-doped trenches introduced into the n-type epitaxial layer, mesa regions between adjacent trenches, a metal layer functioning as a cathode electrode, and another metal layer functioning as an anode electrode, the thickness of the epitaxial layer is more than four times the depth of the trenches.