Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

Abstract: Methods for removing residual polymers formed during etching of a boron-doped amorphous carbon layer are provided herein. In some embodiments, a method of etching a feature in a substrate includes: exposing a boron doped amorphous carbon layer disposed on the substrate to a first plasma through a patterned mask layer to etch a feature into the boron doped amorphous carbon layer, wherein the first plasma is formed from a first process gas that reacts with the boron doped amorphous carbon layer to form residual polymers proximate a bottom of the feature; and exposing the residual polymers to a second plasma through the patterned mask layer to etch the residual polymers proximate the bottom of the feature, wherein the second plasma is formed from a second process gas comprising nitrogen (N2), oxygen (O2), hydrogen (H2), and methane (CH4).

Abstract: In a manufacturing method of a semiconductor device according to an embodiment, a processing target film is formed above a substrate. A buffer layer in a polycrystalline state or an amorphous state is formed on the processing target film. A mask material is formed on the buffer layer. The processing target film is etched using the mask material as a mask. The buffer layer has an etching rate smaller than the processing target film.

Abstract: According to an embodiment, a manufacturing method of a semiconductor device includes: forming a first film on a processing target by using a first material; forming a second film on the first film by using a second material; selectively removing the second and first films to provide an opening pierced in the second and first films; selectively forming a metal film on an inner surface of the opening in the first film; and processing the processing target by using the metal film as a mask.

Abstract: In a manufacturing method for a semiconductor device according to an embodiment, a first heat treatment to anneal or oxidize an SiC layer in an atmosphere where a gas including carbon (C) exists is applied. Further, the semiconductor device according to the embodiment includes: an SiC substrate having a first surface and a second surface; a first conductivity type SiC layer disposed on the first surface side of the SiC substrate, and including a low level density region having Z1/2 level density of 1×1011 cm?3 or less measured by deep level transient spectroscopy (DLTS); a second conductivity type SiC region disposed on a surface of the SiC layer; a first electrode disposed on the SiC region; and a second electrode disposed on the second surface side of the SiC substrate.

Abstract: A method for introducing impurity into a semiconductor substrate includes bringing a solution containing a compound of an impurity element into contact with a primary surface of a semiconductor substrate; and irradiating the primary surface of the semiconductor substrate with a laser beam through the solution to raise a temperature of the primary surface of the semiconductor substrate at a position irradiated by the laser beam so as to dope the impurity element into the semiconductor substrate. The laser beam irradiation is performed such that the raised temperature does not return to room temperature until a prescribed dose of the impurity element is caused to be doped into the semiconductor substrate.

Abstract: A method may include providing a substrate having a surface that defines a substrate plane and a substrate feature that extends from the substrate plane; directing an ion beam comprising angled ions to the substrate at a non-zero angle with respect to a perpendicular to the substrate plane, wherein a first portion of the substrate feature is exposed to the ion beam and wherein a second portion of the substrate feature is not exposed to the ion beam; directing molecules of a molecular species to the substrate wherein the molecules of the molecular species cover the substrate feature; and providing a second species to react with the molecular species, wherein selective growth of a layer comprising the molecular species and the second species takes place such that a first thickness of the layer grown on the first portion is different from a second thickness grown on the second portion.

Abstract: The present invention generally provides semiconductor substrates having submicron-sized surface features generated by irradiating the surface with ultra short laser pulses. In one aspect, a method of processing a semiconductor substrate is disclosed that includes placing at least a portion of a surface of the substrate in contact with a fluid, and exposing that surface portion to one or more femtosecond pulses so as to modify the topography of that portion. The modification can include, e.g., generating a plurality of submicron-sized spikes in an upper layer of the surface.

Abstract: A manufacturing method of a graphene modulated high-k oxide and metal gate Ge-based MOS device, which comprises the following steps: 1) introducing a graphene thin film on a Ge-based substrate; 2) conducting fluorination treatment to the graphene thin film to form fluorinated graphene; 3) activating the surface of the fluorinated graphene by adopting ozone plasmas, and then forming a high-k gate dielectric on the surface of the fluorinated graphene through an atomic layer deposition technology; and 4) forming a metal electrode on the surface of the high-k gate dielectric. Since the present invention utilizes the graphene as a passivation layer to inhibit the formation of unstable oxide GeOx on the surface of the Ge-based substrate and to stop mutual diffusion between the gate dielectric and the Ge-based substrate, the interface property between Ge and the high-k gate dielectric layer is improved.

Abstract: A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; depositing a first cap layer comprising an oxide over the dielectric stack; forming a second cap layer comprising a nitride over the first cap layer; patterning the first and second cap layers and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to form a blocking oxide over the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.

Abstract: The invention relates to a method for forming a uniform silicide film using a crystalline semiconductor film in which orientation of crystal planes is controlled, and a method for manufacturing a thin film transistor with less variation in electric characteristics, which is formed over an insulating substrate using the silicide film. A semiconductor film over which a cap film is formed is irradiated with a laser to be crystallized under the predetermined condition, so that a crystalline semiconductor film including large grain crystals in which orientation of crystal planes is controlled in one direction is formed. The crystalline semiconductor film is used for silicide, whereby a uniform silicide film can be formed.

Abstract: A dry etching method according to the present invention is for etching a silicon layer as a processing target in a processing room, characterized by supplying an iodine heptafluoride-containing etching gas from a gas supply source at a supply pressure of 66 kPa to 0.5 MPa, evacuating the processing room to an internal pressure lower than the supply pressure of the etching gas and, while maintaining the etching gas at the supply pressure, introducing the etching gas into the evacuated processing room so as to etch the silicon layer by the etching gas. It is possible by this dry etching method to etch the silicon upon adiabatic expansion of the etching gas under mild pressure conditions, with no fear of equipment load and equipment cost increase, and achieve good uniformity of in-plane etching amount distribution.

Abstract: The disclosure relates to a process for treating a structure, the structure comprising, from its back side to its front side, a carrier substrate, an insulating layer and a useful layer, the useful layer having a free surface, the structure being placed in an atmosphere containing chemical species, the chemical species being capable of reacting chemically with the useful layer. This treatment process is noteworthy in that the useful layer is heated by a pulsed laser beam, the beam sweeping the free surface, the wavelength of the beam differing by, at most, plus or minus 15 nm from a central wavelength, the central wavelength being chosen so that the sensitivity of the reflectivity of the structure relative to the insulating layer is zero.

Abstract: A method includes forming a first material layer on a substrate and performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer. The method further includes performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer, wherein the second layout a cut pattern for the first layout. The method further includes forming spacer features on sidewalls of both the first and second pluralities of trenches, wherein the spacer features have a thickness and the cut pattern corresponds to a first trench of the second plurality whose width is less than twice the thickness of the spacer features. The method further includes removing the first material layer; forming a second material layer on the substrate and within openings defined by the spacer features; and removing the spacer features.

Abstract: A method of forming patterns of a semiconductor device includes forming a material film on a substrate, forming a hard mask on the material film, forming a first mold mask pattern and a second mold mask pattern on the hard mask, forming a pair of first spacers to cover opposite sidewalls of the first mold mask pattern, and a pair of second spacers to cover opposite sidewalls of the second mold mask pattern, forming a first gap and a second gap to expose the hard mask by removing the first mold mask pattern and the second mold mask pattern, the first gap being formed between the pair of first spacers and the second gap being formed between the pair of second spacers, forming a mask pattern on the hard mask to cover the first gap and expose the second gap, forming an auxiliary pattern to cover the second gap, removing the mask pattern; and forming a hard mask pattern by patterning the hard mask using the first spacers, the second spacers and the auxiliary pattern as a mask.

Abstract: A thin film transistor substrate includes a gate electrode arranged on a substrate, a gate insulation layer arranged on the gate electrode, an active pattern arranged on the gate insulation layer, a source electrode overlapping a first end portion of the active pattern, and a drain electrode overlapping a second and opposite end portion of the active pattern. A fluorocarbon-like material is arranged on one or more of surfaces of at least one of the active pattern, the source electrode and the drain electrode, and on a photoresist pattern used in the formation process of the thin film substrate. The fluorocarbon-like material on the photoresist pattern serves to maintain a shape and size of the photoresist pattern during subsequent patterning processes.

Abstract: A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches.

Abstract: A polishing device includes a housing, a flexible base coupled to the housing, and a contact region disposed on a first side of the flexible base, wherein the flexible base expands and contracts based on pressure contained within the housing and a second side of the flexible base to form a contact area on the first side that is less than a surface area of the flexible base.

Abstract: A method includes performing a chemical-mechanical planarization (CMP) on an article, providing a polishing fluid capable of transferring charges to the article, and detecting a current generated in response to the charges transferred to the article. An apparatus that is capable of performing the method and a system that includes the apparatus are also disclosed.

Abstract: A method of manufacturing a semiconductor structure, by depositing a dielectric layer is a dummy gate, or an existing gate structure, prior to the formation of gate spacers. Following the formation of spacers, and in some embodiments replacing a dummy gate with a final gate structure, oxygen is introduced to a gate dielectric through a diffusion process, using the deposited dielectric layer as a diffusion pathway.

Abstract: A method for etching a silicon oxide film on a target substrate where an etching area is partitioned by pattern layers and stopping the etching before a base layer of the silicon oxide layer is etched is disclosed. The method includes heating the target substrate in a vacuum atmosphere and intermittently supplying, as an etching gas, at least one of a processing gas containing a hydrogen fluoride gas and an ammonia gas in a pre-mixed state and a processing gas containing a compound of nitrogen, hydrogen and fluorine to the target substrate from a gas supply unit multiple times.

Abstract: There is provided a method for reducing the nonuniformity of forward voltage Vf of an N-type semiconductor wafer in which density of impurities included in an N-layer is nonuniformly distributed in a plane view of the semiconductor wafer. The method reduces the nonuniformity of forward voltage, by irradiating charged particles to the N-type semiconductor wafer, and generating defects in the N-layer to reduce the nonuniformity of forward voltage. In one aspect of the method, charged particles are irradiated so that a reaching positon in a depth direction or an irradiation density may differ according to the density of impurities in the N-layer in the plane view of the semiconductor wafer.

Abstract: The present disclosure provides a method for upgrading materials, for example crystalline metallurgical silicon, to remove impurities using microwave processing to induce migration of impurities in the material to one or both of internal surfaces where they are trapped and neutralized or one or more external surfaces followed by trapping of the impurity by binding to gettering agents on the surface with subsequent removal of the impurity and gettering agent.

Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.

Abstract: A hardmask composition includes a first material including one of an aromatic ring-containing monomer and a polymer containing a repeating unit including an aromatic ring-containing monomer, a second material including at least one of a hexagonal boron nitride and a precursor thereof, a chalcogenide-based material and a precursor thereof, and a two-dimensional carbon nanostructure and a precursor thereof, the two-dimensional carbon nanostructure containing about 0.01 atom % to about 40 atom % of oxygen, and a solvent.

Abstract: In an example embodiment, an integrated circuit (IC) comprises a device die having a top-side surface and an under-side surface, the top-side surface having bond pads connected to active circuit elements, the under-side surface having a conductive surface. A first set of lead frame clips having upper portions and lower portions, are solder-anchored, on the upper portions, to a first set of bond pads; the lower portions are flush with the conductive surface. Wires are bonded to an additional set of bond pads opposite the first set of bond pads and to lower lead frame portions of a second set of lead frame clips opposite the first set of lead frame clips; the lower lead frame portions of the second set of lead frame clips are flush with the conductive surface. The device is encapsulated in a molding compound leaving exposed the conductive surface and underside surfaces of the first and second sets of the lead frame portions.

Abstract: A power field-effect transistor package is fabricated. A leadframe including a flat plate and a coplanar flat strip spaced from the plate is provided. The plate has a first thickness and the strip has a second thickness smaller than the first thickness. A field-effect power transistor chip having a third thickness is provided. A first and second contact pad on one chip side and a third contact pad on the opposite chip side are created. The first pad is attached to the plate and the second pad to the strip. Terminals are concurrently attached to the plate and the strip so that the terminals are coplanar with the third contact pad. The thickness difference between plate and strip and spaces between chip and terminals is filled with an encapsulation compound having a surface coplanar with the plate and the opposite surface coplanar with the third pad and terminals. The chip, leadframe and terminals are integrated into a package having a thickness equal to the sum of the first and third thicknesses.

Abstract: A wafer level packaging method entails providing electronic devices and providing a platform structure having cavities extending through the platform structure. The platform structure is mounted to a temporary support. One or more electronic devices are placed in the cavities with an active side of each electronic device facing the temporary support. The platform structure and the electronic devices are encapsulated in an encapsulation material to produce a panel assembly. Redistribution layers may be formed over the panel assembly, after which the panel assembly may be separated into a plurality of integrated electronic packages. The platform structure may be formed from a semiconductor material, and platform segments within each package provide a fan-out region for conductive interconnects, as well as provide a platform for a metallization layer and/or for forming through silicon vias.

Abstract: A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate.

Abstract: A substrate treating apparatus includes a rotating and holding unit that rotates a substrate, a first supply source that supplies first pure water having a first temperature, a second supply source that supplies second pure water having a second temperature higher than the first temperature, a treatment solution supply unit that supplies a treatment solution to a central section of an upper surface of the substrate, a first supply unit that supplies a first liquid containing the first pure water to a central section of a lower surface of the substrate, a second supply unit that supplies a second liquid containing the second pure water to a peripheral section and an intermediate section of the lower surface, and a heat amount control unit that independently controls an amount of heat to be supplied by the first supply unit and an amount of heat to be supplied by the second supply unit.

Abstract: Apparatus for coupling a hot wire source to a process chamber is provided herein. In some embodiments, an apparatus for coupling a hot wire source to a process chamber may include: a housing having an open end and a through hole formed through a top and a bottom of the housing; and a filament assembly configured to be disposed within the housing, the filament assembly having a frame and a plurality of filaments disposed across the frame, wherein the plurality of filaments of the filament assembly are substantially parallel with the top and the bottom of the housing and at least a portion of the plurality of filaments are disposed within the through hole of the housing when the filament assembly is disposed within the housing.

Abstract: According to one embodiment, there is provided a substrate processing apparatus including a processing chamber, a substrate processing unit, and a monitoring unit. A stage is placed in the processing chamber. A substrate is able to be put on the stage. The substrate processing unit is configured to process the substrate inside the processing chamber. The monitoring unit is configured to monitor a mass of the substrate via the stage with performing a correction according to a pressure, in a period when the substrate is being processed by the substrate processing unit.

Abstract: A high-efficiency buffer stocker is disclosed. The buffer stocker includes an overhead transport track for supporting overhead transport vehicles carrying wafer containers and at least one conveyor system or conveyor belt provided beneath the overhead transport track for receiving the wafer containers from the overhead transport vehicles on the overhead transport track. The buffer stocker is capable of absorbing the excessive flow of wafer containers between a processing tool and a stocker, for example, to facilitate the orderly and efficient flow of wafers between sequential process tools in a semiconductor fabrication facility, for example.

Abstract: In fabricating semiconductor packages, a first supporting unit is supported by a supporting substrate with one surface of an adhesive sheet directed upward, the first supporting unit being constituted by attaching the adhesive sheet having an adhesive layer as the one surface thereof and a non-adhesive layer as the other surface thereof to a frame member; semiconductor chips are mounted on the one surface of the adhesive sheet; on the adhesive sheet, a resin portion containing the semiconductor chips is formed by resin-sealing the semiconductor chips; the first supporting unit is removed from the second supporting unit; the resin portion is stripped from the adhesive sheet; external connection members are formed at the semiconductor chips contained in the resin portion; and portions between the respective semiconductor chips contained in the resin portion are cut to obtain individual semiconductor packages.

Abstract: An attachment method including an overlapping step of overlapping a support plate over a substrate under a reduced pressure environment; a temporary fixing step of temporarily fixing the support plate to the substrate; and an attaching step of attaching the support plate to the substrate under a reduced pressure environment. The method further includes, prior to the overlapping step, at least one of a first heating step in which heating is performed under an atmospheric pressure environment and a second heating step in which heating is performed under a reduced pressure environment.

Abstract: In a carrier system, a chuck unit is used to hold a placed wafer from above, and vertical-motion pins use suction to hold the wafer from below. Then, the chuck unit and the vertical-motion pins are subsequently lowered until a bottom surface of the wafer comes into contact with a wafer table. During the lowering, the holding force exerted by the chuck unit and the arrangement of chuck members are optimally adjusted such that, as a result of the restraint of the wafer by the chuck unit and the vertical-motion pins, localized surplus-restraint is imparted to the wafer, and warping does not occur.

Abstract: Disclosed are systems, devices and methodologies for handling wafers in wafer processing operations through use of wafer carriers. In an example situation, a wafer carrier can be configured as a plate to allow bonding of a wafer thereto to provide support for the wafer during some processing operations. Upon completion of such operations, the processed wafer can be separated from the support plate so as to allow further processing. Various devices and methodologies related to such wafer carriers for efficient handling of wafers are disclosed.

Abstract: Embodiments of apparatus for supporting a substrate are disclosed herein. In some embodiments, an apparatus for supporting a substrate includes a support member; and a plurality of substrate contact elements protruding from the support member, wherein each of the plurality of substrate contact elements includes: a first contact surface to support a substrate when placed thereon; and a second contact surface extending from the first contact surface, wherein the second contact surface is adjacent a periphery of the substrate to prevent radial movement of the substrate, wherein the first contact surface is at a first angle with respect to the support member and the second contact surface is at a second angle with respect to the support member, and wherein the first angle is between about 3 degrees and 5 degrees.

Abstract: A sample holder includes a substrate composed of ceramics, having a sample holding surface provided in an upper face thereof; a supporting member composed of metal, an upper face of the supporting member covering a lower face of the substrate; and a joining layer composed of indium or an indium alloy, the substrate and the supporting member being joined to each other via the joining layer. The joining layer has a layer region in at least one of a joining surface to the substrate and a joining surface to the supporting member, a content percentage of indium oxides of the layer region being higher than that of an intermediate region in a thickness direction of the joining layer.

Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.

Abstract: Provided are gap-fill methods.

Abstract: Among other things, one or more semiconductor arrangements comprising isolation trenches, and techniques for forming such isolation trenches are provided. A substrate comprises a front side surface and a backside surface. One or more devices are formed over the front side surface. A wet etch is performed to form a tapered portion of an isolation trench. A dry etch is performed to form a non-tapered portion of the isolation trench. Because both the wet etch and the dry etch are performed, etching time is reduced compared to merely using the dry etch due to the wet etch having a relatively faster etch rate than the dry etch. In an embodiment, the isolation trench provides isolation for a current leakage path associated with a device or other material formed over the front side surface. In an embodiment, metal is formed within the isolation trench for backside metallization.

Abstract: It is provided a handle substrate of a composite substrate for a semiconductor. The handle substrate is composed of a translucent polycrystalline alumina. A purity of alumina of the translucent polycrystalline alumina is 99.9% or higher, an average of a total forward light transmittance of the translucent polycrystalline alumina is 60% or higher in a wavelength range of 200 to 400 nm, and an average of a linear light transmittance of the translucent polycrystalline alumina is 15% or lower in a wavelength range of 200 to 400 nm.

Abstract: Provided are methods of surface treatment, semiconductor devices and methods of forming the semiconductor device. The methods of forming the semiconductor device include forming a first oxide layer and a second oxide layer on a substrate. The first and second oxide layers are patterned to form a contact hole exposing the substrate. A sidewall of the first oxide layer exposed by the contact hole reacts with HF to form a first reaction layer and a sidewall of the second oxide layer exposed by the contact hole reacts with NH3 and HF to form a second reaction layer. The first and second reaction layers are removed to enlarge the contact hole. A contact plug is formed in the enlarged contact hole.

Abstract: A method for fabricating a semiconductor device includes forming a first photo-sensitive layer over a contact pad, wherein the contact pad is on a substrate. The method further includes patterning the first photo-sensitive layer to form a first opening over a portion of the contact pad. The method further includes plating a conductive via in the first opening; and removing the first photo-sensitive layer. The method further includes forming a passivation layer over the substrate, contact pad, and conductive via, and exposing the conductive via by grinding the passivation layer. The method further includes forming a second photo-sensitive layer over the conductive via and passivation layer. The method further includes patterning the second photo-sensitive layer to form a second opening larger than and completely exposing the conductive via. The method further includes plating a conductive pillar in the second opening; and removing the second photo-sensitive layer.

Abstract: A method for self-aligning diamagnetic materials includes contacting first and second magnets together other along a contact line so as to generate a diametric magnetization that is perpendicular to the contact line. A diamagnetic rod is positioned with respect to the first and second magnets to levitate above the contact line of the first and second magnets.

Abstract: A method for a method of forming a semiconductor device includes providing a semiconductor substrate having a bottom surface opposite a top surface with circuitry disposed at the top surface. The method further includes forming a first metal layer having a first metal over the bottom surface of the semiconductor substrate. The first metal layer is formed by depositing an adhesion promoter followed by depositing the first metal.

Abstract: A method of forming a device may include: forming an opening through a dielectric layer and an underlying etching stop layer to expose a metal line. The method may further include the step of catalytically growing a graphene layer on an exposed surface of the metal line, and depositing an amorphous carbon layer on sidewalls of the opening. The steps of catalytically growing the graphene layer and depositing the amorphous carbon layer may be performed simultaneously.

Abstract: Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on copper instead of insulating or dielectric materials. In some embodiments, a first precursor forms a layer on the first surface and is subsequently reacted or converted to form a metallic layer. The deposition temperature may be selected such that a selectivity of above about 50% or even about 90% is achieved.

Abstract: A semiconductor structure and a method for forming the same are provided. The method includes forming a gate structure over a substrate and forming source and drain regions adjacent to the gate structure. The method also includes forming a first ILD layer surrounding the gate structure over the source and drain regions and forming a contact modulation structure over the gate structure. The method also includes etching the first ILD layer and the contact modulation structure to form a first contact trench over the source and drain regions and a second contact trench over the gate structure. The method further includes forming a first contact in the first contact trench and a second contact in the second contact trench. In addition, the first ILD layer has a first etching rate and the contact modulation structure has a second etching rate that is less than the first etching rate.