Patents Issued in January 12, 2016
  • Patent number: 9236861
    Abstract: A capacitive proximity sensor circuit capable of distinguishing between instances of detected user proximity includes one or more guard electrodes, a first sensor, and a second sensor. The capacitive proximity sensor is installed in a device such that a first sensor faces a first component of the device, and the second sensor faces a second component of the device. The first and second sensors measure a capacitance to detect proximity of a user relative to the respective sensor. The guard electrode is provided to mitigate stray capacitance to reduce error in the capacitance measurements obtained by the first and second sensors.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: January 12, 2016
    Assignee: STMicroelectronics Asia Pacific Pte Ltd
    Inventors: Jenn Woei Soo, Kien Beng Tan
  • Patent number: 9236862
    Abstract: A multi-layer body for providing a touch panel functionality has a plurality of areas of surface which have a different size defined by corresponding electrically conductive elements; in particular, larger areas of surface are arranged more in a central area of the entirety of the area of surface and smaller areas of surface are arranged more further toward an edge of the body.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: January 12, 2016
    Assignee: PolyIC GmbH & CO.KG
    Inventors: Walter Fix, Andreas Ullmann, Manfred Walter
  • Patent number: 9236863
    Abstract: Aspects of the invention provide for compensating impedance calibration circuits. In one embodiment, a compensated impedance calibration circuit, includes: a variable resistor network including a tunable resistor and a fixed resistor; and an external resistance network including a target external precision resistor and a parasitic distribution resistance; wherein a resistance of the variable resistor network is proportional to a resistance of the external resistance network, such that a ratio of an output voltage of the variable resistor network to a power supply voltage is constant.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: January 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Brian D. Jones, Jeffrey H. Sloan, Xiaopeng Wang
  • Patent number: 9236864
    Abstract: An integrated circuit (IC) is provided where the IC includes a first die, a second die stacked above the first die, and a plurality of die-to-die interconnects coupling the first die to the second die, where the plurality of die-to-die interconnects includes at least one redundancy die-to-die interconnect. In one implementation, the plurality of die-to-die interconnects includes a plurality of pre-designated die-to-die interconnects, where if a pre-designated die-to-die interconnect of the plurality of pre-designated die-to-die interconnects is defective, then signals intended for transmission via the pre-designated die-to-die interconnect are instead transmitted via the at least one redundancy die-to-die interconnect.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: January 12, 2016
    Assignee: Altera Corporation
    Inventors: Siang Poh Loh, Chooi Pei Lim
  • Patent number: 9236865
    Abstract: An apparatus for generating random bits includes a plurality of mapping devices. A respective mapping device is configured to map a predefined number of input signals, with the aid of a combinatorial mapping, into a predefined number of output signals. The plurality of mapping devices are concatenated with one another, and at least one combinatorial mapping is configured such that a state change of an input signal of a respective mapping device is mapped on average onto more than one output signal of the respective mapping device. No feedback loop is present such that a state change of at least one feedback output signal of a specific mapping device is fed as a state change of at least one input signal to another mapping device such that one or a plurality of output signals of the specific mapping device is influenced by the state change of the feedback output signal.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: January 12, 2016
    Assignee: Siemens Aktiengesellschaft
    Inventors: Pascale Böffgen, Markus Dichtl
  • Patent number: 9236866
    Abstract: A circuit for driving a gate of a power MOS transistor includes an adaptive pull-up unit and an adaptive pull-down unit. The adaptive pull-up unit is connected between a first power source voltage and the gate of the power MOS transistor. The adaptive pull-up unit maximizes pull-up current driving ability. The adaptive pull-down unit is connected between a second power source voltage and the gate of the power MOS transistor. The adaptive pull-down unit maximizes pull-down current driving ability.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: January 12, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyo-Sang Youn, Woo-Seok Kim
  • Patent number: 9236867
    Abstract: An integrated circuit (IC) includes a plurality of pads adapted to send or receive signals, and a plurality of mixed signal interface blocks, each of which is coupled to a corresponding pad in the plurality of pads. Furthermore, each mixed signal interface block in the plurality of mixed signal interface blocks is adapted to be configurable to provide selected functionality independently of the other mixed signal interface blocks.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: January 12, 2016
    Assignee: Silicon Laboratories Inc.
    Inventors: Jinwen Xiao, Pavel Konecny, Axel Thomsen, Clayton Daigle, Xiaodong Wang, John Khoury, Alan Westwick, Shahram Tadayon
  • Patent number: 9236868
    Abstract: An electronic device includes a resonator provided with a heating element, and a circuit component opposed to the heating element, and provided with at least an oscillating amplifier element, and a distance between the heating element and the circuit component is in a range not smaller than 0 mm and no larger than 1.5 mm.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: January 12, 2016
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Kensaku Isohata
  • Patent number: 9236869
    Abstract: In order to solve a problem that power consumption as to an edge sampling circuit is large in a semiconductor device in the related art, a semiconductor device according to one embodiment has a first sampling circuit for outputting an odd-numbered data value and an edge value and a second sampling circuit for outputting an even-numbered data value and an edge value, and a first offset and a second offset used for determining the edge value in one sampling circuit are determined based on a data value acquired from a location other than between a selector for selecting one of a plurality of data values sampled with a different offset in a path for sampling the data value and a shift register for transferring the data value selected by the selector in the other sampling circuit.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: January 12, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Katsuhiko Hata
  • Patent number: 9236870
    Abstract: In an integrated circuit, a first delay locked loop circuit is configured to adjust a phase of a first clock signal input to a first clock input terminal, and to at least one of transmit and receive information based on the phase-adjusted first clock signal. A second delay locked loop circuit is configured to adjust a phase of a second clock signal input to a second clock input terminal, and to at least one of transmit and receive information based on the phase-adjusted second clock signal. A path selection circuit is configured to select, in response to a select signal, one of a first signal path through the first delay locked loop circuit and a second signal path through the second delay locked loop circuit as a signal path for at least one of transmitting and receiving the information.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: January 12, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Tae-hyung Kim
  • Patent number: 9236871
    Abstract: A digital filter for a frequency synthesizer (e.g., PLL, UFT) may include an analog-to-digital (ADC) converter, which is responsive to a control voltage at an input thereof, and a digital-to-analog (DAC) converter, which has an input responsive to a signal generated at an output of the ADC. An impedance element is provided between the DAC and ADC. The impedance element has real and reactive components, a first current carrying terminal electrically coupled to an output of the DAC and a second current carrying terminal electrically coupled to the input of the ADC. The impedance element can include a resistor and a capacitor, which are electrically connected in parallel. A gain device, such as a programmable multiplier, may also be provided, which has an input responsive to the signal generated at the output of the ADC and an output electrically coupled to the input of the DAC.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: January 12, 2016
    Assignee: Integrated Device Technology, inc.
    Inventors: Pengfei Hu, Brian Buell
  • Patent number: 9236872
    Abstract: The present invention is for, in a voltage-controlled oscillator in which the oscillation frequency can be adjusted using a capacitor array, reducing drift that occurs in the carrier frequency if the oscillation signal is subjected to frequency modulation after the control loop of the PLL circuit has been cut off. This voltage-controlled oscillator includes an oscillation circuit for performing an oscillation operation at a frequency that corresponds to an inductance and a capacitance between a first node and a second node, a first and second group of capacitors that have first terminals connected to the first node and the second node respectively, a first and second group of transistors that are respectively connected between a reference potential and second terminals of the first group and second group of capacitors, and a first and second group of resistors that are respectively parallel-connected to the first group and second group of transistors.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: January 12, 2016
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Koichi Tsuhara, Rikiichi Uchino, Katsuhiko Maki
  • Patent number: 9236873
    Abstract: A PLL includes a fractional divider to generate a periodic PLL output signal in response to REFHF. The fractional divider includes a digital control circuit (DDC) responsive to a digital control input signal and a multi-modulus divider (MMD), which is responsive to REFHF and a first digital control output signal generated by the DDC. A feedback divider (FD) is provided to generate a FD output signal in response to an MMD output signal generated by the MMD. A phase detector (PD) is provided to generate a PD output signal in response to the FD output signal and REF_CLK. A loop filter is provided to generate the digital control input signal in response to the PD output signal as modified by a noise cancellation signal (NCS). The NCS is generated to at least partially compensate for non-random deterministic noise in the MMD output signal.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: January 12, 2016
    Assignee: Integrated Device Technology, Inc.
    Inventor: Brian Buell
  • Patent number: 9236874
    Abstract: Provided are methods and systems for reducing a transition rate in transmitting data between analog and digital chips in Sigma-Delta Modulator (SDM) based Digital to Analog Converters (DACs) and Analog to Digital Converters (ADCs) intended to be used in audio signal processing. An example method may comprise receiving, by a digital chip, SDM binary data, mapping the SDM binary data to transition binary codes, and transmitting the transition binary codes to an analog chip. The mapping can be carried out according to a principle that the more commonly used SDM binary data codes correspond to transition binary data codes that require that fewer transitions occur in the signals between the chips. The methods and systems described provide for lowering the power needed for carrying out the data transmission between digital and analog chips.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: January 12, 2016
    Assignee: Audience, Inc.
    Inventor: David P. Rossum
  • Patent number: 9236875
    Abstract: To provide a D/A converter including a sampling circuit capable of suppressing a high-frequency component in an input signal without obstructing downsizing of electronic equipment. A D/A converter includes a first capacitative element unit including plural sampling capacitors, a second capacitative element unit including plural sampling capacitors, a first switch unit including the plural switches configured to store charges in the plural sampling capacitors of the first capacitative element unit and to transfer the charge, and a second switch unit including the plural switches configured to store charges in the plural sampling capacitors of the second capacitative element unit and to transfer the charge. The first and the second switch units operate alternately.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: January 12, 2016
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Yutaka Nakanishi, Junya Nakanishi
  • Patent number: 9236876
    Abstract: A double-integration type A/D converter for performing A/D conversion by integrating an input voltage and a reference voltage is disclosed. The A/D converter includes an integrator configured to integrate the input voltage and the reference voltage; a first switch configured to relay supply of the input voltage to an input terminal of the integrator; a second switch configured to relay supply of the reference voltage to the input terminal; and a control circuit configured to control switching on and off the first switch and the second switch. The control circuit generates a switching signal that switches on and off the first switch and the second switch individually and a switching signal that switches on and off the first switch and the second switch simultaneously. In addition, superimposition of the input voltage and the reference voltage is integrated when the first switch and the second switch are simultaneously switched on.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: January 12, 2016
    Assignee: Rohm Co., Ltd.
    Inventor: Takashi Miyake
  • Patent number: 9236877
    Abstract: A micro-electro-mechanical system (MEMS) includes a micro-mechanical structure that generates a first electrical signal. An analog-to-digital converter (ADC) is coupled with the micro-mechanical structure. The first electrical signal is converted to a second electrical signal using a converter coupled between the micro-mechanical structure and the ADC. The first electrical signal is free from being amplified.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: January 12, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Chow Peng, Wen-Hung Huang, Yu-Wei Lin
  • Patent number: 9236878
    Abstract: A method is disclosed. An analog signal is sampled to form a sample value using a sample and hold circuit. The sample value is converted to form a first digital result. The sample value is converted to form a second digital result.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: January 12, 2016
    Assignee: Infineon Technologies AG
    Inventors: Peter Bogner, Herwig Wappis, Jens Barrenscheen
  • Patent number: 9236879
    Abstract: According to this A/D converter, a first A/D conversion operation for performing integral A/D conversion and a second A/D conversion operation for performing cyclic A/D conversion are realized based on control of operational procedures in a same circuit configuration. Moreover, in the first A/D conversion operation, since a capacity of a capacitor used in the integration of an output signal is greater than a capacity of a capacitor used for storing an input analog signal and a standard reference voltage, the analog signal that is input in the integral A/D conversion is attenuated according to the capacity ratio and subject to sampling and integration. Consequently, the voltage range of the analog signal that is output in the integral A/D conversion also decreases according to the capacity ratio of the capacitors, and the A/D converter can be therefore constructed with a single-ended configuration.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: January 12, 2016
    Assignee: NATIONAL UNIVERSITY CORPORATION SHIZUOKA UNIVERSITY
    Inventor: Shoji Kawahito
  • Patent number: 9236880
    Abstract: The systems, methods, and devices disclosed herein relate to a bit-per-stage ADC. The bit-per-stage ADC extracts one or more bits at each stage and creates a residue so that succeeding similar or identical stages can extract more bits. The ADC uses a reflected binary output code so that a bit can be extracted by observing the sign (e.g., polarity) of an input. The residue can be generated by rectifying the input, multiplying it by two, and level-shifting it by half the span. The generation of the residue is achieved using capacitors and switches. This causes the ADC to have low power consumption and a small size.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: January 12, 2016
    Assignee: Analog Devices, Inc.
    Inventor: John Memishian
  • Patent number: 9236881
    Abstract: The present invention relates to compression of values and bitmaps, and methods thereof. Such methods are configured for operating on a computer system having a word length architecture of length WL and are based on the observation that not all the bits used for the run-length counter—i.e., the fill length field (FL) inhere—are often used, since runs are seldom so long. Contrarily to other compression schemes (e.g., WAH), said methods may assign the unused bits to one or more position list fields (PL, PL1, PL2, PLs), thus boosting the compression ratio. Moreover, the total length (in terms of number of bits) of the uncompressed data—comprising values or bitmaps—may be stored just once, preferably at the beginning of the compression, thus dramatically diminishing the storage requirements for the compression scheme, since it is not required to keep track of the length of each bitmap word while performing the compression or the decompression.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: January 12, 2016
    Assignee: Algorhyme A/S
    Inventor: Torben Bach Pedersen
  • Patent number: 9236882
    Abstract: Data compression using a combination of content independent data compression and content dependent data compression. In one aspect, a system for compressing data comprises: a processor, and a plurality of data compression encoders wherein at least one data encoder utilizes asymmetric data compression. The processor is configured to determine one or more parameters, attributes, or values of the data within at least a portion of a data block containing either video or audio data, to select one or more data compression encoders from the plurality of data compression encoders based upon the determined one or more parameters, attributes, or values of the data and a throughput of a communications channel, and to perform data compression with the selected one or more data compression encoders on at least the portion of the data block.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: January 12, 2016
    Assignee: REALTIME DATA, LLC
    Inventor: James J. Fallon
  • Patent number: 9236883
    Abstract: A computer device may receive a codebook, and generate a unitary transformation operator for the codebook. Furthermore, the computer device may decompose the unitary transformation operator into representations of two or more devices, and cause a generating of a layout of a photonic circuit that includes the two or more devices.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: January 12, 2016
    Assignee: RAYTHEON BBN TECHNOLOGIES CORP.
    Inventor: Saikat Guha
  • Patent number: 9236884
    Abstract: A method, an apparatus, and a computer program product for communication within a wireless terminal. The method can be implemented using dedicated logic and managed and controlled by state machines and/or sequencers. Data received or provided in a memory of a first integrated circuit of a terminal is encoded and transmitted in a data packet to a second integrated circuit. A header identifying the data type and providing a destination is included in the data packet. The destination may be identified as a memory address memory of the second integrated circuit that is mapped to a corresponding memory address of the first integrated circuit at which the data is received. In an aspect, the apparatus receives a header, detects an error in the received header, determines a failure to identify a packet boundary when the error is detected, and performs a search operation to identify the packet boundary.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: January 12, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Hans Georg Gruber, Subra Dravida, Parvathanathan Subrahmanya, Vidyut Mukund Naware, Helena Deirdre O'Shea, Garret Webster Shih, Jason Thurston
  • Patent number: 9236885
    Abstract: A method of encoding data into a chain reaction code includes generating a set of input symbols from input data. Subsequently, one or more non-systematic output symbols is generated from the set of input symbols, each of the one or more non-systematic output symbols being selected from an alphabet of non-systematic output symbols, and each non-systematic output symbol generated as a function of one or more of the input symbols. As a result of this encoding process, any subset of the set of input symbols is recoverable from (i) a predetermined number of non-systematic output symbols, or (ii) a combination of (a) input symbols which are not included in the subset of input symbols that are to be recovered, and (b) one or more of the non-systematic output symbols.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: January 12, 2016
    Assignee: Digital Fountain, Inc.
    Inventors: Mohammad Amin Shokrollahi, Michael G. Luby
  • Patent number: 9236886
    Abstract: The various implementations described herein include systems, methods and/or devices that may enhance performance of error control encoding. The method includes receiving information data and generating parity information based on an m×k parity matrix comprising an array of b×b circulant sub-matrices, including m columns of said sub-matrices, each column comprising k said sub-matrices. The method further includes dividing the information data into a plurality of b-sized trunks and generating m parity segments. Each parity segment consists of b bits, and each parity segment is generated by multiplying each of the k b×b circulant sub-matrices in a respective column of the parity matrix by a corresponding trunk of information data, where each multiplication of a b×b circulant sub-matrix by a corresponding trunk comprises b2 concurrent computations. The method further includes generating a codeword based on the information data and the m parity segments.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: January 12, 2016
    Assignee: SANDISK ENTERPRISE IP LLC
    Inventors: Jiangli Zhu, Ying Yu Tai, Xiaoheng Chen
  • Patent number: 9236887
    Abstract: A method of encoding data operates on an ordered set of input symbols and includes generating redundant symbols from the input symbols, and includes generating output symbols from a combined set of symbols including the input symbols and the redundant symbols, wherein the number of possible output symbols is much larger than the number of the combined set of symbols, wherein at least one output symbol is generated from more than one symbol in the combined set of symbols and from less than all of the symbols in the combined set of symbols. The redundant symbols are generated from an ordered set of input symbols in a deterministic process such that a first set of static symbols calculated using a first input symbol has a low common membership with a second set of static symbols calculated using a second input symbol distinct from the first input symbol.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: January 12, 2016
    Assignee: Digital Fountain, Inc.
    Inventors: Michael G. Luby, M. Amin Shokrollahi, Mark Watson
  • Patent number: 9236888
    Abstract: According to an embodiment, a storage device includes: a semiconductor memory that includes a multilevel memory cell, stores a first code word and a second code word, and in which a plurality of memory cells connected to one word line can store a plurality of pages; and a controller. The controller performs error correction processing of the first code word read out from one page among the plurality of pages of the semiconductor memory, and the second code word written in a page other than the page corresponding to the first code word among the plurality of pages, re-reads the first code word when the first code word is uncorrectable and the second code word was able to be corrected by the error correction processing, and determines a bit value of the first code word using a re-read result and the second code word after error correction.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: January 12, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Susumu Yamazaki, Kenji Yoshida
  • Patent number: 9236889
    Abstract: A maximum a posteriori (MAP) decoding apparatus and method are provided, which select a path having a maximum value without calculating all path metrics by generating metric difference vectors based on generated tables, calculating metrics of a path formed through a combination of a state and a branch each having a maximum metric, and calculating an index and a metric of a current state to which a calculation value is to be applied based on a result of comparing a state metric difference vector and a branch metric difference vector.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: January 12, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yong Ho Lee, Deock Gil Oh
  • Patent number: 9236890
    Abstract: A method for decoding includes receiving channel inputs for respective bits of a super code word that includes at least first and second component code words having a shared group of bits. At least the first and second component code words are iteratively decoded, and, in response to recognizing that the first and second component code words contain errors only within the shared group of bits, the first and second component code words are jointly decoded.
    Type: Grant
    Filed: December 14, 2014
    Date of Patent: January 12, 2016
    Assignee: APPLE INC.
    Inventors: Micha Anholt, Moti Teitel, Tomer Ish-Shalom
  • Patent number: 9236891
    Abstract: A radio communication transmitter apparatus 20 is operable to transmit multiple radio frequency bands in a telecommunication system. The apparatus comprises a plurality of digital transmitter chains 211 to 21N, wherein each digital transmitter chain is coupled to receive a digital representation 271 to 27N of a respective base band signal for processing by a respective digital transmitter chain. Each digital transmitter chain 211 to 21N comprises a digital transmitter 251 to 25N that is adapted to convert a respective digital base band signal directly into a digital representation of a radio frequency signal 231 to 23N. A digital combining unit 25 is coupled to receive the output of each digital transmitter chain 211 to 21N, and adapted to combine the digital representation of a radio frequency signal 231 to 23N received from each digital transmitter chain 211 to 21N into a digital representation of a radio frequency signal 26 comprising multiple radio frequency bands.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: January 12, 2016
    Assignee: Telefonaktiebolaget L M Ericsson (Publ)
    Inventors: Bernt Johansson, Bo Berglund
  • Patent number: 9236892
    Abstract: Logarithmic Detector Amplifiers (LDAs), multiple antennas, active antennas, and multiple active antennas and receivers are provided in a variety of configurations that are synchronized to reduce or eliminate interference so at to provide, a greater range and bandwidth between wireless routers and their clients in WLAN and WAN environments.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: January 12, 2016
    Assignee: DOCKON AG
    Inventors: Alexandre Dupuy, Patrick Rada, Forrest Brown
  • Patent number: 9236893
    Abstract: A distortion compensation device which compensates for a distortion of an amplifier includes an FIR filter, a calculation unit that calculates an error between a reference signal and a feedback signal from the amplifier, an update unit that updates a coefficient set to the FIR filter on the basis of the error, and a delay unit that, on the basis of a magnitude of the coefficient, delays the feedback signal while controlling a delay of the feedback signal with respect to the reference signal.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: January 12, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Hiroyoshi Ishikawa, Kazuo Nagatani
  • Patent number: 9236894
    Abstract: A pulsed multi-channel UWB receiver. The receiver includes a first stage translating a received signal into baseband or at an intermediate frequency, a second stage carrying out quadrature mixing on the in-phase and quadrature channels of the first stage, a third stage carrying out an integration on a time window of the signals from the second stage, and a fourth stage carrying out a combination of the integration results from the third stage to provide the real part and the imaginary part of the modulation symbol. The receiver is configurable according to the receiving channel and processing type selected.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: January 12, 2016
    Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, BE SPOON
    Inventors: Laurent Ouvry, Francois Dehmas, Frederic Hameau, Gilles Masson
  • Patent number: 9236895
    Abstract: In a Radio Frequency (RF) filter, a first conductive link has a first length corresponding to a first (N) number of wavelengths of a primary RF frequency. A second conductive link has a second length corresponding to both a second (M) number of wavelengths of the primary RF frequency and an out-out-phase (X) number of wavelengths of a secondary RF frequency. An input interface receives an input RF signal and transfers a first component of the input signal over the first link and transfers a second component of the input RF signal over the second link. An output interface combines the first component from the first link with the second component from the second link to transfer an output RF signal. The energy at the primary frequency constructively combines in-phase, but the energy at the secondary frequency destructively combines out-of-phase.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: January 12, 2016
    Assignee: Clearwire IP Holdings LLC
    Inventor: Walter F. Rausch
  • Patent number: 9236896
    Abstract: A wireless communications system is provided with a first wireless communications module, a second wireless communications module, and an RF module. The first wireless communications module transmits or receives a first wireless signal, and the second wireless communications module transmits or receives a second wireless signal. The RF module allocates a first transceiving path and a second transceiving path to the first wireless communications module and the second wireless communications module, respectively, to enable the transmission or reception of the first wireless signal and the second wireless signal at the same time.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: January 12, 2016
    Assignee: MEDIATEK INC.
    Inventors: Chih-Hao Yeh, Hong-Kai Hsu, En-Chieh Hsia, Hsien-Chyi Chiou, Wei Wang, Shu-Ping Shiu
  • Patent number: 9236897
    Abstract: A method for transporting communications signals includes receiving an analog IF signal at a first unit. The analog IF signal includes a first carrier having a first frequency and a first bandwidth and a second carrier having a second frequency different from the first frequency and a second bandwidth. The analog IF signal is converted to a digitally sampled IF signal having the first carrier located in a first Nyquist zone, the second carrier located in a second Nyquist zone, an image of the first carrier located in a third Nyquist zone, and an image of the second carrier located in the third Nyquist zone. The image of the first carrier and the image of the second carrier is transmitted from the first unit to a second unit, where the image of the first carrier and the image of the second carrier is then converted to the analog IF signal.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: January 12, 2016
    Assignee: Dali Systems Co. Ltd.
    Inventors: Shawn Patrick Stapleton, Wan-Jong Kim
  • Patent number: 9236898
    Abstract: Transmitter observation receivers and methods are described that can predistortion-compensate transmitters capable of operating in multiple communication bands and frequency ranges. Such observation receivers and method involve generating at least one compensation signal such that a signal to be transmitted that is within a bandwidth that simultaneously encompasses multiple frequency ranges is compensated.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: January 12, 2016
    Assignee: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
    Inventors: Bradley John Morris, Somsack Sychaleun
  • Patent number: 9236899
    Abstract: A method, system and circuit for crest factor reduction of inter-band multi-standard carrier aggregated signals are disclosed. In one embodiment, a method includes calculating the amplitude of each of the plurality of carrier signals of the inter-band carrier aggregated signals. An estimate of an envelope of a combination of the carrier signals is produced based on a sum of the calculated amplitudes of the plurality of carrier signals. The estimate of the envelope of the combination of the carrier signals is compared to a clipping threshold to determine whether to clip each of the plurality of carrier signals.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: January 12, 2016
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventors: Bilel Fehri, Slim Boumaiza
  • Patent number: 9236900
    Abstract: Disclosed are a radio transmission device and a radio transmission method which can reduce a processing amount or a memory amount while maintaining the randomizing effect of other cell interference. When using as a reference signal, a ZC sequence of the sequence length uniquely correlated to a transmission bandwidth of a reference signal, as the transmission bandwidth becomes smaller and the sequence length of the ZC sequence becomes shorter, the sequence is switched at a shorter time interval and as the transmission bandwidth becomes greater and the sequence length of the ZC sequence becomes longer, the switching is performed at a longer time interval. Thus, a reference signal is generated by using the ZC sequence in accordance with the timing into which the reference signal transmission bandwidth and the sequence are switched.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: January 12, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Takashi Iwai, Daichi Imamura, Sadaki Futagi, Yoshihiko Ogawa, Tomofumi Takata, Atsushi Matsumoto
  • Patent number: 9236901
    Abstract: Code detection to assist a symbol-level equalizer in a receiver is described. In an embodiment, code detection uses adaptive Infinite Impulse Response (IIR) filtering to determine spreading code usage information and active code channels in a received signal. The spreading code usage information indicates if a spreading code associated with a code channel is among spreading codes used in the received signal. In another embodiment, the spreading code usage information is determined based on a forgetting factor associated with the filtering of a symbol power associated with the code channel.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: January 12, 2016
    Assignee: Broadcom Corporation
    Inventors: Hou-Shin Chen, Fu-Hsuan Chiu
  • Patent number: 9236902
    Abstract: The present invention describes a method and apparatus for implementing a mobile receiver (10) that combats multiple access interference (MAI) in a code division multiple access (CDMA) spread spectrum system. Such capability is required by mobile receivers to support high data rate applications such as the ones provided by HSDPA and 1xTREME. A receiver (10) combining equalization and interference cancellation (IC), according to the invention, avoids the shortcomings of either equalization or IC and provides superior performance relative to prior art methodologies. The approach proposed by this invention for the operation of the mobile receiver is to first perform equalization (12) of the received signal (r) and then use the resulting decisions to perform IC. Combining equalization and IC yields a complexity that is smaller to that obtained by implementing conventional IC with a Rake receiver for the same performance.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: January 12, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Aris Papasakellariou
  • Patent number: 9236903
    Abstract: A method for detecting multi-path interference in a spread-spectrum signal. A variation of a first signal and a variation of a second signal is compared. The variation of the first signal corresponds to a correlation of the spread-spectrum signal and a spreading code having a first offset. The variation of the second signal corresponds to a correlation of the spread-spectrum signal and the spreading code having a second offset. Multi-path interference is detected in dependence on the comparison.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: January 12, 2016
    Assignee: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
    Inventor: Philip Mattos
  • Patent number: 9236904
    Abstract: In one embodiment, a device determines a need to resynchronize a broadcast and unicast frequency-hopping schedules on its network interface. In response to the need, the device may solicit the broadcast schedule from one or more neighbor devices having the synchronized broadcast schedule, and then establishes the unicast schedule for the network interface using communication during the synchronized broadcast schedule.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: January 12, 2016
    Assignee: Cisco Technology, Inc.
    Inventors: Jonathan W. Hui, Wei Hong, Jean-Philippe Vasseur
  • Patent number: 9236905
    Abstract: A wireless communication system in which a master device and a slave device each performing wireless communication by a frequency hopping system can operate in synchronism with each other. In the master device, a master microcomputer outputs a first sync signal to a RTC unit after a transmission timing signal is received and a carrier frequency is changed a predetermined number of times according to a first change timing signal. In the slave device, a slave microcomputer outputs a second sync signal to a RTC unit after a reception timing signal is received and a carrier frequency is changed the predetermined number of times according to a second change timing signal.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: January 12, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Kei Tohyama
  • Patent number: 9236906
    Abstract: A transmitter device transmits data over a physical communication link to at least one destination. A monitor resource monitors a frequency band of signals on the physical communication link. At least a portion of the monitored frequency band in the physical communication link used to transmit the data is also allocated for transmissions of wireless communications in a vicinity of the physical communication link. The physical communication link may be damaged for any number of reasons such as a loose connector, rodent chewing on the physical communication link, etc. The damaged locations of the physical communication link are places where the wireless communications are more likely to couple onto the physical communication link and cause interference. In response to detecting presence of an interference signal in the monitored frequency band of the physical communication link, the monitor resource transmits one or more notifications.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: January 12, 2016
    Assignee: Time Warner Cable Enterprises LLC
    Inventors: Don Gunasekara, Harriet DuBois, Kevin Caldwell
  • Patent number: 9236907
    Abstract: An electronic device comprising a laminate constituted by pluralities of insulation layers on which conductor patterns are formed; ground electrodes being formed on an upper-surface-side insulation layer and a bottom-surface-side insulation layer in the laminate; the laminate being partitioned to first and second regions by a first shield constituted by a line of via-holes electrically connecting the upper-surface-side ground electrode to the bottom-surface-side ground electrode; conductor patterns constituting a first filter for a first frequency band and conductor patterns constituting a first balun for the first frequency band being arranged in the first and second regions, respectively; pluralities of terminal electrodes being formed on bottom or side surfaces of the laminate; one of terminal electrodes of the first filter, which acts as an unbalanced port, being adjacent to a terminal electrode of the first balun, which acts as an unbalanced port, with no other terminal electrode than a ground electrode
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: January 12, 2016
    Assignee: HITACHI METALS, LTD.
    Inventor: Hirotaka Satake
  • Patent number: 9236908
    Abstract: An obstruction lighting and power line communication system is provided. The system includes a first controller coupled to and configured to control a first light source. The system includes a first transceiver associated with the first light source and configured to transmit and receive telemetry data signals associated with the first light source. The system includes a power line cable coupling the first controller and the first transceiver. The system includes a power supply coupled to the power line cable and configured to provide power to the first light source over the power line cable. The system includes a system controller configured to exchange control and telemetry signals with the first controller and the first transceiver over the power line cable.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: January 12, 2016
    Assignee: SPX Corporation
    Inventors: Christopher Range, Russell Bruner
  • Patent number: 9236909
    Abstract: An embodiment is an integrated System on Chip (SoC) including a communication interface configured to implement a communication protocol including functional blocks that are energized or de-energized individually so that a minimum power consumption is used to receive and detect a signal, and a receiver identification (ID) detection function configured to determine whether the signal is intended for the device in which the SoC resides. The SoC further includes a power management function configured to control which functions in the SoC and/or device in which the SoC resides are energized or de-energized depending on the results of the receiver ID detection function, and a power source capable of energizing a minimum number of the functional blocks required to receive and detect a signal, wherein the power source can be used in a low power state and switched over to a main power supply when the SoC is energized.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: January 12, 2016
    Assignee: STMicroelectronics, Inc.
    Inventor: Oleg Logvinov
  • Patent number: 9236910
    Abstract: In an in-vehicle power line communication system in which a power line communication network and a battery are connected to each other via a first power line, the power line communication network includes a master power line communication node connected to the battery via the first power line, a second power line, slave power line communication nodes including at least a transmitting slave power line communication node and a receiving slave power line communication node, a transmitting-side in-vehicle device, and a receiving-side in-vehicle device. The master power line communication node and the slave power line communication nodes communicate with each other using a time-triggered communication protocol. The mutual communicating of the slave power line communication nodes are controlled by a token signal output from the master power line communication node. Only the master power line communication node and the slave power line communication nodes are connected to the second power line.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: January 12, 2016
    Assignee: HONDA MOTOR CO., LTD.
    Inventor: Tsuyoshi Eguchi