Abstract: A flat panel photovoltaic (PV) system is provided formed from a first sheet with rows of concentrated III-V photovoltaic (CPV) solar cells. An overlying second sheet is made up of rows of waveguides, where each waveguide is coupled to a corresponding CPV solar cell. A third sheet includes overlying one-piece linear lenses, each having a focal line coupled to the waveguides in a corresponding row. Optionally, a fourth sheet underlies the first sheet, which is a 1-sun solar panel including a plurality of silicon PV cells. In one variation adjacent rows of waveguides couple to the same row of CPV cells. In another variation, each waveguide in a row is optically coupled to waveguides in an adjacent row, which adjacent waveguides are then coupled to a corresponding row of CPV cells. A lens overlies each row of waveguides, with a focal line coupled to each waveguide in that row.

Abstract: A method is provided for using asymmetrically focused photovoltaic conversion in a hybrid parabolic trough solar power system. Light rays received in a plurality of transverse planes are concentrated towards a primary linear focus in an axial plane, orthogonal to the transverse planes. T band wavelengths of light are transmitted to the primary linear focus, while R band wavelengths of light are reflected towards a secondary linear focus in the axial plane. The light received at the primary linear focus is translated into thermal energy. The light received at the secondary linear focus is asymmetrically focused along a plurality of tertiary linear foci, orthogonal to the axial plane. The focused light in each tertiary linear focus is concentrated into a plurality of receiving areas and translated into electrical energy. Asymmetrical optical elements are used having an optical input interfaces elongated along rotatable axes, orthogonal to the axial plane.

Abstract: Method and apparatus for obtaining photovoltaic (PV) module I-V curve data. In one embodiment, the method comprises reducing an operating voltage of a PV module coupled to a power conditioner to a minimum operating value; once the operating voltage has stabilized at the minimum operating value, stopping power production in the power conditioner; and determining, by the power conditioner, a plurality of sets of I-V curve data from PV module, wherein each set of I-V curve data in the plurality of sets comprises a voltage value indicating output voltage from the PV module and a current value indicating output current from the PV module.

Abstract: A crystal oscillator achieves fast start-up by injecting an in-band periodic signal into the crystal oscillator driver circuit. The in-band periodic signal has a frequency that is within a bandwidth of the crystal oscillator. Injection of the in-band periodic signal begins in response to a power-up condition and stops after a predetermined time period corresponding to the amount of time it takes to ensure the crystal driver is achieving full swing.

Abstract: In one aspect, a VCO is provided. The VCO includes an inductor, a voltage-controlled capacitive element configured to operate with the inductor to generate an oscillating signal, a voltage supply configured to provide a plurality of voltages to the voltage-controlled capacitive element in a calibration mode, and a control circuit configured to store frequency information indicating frequencies of the oscillating signal in response to the plurality of voltages being provided to the voltage-controlled capacitive element. In another aspect, a PLL is provided. The PLL includes means for selecting, in an open loop configuration, a capacitance of a capacitor based on a target frequency and means for selecting, in a closed loop configuration, an operation voltage of a voltage-controlled capacitive element based on the capacitance of the capacitor.

Abstract: A novel and useful RF oscillator suitable for use in applications requiring ultra-low voltage and power. The oscillator structure, employing alternating current source transistors, combines the benefits of low supply voltage operation of conventional NMOS cross-coupled oscillators together with high current efficiency of the complementary push-pull oscillators. In addition, the 1/f noise upconversion is also reduced. The oscillator can be incorporated within a wide range of circuit applications, including for example a conventional phase locked loop (PLL), all-digital phase-locked loop (ADPLL), wireline transceiver circuits and mobile devices.

Abstract: The disclosure provides an oscillator circuit for a voltage controlled oscillator. The oscillator circuit includes first and second coupled transmission lines, wherein the oscillator circuit is configured to provide a variable load impedance at a first end of a signal line of the first transmission line such that a variable inductance is provided between first and second ends of a signal line of the second transmission line in dependence on the variable load impedance. The oscillator circuit is configured to adjust the variable inductance provided between the first and second ends of the signal line of the second transmission line by adjusting the variable load impedance provided at the first end of the signal line of the first transmission line, wherein the variable inductance provided between the first and second ends of the signal line of the second transmission line constitutes a frequency determining element of the oscillator circuit.

Abstract: A novel and useful 60 GHz frequency generator based on a third harmonic extraction technique which improves system level efficiency and performance. The frequency generator employs a third harmonic boosting technique to increase the third harmonic at the output of the oscillator. The oscillator generates both ˜20 GHz fundamental and a significant amount of the third harmonic at ˜60 GHz and avoids the need for a frequency divider operating at 60 GHz. The undesired fundamental harmonic at ˜20 GHz is rejected by the good fundamental HRR inherent in the oscillator buffer stage while the ˜60 GHz component is amplified to the output. The fundamental harmonic is further suppressed by an active cancellation by properly combining the two outputs. The oscillator fabricated in 40 nm CMOS exhibits a phase noise of ?100 dBc/Hz at 1 MHz offset from a 60 GHz carrier and have a tuning range of 25%.

Abstract: A crystal oscillator, including: a voltage stabilizing unit, a transconductance unit, a feedback resistor, a crystal resonator and at least two ground capacitors. The voltage stabilizing unit includes a current source and a first branch circuit including PMOS and NMOS connected in series, PMOS has its source connected to output of the current source, PMOS and NMOS have their gates connected to drains thereof, and NMOS has its source connected to ground. The transconductance unit includes a second branch circuit including PMOS and NMOS connected in series, PMOS has its source connected to output of the voltage stabilizing unit, PMOS and NMOS have their gates connected to input of the crystal resonator and one end of the resistor, and have their drains connected to output of the crystal resonator and another end of the resistor. The capacitors are connected to two ends of the crystal resonator respectively and ground.

Abstract: An amplifier having orthogonal tuning elements is provided. In one embodiment, an amplifier comprises an input amplifier stage having a first tuning element used to control a first performance criteria of the amplifier; an output amplifier stage operatively coupled to the first amplifier stage; a bias circuit operatively coupled to the second amplifier stage and having a second tuning element used to control a second performance criteria of the amplifier; and wherein the first tuning element operates substantially independent of the second tuning element.

Abstract: One object of this invention is to provide a structure of integrated power transistor device having low thermal budget metal oxynitrides as the active channel on a CMOS logic and control circuit chip to form an integrated intelligent power switching module for power switching. The other object of this invention is to provide a structure of integrated power amplifier transistor device having low thermal budget metal oxynitride active channel layer on a CMOS logic and control circuit chip to form an integrated intelligent microwave power amplifier for RF power amplification.

Abstract: A novel and useful fully integrated switched-mode wideband 60 GHz power amplifier architecture. Using an appropriate second-harmonic termination of its output matching network, the required systematic peak current of the final stage is reduced such that the PA functions as a class-E/F2 switched-mode PA at saturation. In addition, low/moderate magnetic coupling factor transformers in the intermediate stages enable the PA to reach a high power added efficiency (PAE) and bandwidth product. Transformers of low/moderate coupling are also utilized in the preliminary stages of the PA to improve the overall bandwidth. In addition, the PA exploits the different behavior of the output impedance matching network for differential mode (DM) and common mode (CM) excitations. The PA is also stabilized against the combination of DM and CM oscillation modes. The PA also provides a technique to stabilize transformer-based mm-wave amplifiers against various modes of undesired oscillations.

Abstract: Described embodiments provide a radio frequency (RF) amplifier system having at least one amplifier. The at least one amplifier includes an RF input port, an RF output port and a drain bias port. At least one voltage modulator is coupled to the bias port of the least one amplifier to provide a bias voltage. The bias voltage is selected by switching among a plurality of discrete voltages. At least one filter circuit is coupled between the at least one voltage modulator and the at least one amplifier. The at least one filter circuit controls spectral components resultant from transitions in the bias voltage when switching among the plurality of discrete voltages. A controller dynamically adapts at least one setting of the at least one voltage modulator by using multi-pulse transitions when switching among the plurality of discrete voltages for a first operating condition of the RF amplifier.

Abstract: Envelope power supply circuitry includes power converter circuitry and envelope tracking circuitry. The power converter circuitry is configured to receive an envelope power converter control signal and a supply voltage and provide an envelope power supply signal for an amplifier from the supply voltage and based on the envelope power converter control signal. The envelope tracking circuitry is coupled to the power converter circuitry. In a first mode of operation, the envelope tracking circuitry is configured to provide the envelope power converter control signal such that a gain of the amplifier remains substantially constant over a range of input power provided to the amplifier. In a second mode of operation, the envelope tracking circuitry is configured to limit the dynamic range of the envelope power supply signal.

Abstract: Peak voltage limiting circuits and method for power amplifiers. A power amplifier and/or a voltage limiting circuit includes a diode circuit coupled to an output of an amplification stage, the diode circuit configured to provide a conductive path from the output when an output voltage exceeds a selected value. The power amplifier and/or voltage limiting circuit also includes a sink circuit coupled to the diode circuit and a bias circuit, the sink circuit configured to reduce a bias voltage provided by the bias circuit when the output voltage exceeds the selected value to thereby limit the output voltage.

Abstract: A transmission line driver circuit includes: a transmission line driving amplifier having a first transmission terminal and a second transmission terminal; a first signal node; a second signal node; a first adjustable resistor positioned between the first transmission terminal and the first signal node; a second adjustable resistor positioned between the second transmission terminal and the second signal node; an internal node; a first divider resistor positioned between the first signal node and the internal node; a second divider resistor positioned between the second signal node and the internal node; a comparing circuit for comparing a divided voltage at the internal node with a reference voltage to generate a comparison signal; and an adjusting circuit for adjusting resistance of at least one of the first and second adjustable resistors according to the comparison signal.

Abstract: The connection intervals of N amplifier blocks 3-1 to 3-N to an input transmission line 1 increase with the distance from a signal input terminal RFin, and among the N amplifier blocks 3-1 to 3-N, the input capacitor 4 in an amplifier block 3-n connected to the input transmission line 1 at a more distant side from the signal input terminal RFin has a lower capacitance value Cn.

Abstract: A novel and useful transmitter (TX) architecture for ultra-low power (ULP) radios. An all-digital PLL employs a digitally controlled oscillator (DCO) having switching current sources to reduce supply voltage and power consumption without sacrificing phase noise and startup margins. It also reduces 1/f noise allowing the ADPLL after settling to reduce its sampling rate or shut it off entirely during direct DCO data modulation. A switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency. The transmitter has been realized in 28 nm CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy.

Abstract: In an example embodiment, an amplifier having high gain and high slew rate is provided and includes a pair of input transistors to which input voltage is applied, a pair of diode-connected loads coupled to the input transistors, at least one pair of current sources coupled to the diode-connected loads, and a bias control configured to turn off the at least one pair of current sources to enable high slew rate for the amplifier and to turn on the at least one pair of current sources to enable high gain for the amplifier. In specific embodiments, the current sources include transistors, the bias control controls a bias voltage to the current sources, and the bias voltage is driven to the supply voltage (VDD) to turn off the current sources.

Abstract: A fault-tolerant switching amplifier includes an inverter unit including N inverters, where N is a natural number, each of the N inverters including a plurality of switching elements and configured to perform switching ON or OFF of the switching elements based on a PWM signal inputted to the switching elements, thus switching an applied direct-current (DC) voltage, and to generate an output signal based on the switching and a switch unit including N switches respectively connected to output terminals of the N inverters, each of the N switches being configured to be short-circuited or open-circuited based on whether or not the corresponding one of the N inverters is in a normal operation condition. The output terminals of the N inverters are connected in series, such that output signals outputted from the inverters are combined to generate an amplified signal.

Abstract: One aspect of this disclosure is a transimpedance amplifier circuit with multiple resistive feedback loops can be implemented with multiple Kelvin sensing channels. A transimpedance amplifier and multiple Kelvin sensing channels can be implemented on a single die having multiple contacts, such as pins, for connecting multiple resistors to the Kelvin sensing channels. The Kelvin sensing channels can be implemented with T-junction switch networks in certain embodiments.

Abstract: Provided is a semiconductor integrated circuit including a pad Pd1 provided on one end side of a resistive element R1 externally provided, a pad Pd5 provided on a different end side of the resistive element R1; an operation amplifier A1, a signal line L11 wired between an output terminal of the operation amplifier A1 and the pad Pd1, a signal line L21 wired between an inverting input terminal of the operation amplifier A1 and the pad Pd5, a ESD protection element r11 provided to the signal line L11, and a signal line L31, through which a voltage signal of the pad Pd1 is transmitted. The signal line L31 is connected to the pad Pd1.

Abstract: An instrumentation amplifier includes first and second resistors for gain setting. The operational amplifiers within the instrumentation amplifier include selectively enabled current drive sources coupled to the amplifier output. The first and second resistors have variable resistances. A control circuit is configured to select the variable resistances of the first and second resistors to implement a fixed gain for the instrumentation amplifier and further selectively enable the current drive sources. The control circuit receives an indication of a downstream programmable gain (for example, from a downstream programmable gain amplifier). The variable resistances of the first and second resistors are selected to be scaled inversely with respect to the downstream programmable gain and the current drive sources are enabled proportionately with respect to the downstream programmable gain.

Abstract: An apparatus includes an input terminal to receive a radio frequency (RF) signal and to communicate the RF signal to a low noise amplifier (LNA) via an input signal path, and a capacitor attenuator coupled to the input terminal to attenuate the RF signal by a controllable amount and having a first portion controllable to include a used part configured on the input signal path and an unused part coupled between the input signal path and an AC reference node, and a second portion coupled between the LNA and the AC reference node.

Abstract: A method and an apparatus for reducing noise due to a path change of an audio signal output from a device are provided. The method includes determining an input period for canceling the noise by using a time point, at which the path change is sensed, as a reference, when sensing the path change of the audio signal; low-pass filtering the audio signal in the determined input period; and interpolating a first partial signal, which is the low-pass filtered audio signal in a first predetermined period that starts from a start time point of the determined input period, and a second partial signal, which is the low-pass filtered audio signal in a second predetermined period that ends at an end time point of the determined input period, within the determined input period.

Abstract: An impedance matching network includes a first terminal, a second terminal, and a reference potential terminal. The impedance matching network further includes a first shunt branch between the first terminal and the reference potential terminal, the first shunt branch including a capacitive element. The impedance matching network also includes a second shunt branch between the second terminal and the reference potential terminal, the second shunt branch including an inductive element. Furthermore, the impedance matching network includes a transmission line transformer with a first inductor path and a second inductor path, wherein the first inductor path connects the first terminal and the second terminal. An alternative impedance matching network includes a transformer and an adaptive matching network. The transformer is configured to transform an impedance connected to a first port so that a corresponding transformed impedance lies within a confined impedance region in a complex impedance plane.

Abstract: A novel and useful adaptive antenna tuner and associated calibration mechanism for passive adaptive antenna matching networks. The tuner is suitable for use with cellular antennas and in one embodiment uses MEMS based tunable devices. The tuner contains voltage and current sensors inserted before the antenna matching network. The sensed complex impedance generates one or more update control signals for the tuning algorithm which drives the MEMS-based tunable devices.

Abstract: A resonator includes a piezoelectric plate and interdigitated electrode(s). The interdigitated electrode includes a plurality of conductive strips disposed over a top surface of the piezoelectric plate. A two-dimensional mode of mechanical vibration is excited in a cross sectional plane of the piezoelectric plate in response to an alternating voltage applied through the interdigitated electrode. The two-dimensional mode of mechanical vibration is a cross-sectional Lamé mode resonance (CLMR) or a degenerate cross-sectional Lamé mode resonance (dCLMR).

Abstract: The invention concerns microelectromechanical resonators. In particular, the invention provides a resonator comprising a support structure, a doped semiconductor resonator suspended to the support structure by at least one anchor, and actuator for exciting resonance into the resonator. According to the invention, the resonator comprises a base portion and at least one protrusion extending outward from the base portion and is excitable by said actuator into a compound resonance mode having temperature coefficient of frequency (TCF) characteristics, which are contributed by both the base portion and the at least one protrusion. The invention enables simple resonators, which are very well temperature compensated over a wide temperature range.

Abstract: The invention provides a microelectromechanical resonator device comprising a support structure and a resonator manufactured on a (100) or (110) semiconductor wafer, wherein the resonator is suspended to the support structure and comprises at least one beam being doped to a doping concentration of 1.1*1020 cm?3 or more with an n-type doping agent and is being capable of resonating in a length-extensional, flexural resonance or torsional mode upon suitable actuation. In particular, the doping concentration and angle of the beam are chosen so as to simultaneously produce zero or close to zero second order TCF, and even more preferably zero or close to zero first and second order TCFs, for the resonator in said resonance mode, thus providing a temperature stable resonator.

Abstract: The invention relates to a microelectromechanical resonator device comprising a support structure and a semiconductor resonator plate doped to a doping concentration with an n-type doping agent and being capable of resonating in a width-extensional resonance mode. In addition, there is at least one anchor suspending the resonator plate to the support structure and an actuator for exciting the width-extensional resonance mode into the resonator plate. According to the invention, the resonator plate is doped to a doping concentration of 1.2*1020 cm?3 or more and has a shape which, in combination with said doping concentration and in said width-extensional resonance mode, provides the second order temperature coefficient of frequency (TCF2) to be 12 ppb/C2 or less at least at one temperature. Several practical implementations are presented.

Abstract: An acoustic wave device includes: a substrate; a piezoelectric film located on the substrate; a lower electrode and an upper electrode facing each other across at least a part of the piezoelectric film; a silicon oxide film located at an opposite side of at least one of the lower electrode and the upper electrode from the piezoelectric film; a non-oxygen-containing insulating film located between the at least one of the lower electrode and the upper electrode and the silicon oxide film; and an additional film located at an opposite side of the silicon oxide film from the non-oxygen-containing insulating film and made of a material different from a material of the silicon oxide film.

Abstract: A resistance element generator includes a reference current generation unit suitable for receiving a source reference current to generate first and second reference currents, a first resistance generation unit suitable for generating a first resistance value by using a first reference voltage and the first reference current, and outputting a first voltage corresponding to the formed first resistance value, and a second resistance generation unit suitable for generating a second resistance value by using a third reference voltage and the second reference current, and outputting a second voltage corresponding to the formed second resistance value.

Abstract: A circuit includes a transistor circuit including a first node, a second node, and a plurality of transistors coupled in parallel between the first node and the second node. The circuit further includes a drive circuit configured to switch on a first group of the plurality of transistors, the first group including a first subgroup and a second subgroup and each of the first subgroup and the second subgroup including one or more of the transistors. The drive circuit is further configured to switch off the first subgroup at the end of a first time period and switch off the second subgroup at a time instant before the end of the first time period.

Abstract: A dynamic rotary traveling wave oscillator circuit includes plurality of multi-output spot-advancing blocks (MOSABs) forming a main-loop and a plurality of multi-input spot-advancing blocks (MISABs) forming a sub-loop. Depending on a desired division ratio, a connection connects blocks on the MOSABs and MISABs to create the desired division ratio.

Abstract: A CML latch includes an input stage including input nodes to receive a differential input signal and output nodes to provide a differential intermediate output signal, and a negative output node to provide a negative side of the differential intermediate output signal, a negative resistance stage including an input node connected to a first voltage source and output nodes connected to the output nodes of the input stage, and a latch stage including input nodes connected to the output nodes of the input stage and output nodes to provide a differential output signal. The negative resistance stage increases a current gain of the input stage.

Abstract: A method for performing phase shift control in an electronic device and an associated apparatus are provided, where the method includes: obtaining a set of clock signals corresponding to a set of phases; and controlling a phase shift of an output signal of an oscillator by selectively mixing the set of clock signals into the oscillator according to a set of digital control signals, wherein the phase shift corresponds to the set of digital control signals, and the set of digital control signals carries a set of digital weightings for selectively mixing the set of clock signals. More particularly, the method may include: selectively mixing the set of clock signals into a specific stage of a plurality of stages of the oscillator according to the set of digital control signals.

Abstract: A load driving device 10 includes a temperature detector TD1 that sets a temperature difference detection signal dt_ot to active when a temperature difference Tdif between a temperature Ttr of an output transistor T1 and an ambient temperature becomes more than a reference temperature difference Tdref1, and sets an over temperature detection signal at_ot to active when the temperature Ttr of the output transistor T1 becomes higher than a reference temperature Tref1, a current limiter IL1 that limits a GS current of the output transistor T1 when any one of the detection signals becomes active, and the output transistor T1 that turns off regardless of an external input signal IN when any one of the detection signals becomes active.

Abstract: Apparatus comprises a switch feature configured to restrict an electrical signal transmitted from a peripheral device, and received through an electrical contact, from being transferred to one of first and second circuit modules coupled to the electrical contact, depending on the voltage amplitude of the electrical signal.

Abstract: Aspects disclosed herein describe a keeper circuit that adapts to variations in the fabrication process used to manufacture a dynamic circuit. The different characteristics of the circuit elements may cause a keeper circuit to behave in an unintended manner. In one example, a logical state of the dynamic circuit may be erroneously changed because of a strong (i.e., leaky) NMOS transistor in a pull down or discharge path. An adaptive keeper circuit, however, is designed to prevent such unintended behavior regardless of any change in the characteristics of the circuit elements in the dynamic circuit. The adaptive keeper circuit matches the behavior of the pull down path and prevents the pull down path from erroneously changing the logical state stored by the dynamic circuit.

Abstract: Presented are systems and methods that allow hardware designers to protect valuable IP and information in the hardware domain in order to increase overall system security. In various embodiments of the invention this is accomplished by configuring logic gates of existing logic circuitry based on a key input. In certain embodiments, a logic function provides results that are dependent not only on input values but also on an encrypted logic key that determines connections for a given logic building block, such that the functionality of the logic function cannot be determined by reverse engineering. In some embodiments, the logic key is created by decrypting a piece of data using a secret decryption key. Advantages of automatic encryption include that existing circuitry need not be re-implemented or re-built, and that the systems and methods presented are backward compatible with standard manufacturing tools.

Abstract: A level shift circuit includes: a latch circuit (Q5, Q6, Q7, Q8) including first (Q5, Q7) and second (Q6, Q8) inverter circuits; a first input MOS transistor (Q1) operating in accordance with an input signal; a second input MOS transistor (Q2) operating in accordance with an inversion signal of the input signal; and a current-voltage control MOS transistor (Q9). The latch circuit (Q5, Q6, Q7, Q8) outputs a voltage having been converted from the input voltage in level. Each of the first and second input MOS transistors (Q1, Q2) receives the input signal at its gate terminal, and drives the latch circuit (Q5, Q6, Q7, Q8) in accordance with the input signal. The current-voltage control MOS transistor (Q9) is provided between the input MOS transistor (Q1, Q2) and the latch circuit (Q5, Q6, Q7, Q8), and is driven in accordance with an inversion operation of the latch circuit by receiving an input of the control voltage at its gate terminal.

Abstract: A control device for a clock generation circuit that generates a clock signal based on a reference signal from an outside, the control device includes: a storage device that stores frequency correction information for the clock signal according to a temperature condition of the clock generation circuit; and a processor that controls a frequency of the clock signal generated by the clock generation circuit under a second temperature condition, based on first and second frequency correction information according to a first temperature condition at first and second time points in the storage device.

Abstract: A transmission circuit includes: a shift register configured to shift, in synchronization with a first clock signal, input parallel data within a plurality of flip-flop circuits; a control circuit configured to output a second clock signal of a phase in accordance with a phase of the first clock signal; a selector configured to select any one of the input parallel data and pieces of output parallel data of the plurality of flip-flop circuits; and a conversion circuit configured to convert, in synchronization with the second clock signal, the parallel data selected by the selector into pieces of serial data, in which the control circuit outputs a selection signal to the selector, in accordance with a deviation amount of the detected phase of the first clock signal.

Abstract: A frequency detection circuit includes: a first comparison circuit configured to output a first comparison result produced by comparison between a second threshold value higher than a first threshold value; a second comparison circuit configured to output a second comparison result produced by comparison between a third threshold value lower than the first threshold value; a third comparison circuit configured to output a third comparison result produced by comparison between the input data, and the first threshold value at second timing of a second clock; a phase detector configured to determine in which one of the areas an edge of the input data is positioned among the three areas produced by dividing a phase in a one-bit width time into three areas; and a phase rotation detector configured to detect a rotation direction of the phase based on a change of a detection result in the phase detector.

Abstract: A spread spectrum clock generator includes a phase comparator that compares a reference clock with a feedback clock, a low-pass filter that passes a predetermined low-frequency component, a phase lock loop that includes a voltage-controlled oscillator generating an output clock whose frequency corresponds to the filtered signal, a triangular wave controller that generates a triangular wave signal for frequency-modulating the spread spectrum clock based on the output clock, a delay controller that generates the feedback clock by controlling delay of the output clock based on the triangular wave signal, a first counter that counts the output clock and output a first count value, a second counter that counts the reference clock and output a second count value, and a phase error correction circuit that compares the first count value with the second count value and corrects phase error of the output clock.

Abstract: A novel and useful digitally controlled injection-locked RF oscillator with an auxiliary loop. The oscillator is injection locked to a time delayed version of its own resonating voltage (or its second harmonic) and its frequency is modulated by manipulating the phase and amplitude of injected current. The oscillator achieves a narrow modulation tuning range and fine step size of an LC tank based digitally controlled oscillator (DCO). The DCO first gets tuned to its center frequency by means of a conventional switched capacitor array. Frequency modulation is then achieved via a novel method of digitally controlling the phase and amplitude of injected current into the LC tank generated from its own resonating voltage. A very linear deviation from the center frequency is achieved with a much lower gain resulting in a very fine resolution DCO step size and high linearity without needing to resort to oversampled noise shaped dithering.

Abstract: An analog-digital conversion system includes an analog-digital converter; and a preamplifier circuit which is provided in the previous stage of the analog-digital converter and differentially amplifies an input analog signal. In the preamplifier circuit, an offset voltage and/or a noise occurs and/or is mixed. The preamplifier circuit outputs two types of analog amplified differential signals where a phase is inverted only with respect to the offset voltage and/or the noise. The analog-digital converter has an averaging circuit which averages the two types of analog amplified differential signals for each clock cycle of sampling preceding an analog-digital conversion and outputs a digital signal based on the differential signal averaged by the averaging circuit.

Abstract: A circuit and method compensates for comparator offset in a successive approximation register analog-to-digital converter. The circuit includes a multiplexed sampler to sample either a common mode voltage or an input signal. The sampled signal is added to a conversion voltage and an offset correction voltage and input to a comparator. The comparator determines a polarity of deviation of the sum of the sampled signal, conversion voltage and off-set correction voltage. Based on the polarity, the offset correction voltage and the conversion voltage are alternately subjected to a successive approximation process to compensate for the offset of the sum from the sampled input signal or sampled common voltage signal.

Abstract: Disclosed are methods and systems for significantly compressing sparse multidimensional ordered series data comprised of indexed data sets, wherein each data set comprises an index, a first variable and a second variable. The methods and systems are particularly suited for compression of data recorded in double precision floating point format.