Abstract: The invention discloses a method for using a shared apparatus in a device capable of running two operating systems, which includes using a first application in a first operating system to communicate with the share apparatus, and when the first operating system is switched to a second operating system, sending associated information on the shared apparatus to a second application in the second operating system so that the second application can use the associated information to communicate with the shared apparatus.

Abstract: A tool for autoscaling applications in a shared cloud resource environment. The tool registers, by one or more computer processors, one or more trigger conditions. The tool initiates, by one or more computer processors, a scaling event based, at least in part, on at least one of the one or more trigger conditions. The tool determines, by one or more computer processors, a scaling decision for the scaling event based, at least in part, on one or more scaling rules related to the one or more trigger conditions.

Abstract: Provided are a message interaction processing method and device. The method includes: a first buffer with a preset size is applied for to a Central Processing Unit (CPU) and/or a chip; and message interaction is performed between the CPU and the chip through the first buffer, wherein the first buffer is used for storing at least two messages. By the disclosure, the problem that frequent switching between states may cause high resource overhead and low message transmission efficiency under the condition of large message interaction between the CPU and the chip is solved, and the effect of remarkably improving message sending and receiving efficiency and performance of network equipment is further achieved.

Abstract: A target device, such as a storage controller, may host an interface that manages objects, such as storage objects (e.g., logical unit numbers (LUNs), volumes, etc.), maintained by the storage controller. Accordingly, an object on the storage controller may be modeled as an object model, such as an object oriented library, based upon modeling information mined from the storage controller. The object model may be automatically generated, such as by discovering the interface to the object using available information in a command line interface (CLI) and/or an XML file (e.g., an XML help file). In this way, the object model may use hosted/exported interfaces to manage the object.

Abstract: Technology is disclosed for determining high availability readiness of a distributed computing system (“system”). A confidence measure (CM) can be computed for a particular controller in the system to determine whether a takeover by the particular controller from a first controller would be successful. The CM can be a percentage value. A CM of 0% indicates that a takeover would be a failure, which results in loss of access to data managed by the first controller. A CM of 100% indicates a successful takeover with no performance impact on the system. A CM between 0% and 100% indicates a successful takeover but with a performance impact. The CM can be computed based on events occurring in the system, e.g., veto and non-veto events. The CM is computed as a function of various weights and/or indices associated with the veto events and/or non-veto events.

Abstract: A system and method for correlating asynchronous operations via an operation identifier comprises receiving an originating operation from a first system that indicates a change in the first system and generating a first message with respect to the originating operation. The first message is associated with the operation identifier. The system and method further propagates the first message to a second system, which causes a subsequent operation being associated with the operation identifier to be performed by the second system, and correlates the originating operation and the subsequent operation via the operation identifier.

Abstract: A user device having a plurality of modules for implementing one or more use cases, maps one or more sensor outputs to a use case based on sensor outputs obtained during a hang/reset state of the user device during the use case. Each of the one or more sensor outputs is associated with one of the plurality of modules. The user device also maps one or more actions to each sensor output mapped to the use case. The one or more actions affect a change in an operating parameter of the module associated with the sensor output during a hang/rest state of the user device during the use case. The one or more actions also affect a corresponding change in the sensor output mapped to the use case.

Abstract: Disclosed herein are method, system and computer program product embodiments for improving the verification process of a system on chip (SoC). An embodiment operates by employing an active interconnect (AIC) between a processing subsystem (e.g., a central processing unit or CPU) and a plurality of peripherals, wherein the processing subsystem is linked to a plurality of applications via a plurality of drivers, and implementing a common set of software codes by at least one of the applications for a software development process and a hardware verification process. The AIC includes a plurality of communication protocols. During the software development process, the AIC configures at least one of the communication protocols to not enforce a timing limitation on one or more transactions between the processing subsystem and at least one of the peripherals, and a high-level programming language model is used for the peripherals.

Abstract: Provided are a system and method for detecting and predicting anomalies based on analysis of time-series data. According to an embodiment of the present disclosure, an abnormality detecting and predicting system includes a database configured to store past case data related to a state of a monitored object; a data collector configured to collect time-series status information of the monitored object; an abnormality detector configured to compare the status information with an abnormality detecting reference in a preset detecting interval and detect an occurrence of an abnormality of the monitored object; a similar case selector configured to select a similar case having a highest degree of similarity to the status information among the past case data when the occurrence of an abnormality is detected by the abnormality detector; and a predictor configured to predict proliferation or diminishing of a detected abnormality using the similar case and an abnormality proliferation predicting reference.

Abstract: A system and method for correlating asynchronous operations via an operation identifier comprises receiving an originating operation from a first system that indicates a change in the first system and generating a first message with respect to the originating operation. The first message is associated with the operation identifier. The system and method further propagates the first message to a second system, which causes a subsequent operation being associated with the operation identifier to be performed by the second system, and correlates the originating operation and the subsequent operation via the operation identifier.

Abstract: A technique includes accessing error information generated in response to memory errors of a memory device. The error information generated in response to the memory errors of the memory device may then be determined as indicative of a row hammer error for the memory device.

Abstract: A management system manages a computer system including multiple monitoring-target devices. A storage device of the management system stores a general rule, general plan information, unresolved information, and configuration information. A control device of the management system creates multiple expanded rules based on the general rule and the configuration information, and if an event related to any of the multiple monitoring-target devices has occurred, identifies, based on the multiple expanded rules, a first conclusion event constituting a candidate for the cause of the occurred event, creates, based on the general plan information, one or more expanded plans, which are recovery plans that can be implemented if the first conclusion event is a cause, identifies an unresolved event based on the unresolved information, identifies a risk site based on the identified unresolved event, and displays data showing the first conclusion event, expanded plan, and risk site.

Abstract: Methods and systems for modular system awareness in virtualized information handling systems (IHSs) include generating, by a chassis management controller (CMC), dependency information indicating which ones of modular IHSs included in a chassis are dependent on individual shared components in the chassis. When a fault occurs at one of the shared components, the CMC may determine, using the dependency information, which particular ones of the modular IHSs are operationally dependent on the fault. The CMC may send information indicative of the fault and of the dependent modular IHSs to a virtual machine manager, which may generate a ranking of virtual machines. The virtual machine manager may use the rankings to make migration decisions for virtual machines among modular IHSs.

Abstract: A computer architecture addresses intermittent memory faults by exploiting redundancy inherent in a hierarchical memory structure, for example, as data moves through various cache levels and registers before use by the processor. Accesses to data from faulted memory areas is diverted to a secondary memory structure holding that data and the secondary memory structure is flagged to increase the persistence of the stored data used for patching against normal updating policies.

Abstract: For single-level cell flash memories and multi-level cell flash memories, different operations can be performed according to their stability when an abnormal status is terminated. Specifically, for the multi-level cell flash memories, when the abnormal status is terminated, a now physical block is used to proceed with write operation, and the previous physical block(s) would not be written any more. On the contrary, for the single-level cell flash memories, when the abnormal status is terminated, the controller needs to perform corresponding operations on the last physical page of the previous physical block(s).

Abstract: A database server includes logic that is operable to monitor and analyze at least events occurring within an environment of the database server and/or execution errors generated by the database server in order to detect whether a problem condition exists. The database server further includes logic that is operable to send one or more commands to a database driver of a client that is communicatively connected to the database server, the one or more commands specifying one or more actions to be taken by the database driver in response to the existence of the problem condition. The database driver includes logic that is operable to receive the one or more commands from the database server and logic that is operable to cause the one or more commands to be executed.

Abstract: A storage module and method for datapath bypass are disclosed. In one embodiment, a storage module begins to perform a read operation that reads a set of code words from the memory and attempts to perform an error detection and correction operation on one of the read code words. In response to determining that the code word has an uncorrectable error, the storage module reads the other code words in the set but bypasses the error detection and correction operation on those other code words. The code word that had the uncorrectable error and the other code words are re-read, wherein at least the code word with the uncorrectable error is re-read with a different read condition. The storage module then attempts to perform the error detection and correction operation on the re-read code words. Other embodiments are provided.

Abstract: In at least one embodiment, a read operation in a data storage system having lossy storage media includes fetching target data of the read operation from a lossy storage device into a buffer, transferring the target data from the buffer to an external controller external to the lossy storage device via a communication bus, performing error location processing on the target data during the transferring of the target data, communicating error location information regarding at least one error location to error repair logic via the communication bus, the error repair logic repairing the at least one error in the target data using the error location information, and the external controller causing the target data as repaired to be transmitted toward a destination. By deserializing the suboperations comprising the read operation, read latency can be reduced.

Abstract: A data storage device including a flash memory and a controller. The flash memory includes a plurality of chips, each of the chips includes a plurality of pages, the pages are arranged to assemble into a super block, the pages of the super block are numbered 0˜X from top to bottom of the super block, the pages with number 0˜Y?1 constitute a data area, and the pages with numbers Y˜X constitute a RAID parity area. The controller corrects data of the data area according to data of the RAID parity area when the data in the data area cannot be successfully read.

Abstract: The inventive concepts relate to an operation method of an error correction decoder correcting an error of data read from a nonvolatile memory. The operation method may include receiving the data from the nonvolatile memory, performing a first error correction with respect to the received data in a simplified mode, and performing, when the first error correction fails in the simplified mode, a second error correction with respect to the received data in a full mode. When the first error correction of the simplified mode is performed, a part of operations of the second error correction of the full mode may be omitted.

Abstract: Processor register protection management is disclosed. In embodiments, a method of processor register protection management can include determining a sensitive logical register for executable code generated by a compiler, generating an error-correction table identifying the sensitive logical register, and storing the error-correction table in a memory accessible by a processor. The processor can be configured to generate a duplicate register of the sensitive logical register identified by the error-correction table.

Abstract: A streams manager clones a portion of a primary flow graph to a virtual machine with a buffer to assure no data is lost if the corresponding portion of the primary flow graph fails. The buffer can be on the input of the cloned portion or on the output of the cloned portion. Cloning a portion of a primary flow graph with a buffer assures no data is lost when the corresponding portion of the primary flow graph fails. When the primary flow graph recovers from the failure, the processing may be switched back to the primary flow graph, which causes the buffer to begin buffering once again.

Abstract: Techniques are described herein which minimize the impact of virtual machine snapshots on the performance of virtual machines and hypervisors. In the context of a volume snapshot which may involve (i) taking virtual machine snapshots of all virtual machines associated with the volume, (ii) taking the volume snapshot, and (iii) removing all the virtual machine snapshots, multiple virtual machine snapshots may be created in parallel. In the process of creating virtual machine snapshots, a storage system may determine which snapshots to create in parallel. The storage system may also prioritize snapshots from certain hypervisors in order to avoid the problem of “starvation”, in which busy hypervisors prevent less busy hypervisors from creating snapshots. The techniques described herein, while mainly described in the context of snapshot creation, are readily applied to snapshot removal.

Abstract: Managing a virtual machine snapshot in O(1) time by initially storing data from a virtual machine executing under a host operating system, to a first host operating system managed data block and creating a first pointer that points to the first host operating system managed data block and associates the virtual machine to the data stored in the first host operating system managed data block. A first value, associated with the first host operating system managed data block, is initialized indicating the number of pointers created to associate the virtual machine to the first host operating system managed data block. Receiving, by the computer host operating system, a request to create a snapshot of the virtual machine creates a second pointer replicating the first pointer, and increments, by the computer host operating system, the first value associated with the first host operating system managed data block.

Abstract: Data integrity is maintained during failed communications between a member node of a primary cluster and a backup cluster by assigning an assisting member node to run an assisting process that transmits data entered into the member node to the backup cluster. In this way, a replicated database is maintained during a partial communication failure between the primary cluster and the backup cluster.

Abstract: Techniques for computer system recovery which remotely restore a default partition to a recent state even when an operating system is functioning abnormally. In an example embodiment, a service center computer establishes a first network connection to a monitored computer system. The service center computer configures the monitored computer system to boot from a bootable image file in the monitored computer system and reboots the monitored computer system into an alternate operating system environment of the bootable image file. The service center computer establishes a second network connection to the monitored computer system to restore a recent backup image of the default partition from a diagnostic partition to a default partition. The service center computer establishes a third network connection to the monitored computer system and reboots the monitored computer system to the default partition.

Abstract: A streams manager clones a portion of a primary flow graph to a virtual machine with a buffer to assure no data is lost if the corresponding portion of the primary flow graph fails. The buffer can be on the input of the cloned portion or on the output of the cloned portion. Cloning a portion of a primary flow graph with a buffer assures no data is lost when the corresponding portion of the primary flow graph fails. When the primary flow graph recovers from the failure, the processing may be switched back to the primary flow graph, which causes the buffer to begin buffering once again.

Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

Abstract: Techniques for selectively utilizing memory available in a redundant host system of a cluster are described. In one embodiment, a cluster of host systems, with at least one redundant host system, with each host system having a plurality of virtual machines with associated virtual machine (VM) reservation memory is provided. A portion of a data store is used to store a base file, the base file accessed by all the plurality of virtual machines. A portion of the memory available in the redundant host system is assigned as spare VM reservation memory. A copy of the base file is selectively stored in the spare VM reservation memory for access by all the plurality of virtual machines.

Abstract: In computing systems that provide multiple computing domains configured to operate according to an active-standby model, techniques are provided for intentionally biasing the race to gain mastership between competing computing domains, which determines which computing domain operates in the active mode, in favor of a particular computer domain. The race to gain mastership may be biased in favor of a computing domain operating in a particular mode prior to the occurrence of the event that triggered the race to gain mastership. For example, in certain embodiments, the race to mastership may be biased in favor of the computing domain that was operating in the active mode prior to the occurrence of an event that triggered the race to gain mastership.

Abstract: A computer-implemented method for managing storage devices in a storage subsystem having an array of storage devices, according to one embodiment, includes determining that at least one storage device in the array of storage devices has failed. Storage device characteristics of the failed storage device are compared with storage device characteristics of each of a plurality of candidate devices, and an attempt is made to identify a first candidate storage device having storage device characteristics that match the storage device characteristics of the failed storage device. A second candidate storage device having storage device characteristics most similar to the storage device characteristics of the failed storage device is identified in response to not identifying a candidate device that matches the failed storage device.

Abstract: The invention introduces a POST (power-On-Self-Test) debugging method, executed by a processing unit, which contains at least the following steps. A phase number indicative of a current POST phase is set. A driver is selected from a scheduled queue. A GUID (Globally Unique Identifier) of the driver is obtained. The phase number and the GUID are stored or output, so as to recognize the phase of the driver being interrupted upon a break point of the driver. After that, the driver is executed.

Abstract: Systems, methods, computer readable media and apparatuses for executing one or more test cases associated with verifying a functionality of a computer system, software application, or the like are presented. The test cases may be received by a system and may be prioritized and integrated into an existing queue of test cases based on the determined priority. In some examples, a configuration for a computing device to execute the test cases may be identified and transmitted to one or more computing devices available to or scheduled to execute the test cases. Accordingly, the test cases may be dynamically allocated to available computing devices for execution. In some arrangements, one or more reports may be generated and/or transmitted reporting the results of the execution of the test cases. The reports may be accessible via the system and/or may be transmitted to a user via, for example, an email message.

Abstract: One or more passive collectors watch a system's real activity confirming normal responses to requests. This passive monitor may have other purposes such as measuring real performance, and determining normal completion of requests which provides complete and accurate performance and availability of the monitored system. When the passive monitoring no longer detects actual activity, the preferred embodiment automatically triggers the execution of synthetic activity which simulates the real usage of the system. This active monitoring determines the state of the usage of the system. If the simulated use of the system results in an abnormal completion of the activity, an outage is recorded. The simulation occurs on a regular interval until the passive monitor sees real normal activity.

Abstract: Methods and systems for reporting performance data for application programming interfaces (APIs) are provided. A method includes receiving a subscription request from a subscriber for a particular API of a plurality of APIs, and monitoring performance of the particular API for a predetermined event that includes a change in at least one of performance status for the particular API and one or more various measurements of performance of the particular API. The method further includes comparing the predetermined event to a table or database of information that includes notification and alert rules for the particular API that specify notification policies for various predetermined events, and when the predetermined event matches at least one of the notification and alert rules, sending, by the computer system, a notification or alert to the subscriber based on the notification policy for the at least one of the notification and alert rules.

Abstract: Systems, methods, and computer program products to discover weak consistency errors in an application, by executing, by a debugger, a first thread of the application, by, determining that a first instruction in the first thread specifies to store a first value at a first memory address, setting a current value stored in the first memory address as an old value for the first memory address in a container for the first thread, executing the first instruction to store the first value at the first memory address, and setting the first value as a new value for the first memory address in the container for the first thread. The debugger then executes a second thread of the application, by restoring old values in the containers for all other threads and restoring a new value for each memory address specified in a container for the second thread to its respective memory address.

Abstract: Methods to discover weak consistency errors in an application, by executing, by a debugger, a first thread of the application, by, determining that a first instruction in the first thread specifies to store a first value at a first memory address, setting a current value stored in the first memory address as an old value for the first memory address in a container for the first thread, executing the first instruction to store the first value at the first memory address, and setting the first value as a new value for the first memory address in the container for the first thread. The debugger then executes a second thread of the application, by restoring old values in the containers for all other threads and restoring a new value for each memory address specified in a container for the second thread to its respective memory address.

Abstract: A plurality of processing elements having stream operators and operating on one or more computer processors receive a stream of tuples. A first stream operator adds a first attribute to a tuple received on a first port of the first stream operator. The first attribute indicates the first port and the first stream operator. A second stream operator adds a second attribute to a tuple received on a first port of the second stream operator. The second attribute indicates the first port of the second stream operator and the second stream operator. It is determined whether a debug tuple has been received by a third stream operator. A debug tuple is a tuple that includes the first and second attributes. An operation, such as halting execution or incrementing a count of debug tuples, is performed when it is determined that a debug tuple has been received.

Abstract: The system includes a receiving module configured to receive a first set of data and a second set of data, wherein the first set of data comprises one or more high quality objects, and one or more ungraded objects, wherein the second set of data comprises one or more ungraded objects, an identification module configured to identify the one or more high quality objects, an extraction module is configured to extract one or more features from each high quality object of the one or more high quality objects, a building module is configured to build a predictive model based on the one or more features extracted for the each high quality object, a comparison module configured to compares the one or more ungraded objects and the one or more high quality objects, and an assessment module configured to score the one or more ungraded objects.

Abstract: System and method for validating a program under a specified model of computation. The model of computation may be related to the synchronous statechart model of computation. A program may be received that specifies a plurality of operations using a variable within a logical tick such that the variable has multiple values within the logical tick. The program may be statically analyzed according to a specified model of computation that specifies program execution based on logical ticks, which may include determining that the program has deterministic semantics that specify deterministic results for each logical tick during execution of the program, including specifying deterministic results of the plurality of operations performed within the logical tick. The program may be validated in accordance with the specified model of computation in response to the determining. Such techniques may allow validation of a larger set of programs than conventional models while maintaining deterministic results.

Abstract: A system stores a plurality of chapters, a plurality of sections each associated with a chapter, a plurality of control points each associated with a section, a plurality of assessment points each associated with a control point, and a plurality of attributes each associated with an assessment point. The system retrieves application information corresponding to an application. The system determines that one of the plurality of stored attributes applies to the application and assigns an attribute score to the application based on the determination. The system calculates various scores based on the attribute score and other scores including, an assessment point score, a control point score, a section score, and a chapter score. Based at least in part upon at least one of these scores, the system determines a strength of the application.

Abstract: A data analysis system processes data generated by instrumented software. The data analysis system receives data streams generated by instances of instrumented software executing on systems. The data analysis system also receives metadata describing data streams. The data analysis system receives an expression based on the metadata. The data analysis system receives data of data streams for each time interval and computes the result of the expression based on the received data values. The data analysis system repeats these steps for each time interval. The data analysis system may quantize data values of data streams for each time interval by generating an aggregate value for the time interval based on data received for each data stream for that time interval. The data analysis system evaluates the expression using the quantized data for the time interval.

Abstract: The technologies described herein use a statistical test to determine whether differences between data sets of buckets in a bucket test, such as differences between averages of two buckets (e.g., differences between means of two buckets), are directionally larger than a predetermined or preset minimum threshold value. The statistical test may also provide an extension to specify the minimum threshold value as a percentage. Also, described herein are techniques for estimating different control variables of a bucket test, such as estimating minimum bucket size to provide sufficient statistical power with use of the minimum threshold value.

Abstract: Interactions with a particular graphical user interface (GUI) of a software system are caused to be recorded and a particular one of the interactions is identified as an interaction with a particular GUI element of the GUI. A particular type of GUI element corresponding to the particular GUI element is determined and at least a portion of an instruction is generated for inclusion in a test of the software system, the instruction referencing the particular GUI element as an instance of the particular type of GUI element.

Abstract: System and method for validating a program under a specified model of computation. The model of computation may be related to the synchronous statechart model of computation. A program may be received that specifies a plurality of operations using a variable within a logical tick such that the variable has multiple values within the logical tick. The program may be statically analyzed according to a specified model of computation that specifies program execution based on logical ticks, which may include determining that the program has deterministic semantics that specify deterministic results for each logical tick during execution of the program, including specifying deterministic results of the plurality of operations performed within the logical tick. The program may be validated in accordance with the specified model of computation in response to the determining. Such techniques may allow validation of a larger set of programs than conventional models while maintaining deterministic results.

Abstract: Systems and methods for preparing an application testing environment and for executing an automated test script in an application testing environment are disclosed. According to an aspect, a method includes providing graphical user interface (GUI) test automation objects. The method also includes classifying each of the GUI test automation objects as one of a test essential object and a test navigation object. Further, the method includes serializing the GUI test automation objects classified as a test navigation object for subsequent testing in a testing environment.

Abstract: Embodiments of the present disclosure provides a memory-efficient mechanism for identifying memory blocks with a low wear count. More particularly, embodiments of the present disclosure provides a mechanism for identifying a memory block whose wear count is within the bottom p % of all wear counts associated with memory blocks in a storage system. If a memory controller always performs the garbage collection operation on a memory block whose wear count is within the bottom p % of all wear counts, then the memory controller is expected to utilize the remaining memory blocks (e.g., memory blocks whose wear count is within the upper (100?p) % of all wear counts) efficiently and level the wear count of at least the remaining memory blocks.

Abstract: One aspect of the technology is a memory device, which comprises a plurality of page buffers and control circuitry. Different page buffer circuits in the plurality of page buffer circuits are coupled to different bit lines in a plurality of bit lines in a memory array. The control circuitry is responsive to a program command to program multiple cells in the memory array, by setting, via the plurality of page buffer circuits, different target voltages at a same time for the different bit lines coupled to the multiple cells.

Abstract: Methods and systems for managing caching mechanisms in storage systems are provided where a global cache management function manages multiple independent cache pools and a global cache pool. As an example, the method includes: splitting a cache storage into a plurality of independently operating cache pools, each cache pool comprising storage space for storing a plurality of cache blocks for storing data related to an input/output (“I/O”) request and metadata associated with each cache pool; receiving the I/O request for writing a data; operating a hash function on the I/O request to assign the I/O request to one of the plurality of cache pools; and writing the data of the I/O request to one or more of the cache blocks associated with the assigned cache pool. In an aspect, this allows efficient I/O processing across multiple processors simultaneously.

Abstract: The present disclosure relates to apparatus, systems, and methods that implement a less-recently-used data eviction mechanism for identifying a memory block of a cache for eviction. The less-recently-used mechanism can achieve a similar functionality as the least-recently-used data eviction mechanism, but at a lower memory requirement. A memory controller can implement the less-recently-used data eviction mechanism by selecting a memory block and determining whether the memory block is one of the less-recently-used memory blocks. If so, the memory controller can evict data in the selected memory block; if not, the memory controller can continue to select other memory blocks until the memory controller selects one of the less-recently-used memory blocks.