Abstract: In a semiconductor device, a heater is formed on a surface of a cap chip, and a first temperature sensor and a second temperature sensor are formed on a surface of a base chip. The cap chip and the base chip are laminated through a connection member such that the surfaces oppose to each other. The position of the heater is different from the positions of the temperature sensors in a direction of the lamination. The heater in the cap chip contacts bumps directly.

Abstract: Provided are a superconducting accelerometer, an acceleration measurement device, and an acceleration measurement method. The superconducting accelerometer includes a test mass including a rod-shaped body part, a disc-shaped coupling part connected to the body part, the test mass being made of a superconductor; a solenoid levitation coil disposed to surround a portion of the body part and adapted to magnetically levitate the test mass, the solenoid levitation coil being made of a superconductor; a measurement superconductor coil disposed at at least one side of an upper portion and a lower portion of the coupling part; and a SQUID sensor adapted to detect current depending on variation of a distance between the test mass and the measurement superconductor coil.

Abstract: An inertial sensor having a body with an excitation coil and a first sensing coil extending along a first axis. A suspended mass includes a magnetic-field concentrator, in a position corresponding to the excitation coil, and configured for displacing by inertia in a plane along the first axis. A supply and sensing circuit is electrically coupled to the excitation coil and to the first sensing coil, and is configured for generating a time-variable flow of electric current that flows in the excitation coil so as to generate a magnetic field that interacts with the magnetic-field concentrator to induce a voltage/current in the sensing coil. The integrated circuit is configured for measuring a value of the voltage/current induced in the first sensing coil so as to detect a quantity associated to the displacement of the suspended mass along the first axis.

Abstract: A resistive element includes a resistive region in a semiconductor substrate, a first contact structure and a second contact structure. The semiconductor substrate includes a first main surface area. The resistive region extends in a lateral direction parallel to the main surface area and in a vertical direction perpendicular to the main surface area, and includes a first piezo-resistive coefficient for a current flow in the lateral direction and a second piezo-resistive coefficient for a current flow in the vertical direction. The first contact structure contacts a portion of a first face of the resistive region and the second contact structure contacts a portion of a second face of the resistive region. The resistive element generates a current flow distribution within the resistive region having a lateral component and a vertical component that results in a piezo-resistive coefficient of the resistive element.

Abstract: A circuit arrangement of a sensor-triggered control system in a safety critical application with a digital signal processor (DSP) is provided. The DSP calculates a first position or attitude from position or attitude signals generated by a sensor. The first position or attitude meets a predetermined requirement to be accurate and unambiguous. A signal conditioning circuit reduces information content of the position or attitude signals to generate reduced position or attitude signals. A position and attitude calculation circuit determiners a second position or attitude based on the reduced position or attitude signals, which does not meet the predetermined requirement. A control unit compares the first position or attitude with the respective second position or attitude to generate a difference and determines whether the difference is within a predetermined scope of accuracy. If the determination of the control unit is negative, a sensor fault signal is outputted.

Abstract: An improved mode of AFM imaging (Peak Force Tapping (PFT) Mode) uses force as the feedback variable to reduce tip-sample interaction forces while maintaining scan speeds achievable by all existing AFM operating modes. Sample imaging and mechanical property mapping are achieved with improved resolution and high sample throughput, with the mode workable across varying environments, including gaseous, fluidic and vacuum.

Abstract: A “Theta” angle adjustment tool is made of a solid parallelepiped and adjusting screw, that allows the wafer probes to be fastened to the auxiliary equipment under correcting “Theta” angles. The procedure consists of loosening the probe and pressing hard on the tool to force the probe to adjust to the intended slope (“Theta”) and then fastening the probe under pressure against the tool and chuck surface. Following that the marks left when the probe tips touch the wafer are assessed and corrective action is taken regarding “Theta misalignment”.

Abstract: A probe card 10 includes a first probe 11 configured to come into electric contact with an emitter electrode of a power device D; a block-shaped first connecting terminal 12 to which the first probe 11 is connected; a second probe 13 configured to come into electric contact with a gate electrode of the power device D; a block-shaped second connecting terminal 14 to which the second probe 13 is connected; a contact plate 15 configured to come into electric contact with a collector electrode of the power device D; and a block-shaped third connecting terminal 16 fixed to the contact plate 15. Further, the first connecting terminal 12, the second connecting terminal 14 and the third connecting terminal 16 electrically come into direct contact with corresponding connection terminals of a tester, respectively.

Abstract: A current applying device in which a contact electrode is destroyed firstly when a large current is applied in the event of failure. A probe device is configured by serially connecting a contact body that is to be in contact with the surface of a power semiconductor to apply a current and a pressing body assembly that presses the contact body so as to apply the current to the power semiconductor and is configured so that, when the pressing body power applied to the pressing body assembly is smaller than the withstand power of the pressing body assembly, the contact body power applied to the contact body is larger than the withstand power of the contact.

Abstract: A contactor including a bellows body, a fixed portion connected to one end of the bellows body, a movable portion connected to the other end of the bellows body, and a movable touch piece that extending from at least one side edge along the bellows body, where the movable portion is configured to be depressed to compress the bellows body and to bring a movable contact point, located at a free end of the movable touch piece, into contact with the fixed portion.

Abstract: A test system including an embodiment having a sensor array adapted to test one or more devices under test in learning modes as well as evaluation modes. An exemplary test system can collect a variety of test data as a part of a machine learning system associated with known-good samples. Data collected by the machine learning system can be used to calculate probabilities that devices under test in an evaluation mode meet a condition of interest based on multiple testing and sensor modalities. Learning phases or modes can be switched on before, during, or after evaluation mode sequencing to improve or adjust machine learning system capabilities to determine probabilities associated with different types of conditions of interest. Multiple permutations of probabilities can collectively be used to determine an overall probability of a condition of interest which has a variety of attributes.

Abstract: A semiconductor die with an array of contacts, where at least two contacts in adjacent positions have the same data signal during testing operations with a test probe. The adjacent contacts of the cluster allow the use of a larger test probe tip and/or greater tolerance on test probe tip alignment during testing operations.

Abstract: A method of cleaning needles of a probe card in a test system includes mounting the probe card, which has a plurality of device under tests (DUTs) and needles, in a card mounting part. The DUTs and needles are scanned using a camera positioned in the test system to provide a scan result. A laser beam is focused on at least one of the needles based on the scan result and the laser beam is irradiated on the at least one of the needles to clean the at least one of the needles.

Abstract: The present invention relates to current measurement apparatus 100. The current measurement apparatus 100 comprises a measurement arrangement 110, 114 which is configured to be disposed in relation to a load 108 which draws a current signal, the measurement arrangement being operative when so disposed to measure the load drawn current signal. The current measurement apparatus 100 also comprises a signal source 112 which is operative to apply a reference input signal to the measurement arrangement 110, 114 whereby an output signal from the measurement arrangement comprises a load output signal corresponding to the load drawn current signal and a reference output signal corresponding to the reference input signal.

Abstract: A local area networking apparatus comprises a power stage for connecting to a network cable for carrying power and data. The power stage comprises a main current flow path which includes a switch comprising at least one transistor positioned in the main current flow path and a current monitoring apparatus for monitoring current flow in the main current flow path, and wherein the current monitoring apparatus comprises a sensor which is not placed in series with the main current flow path. The current monitoring apparatus can comprise a current mirroring stage which is arranged to mirror current flowing in the main current flow path to a monitoring current flow path. The switch can be implemented as a set of switches.

Abstract: Gate drive faults are detected for an inverter which comprises a phase switch having an insulated gate, such as an IGBT. A complementary transistor pair is adapted to receive a supply voltage and a pulse-width modulated (PWM) signal to alternately charge and discharge the insulated gate. A comparator compares the voltage at the insulated gate with a reference voltage representing a gate drive fault to generate a first logic signal. A latch samples the first logic signal when the PWM signal has a value corresponding to charging the insulated gate. A logic circuit inhibits charging of the insulated gate when the latched logic signal indicates the gate drive fault. An insulated gate voltage less than the reference voltage is indicative of an under-voltage fault as well as other device failures of the IGBT or the complementary transistors.

Abstract: An antenna device of an embodiment includes: an antenna; a variable impedance matching circuit that is connected to the antenna; a probe that receives power from the antenna; a power detector that is connected to the probe; a control circuit controlling the variable impedance matching circuit based on a value of power measured by the power detector; a first arithmetic circuit calculating a variation in the value of power measured by the power detector; a comparator circuit that compares the variation with a predetermined numerical value range; and a starter circuit that activates the control circuit based on a result of the comparison performed by the comparator circuit.

Abstract: A method of measurement using a detachable current and voltage sensor provides an isolated and convenient technique for to measuring current passing through a conductor such as an AC branch circuit wire, as well as providing an indication of an electrostatic potential on the wire, which can be used to indicate the phase of the voltage on the wire, and optionally a magnitude of the voltage. The device includes a housing that contains the current and voltage sensors, which may be a ferrite cylinder with a hall effect sensor disposed in a gap along the circumference to measure current, or alternative a winding provided through the cylinder along its axis and a capacitive plate or wire disposed adjacent to, or within, the ferrite cylinder to provide the indication of the voltage.

Abstract: A detachable current and voltage sensor provides an isolated and convenient device to measure current passing through a conductor such as an AC branch circuit wire, as well as providing an indication of an electrostatic potential on the wire, which can be used to indicate the phase of the voltage on the wire, and optionally a magnitude of the voltage. The device includes a housing formed from two portions that mechanically close around the wire and that contain the current and voltage sensors. The current sensor is a ferrite cylinder formed from at least three portions that form the cylinder when the sensor is closed around the wire with a hall effect sensor disposed in a gap between two of the ferrite portions along the circumference to measure current. A capacitive plate or wire is disposed adjacent to, or within, the ferrite cylinder to provide the indication of the voltage.

Abstract: A circuit and method are provided for detecting a power of a signal amplified in a power amplifier. A diode and a voltage bias source are used to shift a voltage of the signal taken at a base of an amplifying transistor of the power amplifier, to generate a positive signal. The positive signal is provided to a base input of an emitter follower exhibiting high input impedance to generate a power detector output which follows the positive signal.

Abstract: A method for determining an energy yield loss of a first wind turbine of a wind farm that includes a plurality of wind turbines. The first wind turbine is operated in a reduced energy yield mode that is outside an energy-optimized normal operating mode and a reduced energy yield of the first wind turbine is determined. At least one second wind turbine is selected according to a pre-determinable criterion. The energy yield of the at least one second wind turbine is determined and depending upon the energy yield of the at least one second wind turbine, an energy yield potential of the first wind turbine is determined. The difference between the energy yield potential of the first wind turbine and the determined reduced energy yield is formed.

Abstract: In accordance with an embodiment, a method of detecting a phase difference between a first signal and a second signal include latching a state of the first signal using the second signal as a clock to produce a first latched signal, latching a state of the second signal using the first signal as a clock to produce a second latched signal summing the first latched signal and the second latched signal to produce an indication of whether the first signal is leading or lagging the second signal.

Abstract: A method of re-offsetting a plurality of amplifier is provided. The method includes testing the plurality of amplifiers based on a re-offset value at bulks of compensation transistors of the plurality of amplifiers; identifying a first group of first amplifiers of the plurality of amplifiers favoring reading a first logic level and/or a second group of second amplifiers of the plurality of amplifiers favoring reading a second logic level different from the first logic level, based on results of the testing step; changing the re-offset value to a new re-offset value; re-offsetting the first group of first amplifiers and/or the second group of second amplifiers based on the new re-offset value; and re-testing the first group of first amplifiers and the second group of second amplifiers.

Abstract: An electrical resistance measuring device for a tire (T) that measures the electrical resistance from a bead portion (71) to a tread portion (70) and includes a measuring tip (5a) that is curvedly deformable along the shape of the tire (T).

Abstract: A method for the detection of a gripping of a hand-held device with one hand, using a capacitive sensor device, uses at least one transmitting electrode, at least one compensating electrode and at least one receiving electrode. An electrical signal is tapped at the receiving electrode and the sensor device can be operated in a first operating mode and in a second operating mode. In the first operating mode, a first alternating electrical signal is applied to the transmitting electrode and a second alternating electrical signal is applied to the compensating electrode. In the second operating mode, the second alternating signal is only applied to the compensating electrode. Furthermore, a sensor device can be provided which is configured to perform the method as described above.

Abstract: A capacitive sensing array device of an electronic apparatus includes sensing electrodes, a shielding conductor layer, a coupling signal source, a constant voltage source and switch modules. The coupling signal source provides a coupling signal coupled to an object. The constant voltage source provides a constant voltage to the shielding conductor layer to form a stable vertical parasitic capacitor between the shielding conductor layer and each sensing electrode. Each switch module is electrically connected to the constant voltage source via the corresponding sensing electrode. When one sensing electrode is selected to perform sensing, the corresponding switch module is configured as an open-circuited state such that the selected sensing electrode is disconnected from the constant voltage source, while the other sensing electrodes are electrically connected to the constant voltage source to form a stable horizontal parasitic capacitor between the selected sensing electrode and the other sensing electrodes.

Abstract: A system for measuring a capacitor (CSENj) precharges a CDAC (23) in a SAR converter (17) to a reference voltage (VAZ) and also precharges a first terminal (3-j) of the capacitor to another reference voltage (GND). During a measurement phase, the CDAC is coupled between an output and an input of an amplifier (31) and the capacitor also is coupled to the input of the amplifier, so as to redistribute charge between the capacitor and the CDAC. The amplifier generates an output voltage (VAMP) representing the capacitance being measured. The output voltage is stored in the CDAC. The SAR converter converts the output voltage to a digital value representing the capacitance being measured.

Abstract: According to some embodiments, a system is provided for simulating a cluster of reflections. The system includes an array of antenna elements distributed in space over a solid angle having an angular spread. The solid angle is substantially less than a full sphere and each antenna element has a spatial orientation. The system also includes a spatial environment simulator connected to the antenna elements and configured to apply one of excitations to the antenna elements and weights to signals from the antenna elements. The combination of the spatial distribution of the antenna elements, the orientation of the antenna elements, and the weighting applied by the variable path simulator simulates a near field arising from a cluster of reflections of a multipath environment.

Abstract: A method of digital sampling of a current or group of currents in an electrical system including using in the sampling, sufficient bandwidth to reconstruct the amplitude and phase of a synthesized power frequency and its harmonics and a fundamental carrier frequency of switching electronics and modulation sidebands.

Abstract: A transformer diagnosis apparatus and method which can advantageously be used for on-line diagnosis of a transformer, and by which transformer properties may be monitored and/or determined. The diagnosis method includes collecting, for at least two different transformer loads, measurements of a current being indicative of the transformer load, as well as measurements of at least one further transformer AC signal. The method further includes deriving, from the collected measurements, at least two values of a quantity which depends on a transformer property as well as on transformer load; and determining, from the derived values, a set of coefficient(s) of a relation for how the quantity is expected to vary with transformer load. The method further includes using the determined coefficient(s) in performing a diagnosis of the transformer.

Abstract: An electrical power supply device includes a DC voltage source with terminals, a controller, and an insulation-defect detecting device for detecting an insulation defect of the voltage source. The device has input terminals connected to source terminals, and circuits connected between respective input terminals and an intermediate point. The insulation-defect current-detection circuit connects between ground and the intermediate point. Both circuits have current-limiter circuits that open and close a connection between respective inputs and the intermediate point. Both current-limiter circuits are rated for traversal by a current of less than a standardized safety threshold when the first current-limiter circuit is closed and one of the terminals of the DC voltage source is shorted to ground. The control circuit is configured to simultaneously keep one current-limiter circuits open and the other closed.

Abstract: A test circuit of a semiconductor integrated circuit includes a through via, a voltage driving unit, and a determination unit. The through via is charged by receiving an input voltage. The voltage driving unit generates a test voltage by charging or discharging the through via in response to a test control signal. The determination unit compares levels of the input voltage and the test voltage and outputs a resultant signal.

Abstract: This disclosure provides systems, methods and apparatus for a display apparatus including dummy display elements that can be switched between being coupled to a test bus and a drive bus. When connected to the drive bus, the circuit components, including thin-film transistors, of the dummy display element experience exposure to typical operating loads. When connected to the test bus, the display apparatus can test the operating parameters of the dummy display element circuit components.

Abstract: A method of testing a semiconductor device includes forming a test circuit over a semiconductor substrate. The test circuit includes a plurality of interconnects electrically connected to a set of device structures supported by the semiconductor substrate. A test, such as a gate stress or leakage current test, of each device structure is conducted with the test circuit. The plurality of interconnects are removed after conducting the test.

Abstract: A current measurement circuit includes first and second input nodes which receive the respective voltages at either side of a resistive element through which electrical current can flow, a differential amplifier means which produces an output signal indicative of the difference in voltage between its input terminals, electrical path forming means providing a connection between each of the input nodes and a respective input terminal of the differential amplifiers, a controllable voltage source for selectively applying an offset voltage to at least one input of the differential amplifier in response to a control signal, a control signal generator which generates the control signal applied to the voltage source such that at a first instance an offset voltage is applied which is greater than that applied at a second instance, and a diagnostic means which is adapted to identify faults present in the electrical path between the first input node and the respective input to the amplifier by comparing the output from

Abstract: A computer implemented system for testing electronic equipment where test inputs, test outputs, test applied environmental conditions, and test processes are recorded and correlated.

Abstract: A testing circuit for testing proper connections between pins and corresponding circuits within an integrated circuit includes a pin selection module. The pin selection module includes a plurality of input pins, an output pin, and a control pin. The pin selection module selectively connects one of the input pins to the output pin based upon a control signal from the control pin. A voltage-dividing module includes an input end to receive a test voltage, an output end connected with the output pin of the pin selection module, and a voltage-dividing element connected between the input end and the output end. A determination module receives an output voltage from the output end, and determines whether the voltage of the output end falls into one of several predetermined voltage ranges, and outputs a result accordingly.

Abstract: An apparatus for testing a device. The apparatus comprises a test control module and a test analysis module. The test control module is operable to generate and transmit first prober and handler (PH) requests to a supervisor module. The supervisor module is operable to transmit first PH commands to a prober and handler for execution thereof. The test analysis module is operable to generate and transmit second PH requests to the supervisor module. The supervisor module is further operable to transmit second PH commands to the prober and handler for execution thereof. The execution of the second PH commands are performed transparently to the test control module.

Abstract: Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.

Abstract: A scan chain of an integrated circuit is disclosed, including a plurality of scannable storage elements and a control test point having a scan latch and an integrated clock gate (ICG) with clock, functional enable (FE) and scan enable (SE) inputs, and a gated clock output. The ICG may respond to an SE input active state, in a serial scan mode allowing the gated clock output to change. The ICG may also be operated in a scan capture mode, responding to an SE input inactive state, in which the gated clock output is inhibited from changing in response to a low FE input level. The ICG's gated clock output may be coupled to the scan latch clock input, which may hold its data output at a fixed level in response to ICG's gated clock output being inhibited from changing during the scan capture operation.

Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

Abstract: A semiconductor device includes a digital circuit having a scan test mode. The digital circuit includes a first flip-flop forming a part of a scan chain when in the scan test mode, and a first selector provided on an input side of the first flip-flop. The first selector is capable of selecting a first signal when not in the scan test mode, and selecting a second signal that is different from the first signal when in the scan test mode.

Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

Abstract: The present invention relates to a measuring device (10) for measuring a resistance of a switching contact (5) of an electrical circuit breaker (1). The measuring device (10) comprises a high-current generating unit (11) for generating a measurement current for the resistance measurement, and a measuring unit (12) for registering a measurement signal at the circuit breaker (1) during the opening or closing of the switching contact (5), and for determining a time-based resistance course of the switching contact (5) during opening or closing, in dependence on the measurement current and the measurement signal.

Abstract: An impulse voltage generator uses a predetermined rectangular waveform signal and a high voltage to generate an impulse voltage. The high voltage is obtained by boosting an instruction voltage of the rectangular waveform signal on a per-cycle basis. A partial discharge frequency calculation section receives detection signals based on partial discharges occurring in an object to be measured by the application of the impulse voltage and counts the detection signal on a per-cycle basis as a partial discharge frequency. An application voltage signal observation circuit observes an application voltage signal indicating the impulse voltage applied to the object to be measured. In a first cycle in which the partial discharge frequency reaches a specified frequency or more, a voltage value acquiring section sets, as a partial discharge starting voltage, the peak value of the voltage indicated by the application voltage signal output from the application voltage signal observation circuit.

Abstract: An analog measurement data detection system according to the present invention includes: a reference voltage generation circuit configured to generate and output a reference voltage; an analog/digital converter configured to compare an analog signal with the reference voltage outputted from the reference voltage generation circuit, and based on a differential voltage between the analog signal and the reference voltage, generate and output a digital signal corresponding to the analog signal. The reference voltage generation circuit is configured to cause the reference voltage to have such a temperature characteristic as to compensate for temperature characteristics of at least the analog/digital converter and the reference voltage generation circuit.

Abstract: Systems and methods for monitoring a battery stack having a plurality of cells are provided. One system includes a plurality of time delay circuits. Each of the time delay circuits is electrically coupled to at least one of the plurality of cells. The time delay circuits are configured to execute a time delay in response to receiving a trigger signal and output a time delay marking signal indicating that the time delay has elapsed. The time delay is based on a voltage of the cell(s) to which the respective time delay circuit is electrically coupled. The system further includes a control circuit configured to receive the time delay marking signal from each of the time delay circuits and, for each received time delay marking signal, to determine the voltage of the at least one of the plurality of cells associated with the respective time delay marking signal.

Abstract: An impedance analyzing device, adapted to a testee comprising an electrode or at least one battery cell, includes a signal capturing unit, a signal adjusting unit, a signal analyzing unit, a processing unit, and a power source supply unit providing a variable-frequency voltage signal to the testee. The signal adjusting unit receiving and adjusts a variable-frequency voltage signal and the current signal to generate an adjusted variable-frequency voltage signal and an adjusted current signal. The signal capturing unit captures a current signal generated by the testee in response to the variable-frequency voltage signal. The signal analyzing unit receives and analyzes the adjusted variable-frequency voltage signal and the adjusted current signal in frequency domain to obtain a frequency domain parameter and/or a time domain parameter. The processing unit receives the frequency domain parameter and/or the time domain parameter to obtain an impedance variation characteristic of the testee.

Abstract: In various embodiments, a method for evaluating a cell of a battery is provided. The method may include: balancing a voltage of at least one cell of the battery using charge pulses, wherein the charge pulses are modulated with an oscillating test signal; measuring a current flow through the cell and measuring a voltage across the cell; demodulating the measured current and the measured voltage; and determining an impedance based on the demodulated current and the demodulated voltage. Further, in various embodiments, a circuit is provided, including a balancing circuit configured to inductively transfer charges between cells in a battery using current pulses, and a control unit configured to control the balancing circuit to provide the current pulses, wherein an average value of the current pulses oscillates over time.

Abstract: An analyzer comprises a particle system acquisition unit operative to acquire information on a particle system defined in a virtual space; a magnetic moment association unit operative to associate a particle in the particle system with a magnetic moment; a numerical operation unit operative to perform numerical operation according to a governing equation that governs a motion of each particle in the particle system, the particle system including the particle which is associated with the magnetic moment by the magnetic moment association unit; and a magnetic field calculation unit operative to calculate a magnetic field created by the particle system using the results of the numerical operation performed by the numerical operation unit.