Abstract: A task worker running on a worker server receives a process specification over a network. The process specification specifies a task to be executed by the task worker. The executed task includes generating an output data object for an output data stream based in part on an input data object from an input data stream. The process specification is accessed to specify the required fields to be read from for executing the task and to specify the generated the fields in the input data object that will be written to during or subsequent to the executing of the task. The task worker executes the task and generates the output data object. The output data object is then transmitted to the output stream based on the stream configuration.

Abstract: A method for job management in an HPC environment includes determining an unallocated subset from a plurality of HPC nodes, with each of the unallocated HPC nodes comprising an integrated fabric. An HPC job is selected from a job queue and executed using at least a portion of the unallocated subset of nodes.

Abstract: Various techniques for automatically administering UNIX commands to target systems are disclosed. One method involves receiving information identifying a UNIX command and additional information identifying one or more target systems. The method then issues N instances of the UNIX command in parallel to the one or more target systems, where N is an integer greater than one. The N instances of the UNIX command are issued automatically, in response to receipt of the information and the additional information. In some situations, issuing the N instances of the UNIX command in parallel involves creating N threads, where each of the N threads is configured to issue a respective one of the N instances of the UNIX command to a respective one of the target systems.

Abstract: Embodiments of the claimed subject matter are directed to methods and a system that allows the optimization of processes operating on a multi-platform system (such as a mainframe) by migrating certain processes operating on one platform to another platform in the system. In one embodiment, optimization is performed by evaluating the processes executing in a partition operating under a proprietary operating system, determining a collection of processes from the processes to be migrated, calculating a cost of migration for rating the collection of processes, prioritizing the collection of processes in an order of migration and incrementally migrating the processes according to the order of migration to another partition in the mainframe executing a lower cost (e.g., open-source) operating system.

Abstract: A lock management method and system, and a method and an apparatus for configuring a lock management system is provided. A corresponding level of a lock management system is set for each service execution node according to the number of service execution nodes included in a distributed system, the number of system instances on all service execution nodes, the number of handling processes on all the service execution nodes, and a delay of access of each service execution node to a central control node of the distributed system. At least one lock manager is allocated to each service execution node separately according to the level, which is corresponding to each service execution node, of the lock management system. A lock level context is configured for each lock manager, where the lock level context is used to determine an adjacent lock manager of each lock manager.

Abstract: A method for interposing on operating system calls in a host is provided. The method includes patching an operating system kernel function, the patching comprising adding a first pointer that invokes an agent function, the patching performed by an agent. The method includes executing the agent function, responsive to a system call stub calling the operating system kernel function, which invokes the agent function via the first pointer, wherein at least one action of the method is performed by a processor of a host having an operating system.

Abstract: A software and implementable system which provides bi-directional communication between engineering, through software add-ins, and other applications within an ERP system. Such a system provides efficiency enhancements and provides improved data flow and communication between engineering and others. While not required, the system is well suited for application in association with manufacturing of equipment, and in particular, manufacturing of custom equipment.

Abstract: A data object from a data source is received by a distributed process in a data stream. The distributed process has a sequence of categories, each category containing one or more tasks that operate on the data object. The data object includes files that can be processed by the tasks. If the task is able to operate on the data object, then the data object is passed to the task. If the task is unable to operate on the data object, then the files in the data object are passed to a file staging area of the distributed process and stored in memory. The files in the file staging area are passed, in sequence, from the file staging area to the task that was unable to operate on the data object. The data object is outputted to a next category or data sink after being operated on by the task.

Abstract: Embodiments described herein are directed to methods, and systems for generating event processing language code in a development environment using an event processing compiler. A query in event processing language is received in a development environment. The query can be associated with sample data from input files or an input data source. An event processing compiler compiles the query, where the compiler transforms the query from event processing language code to a development environment script language code. In particular, the event processing language code transforms the code based on event processing attributes that are intricately aligned in syntax and semantic between the event processing language and the development environment script language. The query as a development environment script is executed using sample data.

Abstract: An electronic device includes a first processor; and a second processor; and a third processor. The second processor is configured to detect an event, select one of the first and third processors to perform one or more operations associated with the event, and cause the selected processor to perform the one or more operations.

Abstract: An approach is provided for distributing notifications from developers to installed applications via a notification enabler separate from the applications. The notification platform determines at least one application installed on at least one device. Then, the notification platform causes, at least in part, a subscription via at least one notification enabler to one or more notification channels associated with the at least one application, wherein the at least one notification enabler is a separate component from the at least one application.

Abstract: A system and method may generate executable block diagrams having blocks that run in accordance with message-based execution semantics. A message may include an input data payload that does not change over time, and the message may persist for only a determined time interval during execution of block diagram. A verification engine may provide one or more tools for evaluating and verifying operation of message-based blocks. The verification engine may support one or more verification blocks that may be added to the block diagram and associated with the diagram's message-based blocks. The verification blocks may capture and present messages exchanged among the message-based blocks. The verification blocks may also specify an expected interaction of messages, and determine whether the actual messages are equivalent to the expected interaction.

Abstract: A cognitive computing hardware system receives an error log from an IT system. The error log comprises a record of errors currently being detected by sensors in the IT system. The cognitive computing hardware system receives an error history log, which describes a history of past errors that have occurred in the IT system. The cognitive computing hardware system receives a listing of alternative IT systems that have been predetermined to have a same functionality as the IT system that is currently experiencing the errors. The cognitive computing hardware system receives a record of real-time events that are external to the IT system, and generates a prioritized set of solutions to heal the IT system, based on the error history log, the listing of alternative IT systems, and the record of real-time events. The cognitive computing hardware system transmits a highest prioritized solution to the IT system.

Abstract: A system analysis device 100 includes a whole model generation unit 1021 which generates a whole model which is obtained by modeling elements or whole of a system and which includes a plurality of partial models, a core model generation unit 1023 which extracts, from a plurality of whole models generated on the basis of the same event, the partial models whose prediction precision satisfies a predetermined criteria, and generates a core model by integrating the extracted partial models, and a threshold setting unit 1024 which calculates a distance between the core model and the plurality of whole models using a predetermined definition, and outputs the distance as a threshold value for error determination using the core model.

Abstract: A method of operating a data processing system comprises: processing data words and switching between contexts; assigning a context signature Sig to any pair formed of a data word and a context; reading, within a current context, a data record from a memory unit, the data record comprising a payload data word and a protection signature; providing, as a verification signature, the context signature Sig of the payload data word and the current context; checking the verification signature against the protection signature; and generating an error signal if the verification signature differs from the protection signature.

Abstract: A method of detecting impending analytical failure in a networked diagnostic clinical analyzer is based upon detecting whether the operation of a particular analyzer is statistically distinguishable based on one or more thresholds. A failure occurs when one or more components or modules of the analyzer fails. A method to detect such an impending failure is disclosed. Baseline data on a pre-selected set of analyzer variables for a population of diagnostic clinical analyzers is used to generate an impending failure threshold. Subsequently, operational data comprising the same pre-selected set of analyzer variables allows generation of a time series of operational statistics. If the operational statistic exceeds the impeding failure threshold in a prescribed manner, an impending analytical failure is predicted. Such detection of impending analytical failures facilitates intelligent scheduling of service for the analyzer in question to maintain high assay throughput and accuracy.

Abstract: Various embodiments for retaining diagnostic information for data in a computing storage environment. In one such embodiment, a diagnostic component, apart from a volume table of contents (VTOC), associated with an integrated catalog facility (ICF) catalog and with a base data set from data sets via a catalog association record, is initialized. The diagnostic component is configured to retain base data set-specific diagnostic information retrievable by the computing storage environment to assist in error diagnosis. The base data set-specific diagnostic information is stored pursuant to at least one detected event associated with the base data set.

Abstract: Diagnosis of defect(s) in a system is disclosed. A defect signature-based query is performed against system diagnostic data stored in one or more structured records. It is determined that a defect signature is associated with a system based at least in part on the query. Remediation information generated based at least in part on the defect signature and the system diagnostic data may be output.

Abstract: A method of controlling a watchdog and an apparatus for the same are provided. The method of controlling a watchdog within a controller includes determining, by a processor, whether to respond to a fault in the controller by comparing a watchdog count with a predetermined watchdog warning level when the fault is detected. Further, the method includes storing, by the processor, information regarding a program group related to the detected fault and a watchdog reset count that corresponds to the program group within a memory after increasing the watchdog reset count when the fault is to be responded to. In addition the processor is configured to reset the controller when the watchdog count exceeds a predetermined watchdog timeout level. Therefore, the present invention prevents occurrence of repeated resets that result from the same cause within the controller.

Abstract: A calibration method includes transmitting first data comprising a calibration data and a first checksum to the storage device according to each of a plurality of training parameter sets; recording a plurality of error indicators respectively which are corresponding to the plurality of training parameter sets and from the storage device; and identifying one of the plurality of training parameter sets as a predetermined parameter set according to the plurality of error indicators respectively corresponding to the plurality of training parameter sets; wherein each error indicator indicates whether transmitting the first data according to the corresponded training parameter set is successful.

Abstract: A computer program product and a computer system for building a scalable system dump facility is provided. The method includes loading a component into system memory. The component includes a plurality of program modules. A component text range table entry is created for each component, whereby the component text range table entry includes: an address range, a component identifier, a data collection function, and a link to one or more related components. Upon invoking a system dump facility, a failing function instruction is determined, based on an address of the failing instruction. The component text range table is searched for an address of a failing function that is in the address range. Memory regions that are associated with the address range are transferred to a storage device first. Memory regions that are associated with related components are transferred next. Remaining memory regions are then transferred.

Abstract: A method for building a scalable system dump facility is provided. The method includes loading a component into system memory. The component includes a plurality of program modules. A component text range table entry is created for each component, whereby the component text range table entry includes: an address range, a component identifier, a data collection function, and a link to one or more related components. Upon invoking a system dump facility, a failing function instruction is determined, based on an address of the failing instruction. The component text range table is searched for an address of a failing function that is in the address range. Memory regions that are associated with the address range are transferred to a storage device first. Memory regions that are associated with related components are transferred next. Remaining memory regions are then transferred.

Abstract: A computing system includes: a volatile memory configured to: store a debug assert flag mask including bits; cores, coupled to the volatile memory, configured to: detect an error in at least one of the cores, set at least one of the bits corresponding to the cores with the error detected, collect debug information for each of the cores with the error detected, collect operating information for each of the cores without the error detected, generate assert dump information based on compiling the debug information; and a nonvolatile memory, coupled to at least one of the cores, configured to: store the assert dump information, the operating information, configured to by at least one of the cores.

Abstract: An electronic system comprises: a pin sensor; and an integrated management module, wherein the integrated management module: identifies a location of a damaged connector between a semiconductor chip and a hardware socket, wherein the location of the damaged connector is described by one or more readings from the pin sensor, and wherein the damaged connector prevents a particular signal from being supplied to the semiconductor chip via the hardware socket; identifies the particular signal as an input for a particular semiconductor function; determines whether the semiconductor chip provides the particular semiconductor function; and adjusts a use of the semiconductor chip based on whether or not the semiconductor chip uses the particular signal to provide the particular semiconductor function.

Abstract: A data reading method, a memory storage device and a memory controlling circuit unit are provided. The method includes: receiving a first read command; setting a plurality of first read events in a multi trigger queue (MTQ) according to the first read command, wherein the first read events include a general read event and at least one cache read event; sending a first read command sequence according to at least one of the first read events and receiving first data from a rewritable non-volatile memory module; and if a decoding for the first data fails, resetting the MTQ, and sending at least one second read command sequence according to at least one second read event in the reset MTQ, wherein the at least one second read event includes at least one of the at least one cache reading event.

Abstract: Software that combines parity bits with error correcting codes (ECC) such that a subset of ECC bits is also used for parity purposes, by performing the following steps: (i) providing a first set of redundant bit(s) in a data block, where the first set of redundant bit(s) is adapted to detect and/or correct errors in the data block; (ii) providing, within the first set of redundant bit(s), a first sub-set of parity bit(s), where the first sub-set of parity bit(s) is adapted to provide single bit error detection for the data block; and (iii) determining, based, at least in part, on a first set of data read requirements, whether to use the first set of redundant bit(s) and/or the first sub-set of parity bit(s) to detect and/or correct potential errors while reading data on the data block.

Abstract: An error of stored data is detected with high accuracy. Data (e.g., a remainder in a CRC) used for detecting an error is stored in a memory in which an error is unlikely to occur. Specifically, the following semiconductor device is used: a memory element including a plurality of transistors, a capacitor, and a data storage portion is provided in a matrix; the data storage portion includes one of a source and a drain of one of the plurality of transistors, a gate of another one of the plurality of transistors, and one electrode of the capacitor; a semiconductor layer including a channel of the transistor, the one of the source and the drain of which is connected to the data storage portion, has a band gap of 2.8 eV or more, or 3.2 eV or more; and the data storage portion stores data for detecting an error.

Abstract: A data access method for a rewritable non-volatile memory module is provided. The method includes: filling dummy data to first data in order to generate second data, and writing the second data and an error checking and correcting code (ECC code) corresponding to the second data into a first physical programming unit. The method also includes: reading data stream from the first physical programming unit, wherein the data stream includes third data and the ECC code. The method further includes: adjusting the third data according to a pattern of the dummy data in order to generate fourth data when the third data cannot be corrected by using the ECC code, and using the ECC code to correct the fourth data in order to obtain corrected data, wherein the corrected data is identical to the second data.

Abstract: A semiconductor memory device and ECC method thereof are provided which a first nonvolatile memory; a second nonvolatile memory having a type different from the first nonvolatile memory; a controller; a first error correction circuit configured to correct an error of first write data to be programmed at the first nonvolatile memory; and a second error correction circuit included in the controller and configured to correct an error of first write data or an error of second write data to be programmed at the second nonvolatile memory, based on an error correction algorithm different from that of the first error correction circuit. Error correction data for correcting an error of the first write data is generated using one of the first error correction circuit and the second error correction circuit according to an attribute of the first write data.

Abstract: A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus.

Abstract: Software that combines parity bits with error correcting codes (ECC) such that a subset of ECC bits is also used for parity purposes, by performing the following steps: (i) providing a first set of redundant bit(s) in a data block, where the first set of redundant bit(s) is adapted to detect and/or correct errors in the data block; (ii) providing, within the first set of redundant bit(s), a first sub-set of parity bit(s), where the first sub-set of parity bit(s) is adapted to provide single bit error detection for the data block; and (iii) determining, based, at least in part, on a first set of data read requirements, whether to use the first set of redundant bit(s) and/or the first sub-set of parity bit(s) to detect and/or correct potential errors while reading data on the data block.

Abstract: Aspects of the present disclosure are directed to circuits, apparatuses and methods for operating volatile memory circuits. According to an example embodiment, an apparatus includes a volatile memory circuit and a control circuit coupled to the volatile memory circuit. The control circuit is configured to generate and store parity data for data blocks written to the volatile memory circuit. The control circuit places the volatile memory circuit in a sleep mode in response to a first control signal. In response to a second control signal, the control circuit places the volatile memory into an active mode. In further response to the second control signal the control circuit detects and corrects errors in the data blocks stored in the volatile memory using the stored parity data.

Abstract: In one embodiment, an apparatus includes one or more memory devices, each memory device having non-volatile memory configured to store data, and a memory controller connected to the one or more memory devices, the memory controller being configured to receive data to be stored to the one or more memory devices, store read-hot data within one error correction code (ECC) codeword as aligned data, and store read-cold data to straddle two or more ECC codewords as non-aligned data and/or dispersed data. According to another embodiment, a method for storing data to non-volatile memory includes receiving data to store to one or more memory devices, each memory device including non-volatile memory configured to store data, storing read-hot data within one ECC codeword as aligned data, and storing read-cold data to straddle two or more ECC codewords as non-aligned data and/or dispersed data.

Abstract: An information handling system includes a plurality of storage disks arranged as a redundant array of independent disks and a controller. The controller communicates with each of the storage disks. The controller determines a total amount of storage space utilized to store parity information within the storage disks based on a smallest disk size of the storage disks and a number of storage disks in the redundant array of independent disks, calculates an amount of storage space utilized to store parity information on each of the disks based on the total amount of storage space utilized to store parity information and the number of storage disks, and allocates a parity region of sectors within each of the storage disks to store the parity information. The parity region is an inner most region of a disk.

Abstract: Techniques, systems, and devices are disclosed for remediating a failed drive in a set of drives, such as a RAID system, without having to physically replace the failed drive. After receiving a signal of an error indicating a specific physical portion on a storage drive in the set of storage drives has caused the drive to fail, the system can unmount the drive from the filesystem while other drives continue to operate. Next, the system can identify one or more files in the filesystem that have associations with the specific physical portion on the failed drive. Next, the system can remount the drive onto the filesystem and subsequently delete the identified files from the filesystem. The system can then perform a direct I/O write to the specific physical portion on the failed drive to force reallocation of the specific physical portion to a different area on the failed drive. The system can also power-cycle the drive before this remediation, e.g., to determine if this remediation can be avoided.

Abstract: A peripheral bus error containment and recovery system enables a bus device to experience a fatal bus error and recover without stopping execution of an operating system. When a fatal bus error is detected at the bus device, a bus controller may deactivate a data link layer for a downstream port populated by the bus device, causing an operating system device driver to be uninstalled for the bus device. Then, the operating system device driver may be reinstalled without physically removing the bus device.

Abstract: In one embodiment, an extent store layer of a storage input/output (I/O) stack executing on one or more nodes of a cluster manages efficient logging and checkpointing of metadata. The metadata managed by the extent store layer, i.e., the extent store metadata, resides in a memory (in-core) of each node and is illustratively organized as a key-value extent store embodied as one or more data structures, e.g., a set of hash tables. Changes to the set of hash tables are recorded as a continuous stream of changes to SSD embodied as an extent store layer log. A separate log stream structure (e.g., an in-core buffer) may be associated respectively with each hash table such that changed (i.e., dirtied) slots of the hash table are recorded as entries in the log stream structure. The hash tables are written to SSD using a fuzzy checkpointing technique.

Abstract: In one embodiment, a device receives a router advertisement message after a power outage event in a network. The device joins the network, in response to receiving the router advertisement message. The device sends a power restoration notification message via the network. The device selectively delays a disconnected node from joining the network.

Abstract: A method for implementing a change capture system using an event publishing system as a database recovery log is provided. The method may include determining a set of data based on a description of events for which change capture is possible. The method may also include selecting at least one item of data from within the determined set of data, wherein the at least one item of data requires change capture to be performed. Additionally, the method may include identifying at least one published event, wherein the at least one published event is produced by the event publishing system. The method may include instructing the event publishing system to deliver the at least one identified published event to the change capture system. Furthermore, the method may include receiving the at least one identified published event. The method may also include processing the at least one published event.

Abstract: A method for implementing a change capture system using an event publishing system as a database recovery log is provided. The method may include determining a set of data based on a description of events for which change capture is possible. The method may also include selecting at least one item of data from within the determined set of data, wherein the at least one item of data requires change capture to be performed. Additionally, the method may include identifying at least one published event, wherein the at least one published event is produced by the event publishing system. The method may include instructing the event publishing system to deliver the at least one identified published event to the change capture system. Furthermore, the method may include receiving the at least one identified published event. The method may also include processing the at least one published event.

Abstract: According to certain aspects, a method can include, at a first time, performing an incremental backup of first data associated with a virtual machine (VM) residing on a source client computing device from the source client computing device to one or more secondary storage devices to create a backup copy of the VM, where the VM is associated with a hypervisor of a first type; receiving an instruction to restore the first data associated with the VM from the one or more secondary storage devices; retrieving the first data from the one or more secondary storage devices; and applying the first data to second data associated with a replicated VM running on the destination client computing device, where the replicated VM is a replicated version of the VM, and where the second data corresponds to data of the VM at a time before the first time.

Abstract: Systems and methods are provided for transmitting data to at least one storage system. A request is received to store a data set in a storage location. In response, a first plurality of shares is generated, each containing a distribution of data from the data set, and at least one share is stored in a local memory configured for backup in at least one remote storage system. At least one share is transmitted to the at least one remote storage system. Systems and methods are also provided for improving data availability. In response to a restoration event, if insufficient shares of data are available to reconstruct a data set, a read instruction in a journaling message is transmitted to a remote storage system requesting an additional share. The additional share is received and stored in a local storage, and the data set is reconstructed.

Abstract: A test device and a method for controlling the test device are disclosed. After a test is interrupted due to a malfunction of the test device, the test device continuously performs the interrupted testing. The test device for testing a biological material includes: a memory configured to store information which relates to progress of a test; and a controller which, if the test is interrupted due to a malfunction of the test device, is configured to continue performance of the test by using the information which relates to the test progress which is stored in the memory.

Abstract: A fault-tolerance through silicon via (TSV) interface is disposed in a three-dimensional random access memory (3-D RAM) with N memory layers and M data access path sets, and each of the memory layers containing K memory arrays, and each of the data access path sets containing a plurality of TSV paths connecting to the memory layers. The fault-tolerance TSV interface includes a path controlling unit and a processing unit. The path controlling unit detects and controls the data access path sets. When a fault occurs in any data access path set connecting to a memory layer, the processing unit provides at least two different fault-tolerance access configurations. In each of the fault-tolerance access configurations, p data access path sets are enabled to access all K memory arrays in the corresponding memory layer, where 0<?<M.

Abstract: A method and apparatus for providing redundancy in an Automatic Teller Machine (ATM) is provided. Application software may be run on top of a virtual environment such as a virtual machine and/or a virtual disk environment. Should a software component fail, the virtual environment will “crash” but the ATM hardware and operating system will remain intact. If the software is fatally flawed—e.g., due to a faulty “upgrade” the older version may be “rolled back” from a previously stored virtual environment.

Abstract: A method and apparatus for providing redundancy in an Automatic Teller Machine (ATM) is provided. Application software may be run on top of a virtual environment such as a virtual machine and/or a virtual disk environment. Should a software component fail, the virtual environment will “crash” but the ATM hardware and operating system will remain intact. If the software is fatally flawed—e.g., due to a faulty “upgrade” the older version may be “rolled back” from a previously stored virtual environment.

Abstract: A data storage device includes memory devices including respective main regions and respective virtual regions, and a processor suitable for forming a super page by selecting main pages from the respective main regions, wherein when a main page of a main region in a memory device is a bad region, the processor forms a virtual super page by selecting a virtual page from a virtual region in the memory device instead of the main page.

Abstract: A failover system and a method of deciding master-slave relationship therefor are provided. The failover system includes a first electronic device, a second electronic device, a decision circuit and at least two isolation modules. The decision circuit is coupled to the first electronic device and the second electronic device and configured to determine operating states of the first electronic device and the second electronic device and output a first selecting signal and a second selecting signal. The at least two isolation modules are coupled to the first electronic device, the second electronic device, and the decision circuit and configured to switch a master-slave relationship between the first electronic device and the second electronic device according to the first selecting signal and the second selecting signal.

Abstract: A method for mirroring in three-dimensional-stacked memory includes receiving a plurality of thermal profiles from a plurality of memory chips. The method also includes ranking the plurality of memory chips in a first ranked list of memory chips as a function of the plurality of thermal profiles and forming a first group of memory chips from the plurality of memory chips based on the first ranked list of memory chips. The method also includes forming a second group of memory chips from the plurality of memory chips distinct from the first group of memory chips based on the first ranked list of memory chips. The method also includes pairing a first memory chip from the first group of memory chips and a second memory chip from the second group of memory chips, and mirroring the pairing of memory chips.

Abstract: A method for mirroring in three-dimensional-stacked memory includes receiving a plurality of thermal profiles from a plurality of memory chips. The method also includes ranking the plurality of memory chips in a first ranked list of memory chips as a function of the plurality of thermal profiles and forming a first group of memory chips from the plurality of memory chips based on the first ranked list of memory chips. The method also includes forming a second group of memory chips from the plurality of memory chips distinct from the first group of memory chips based on the first ranked list of memory chips. The method also includes pairing a first memory chip from the first group of memory chips and a second memory chip from the second group of memory chips, and mirroring the pairing of memory chips.