Abstract: The present invention relates to a kernel state and user state data exchange method for disaster recovery of a virtual container system. In one disaster recovery backup of a virtual container, data needs to be exchanged between a kernel state and a user state. The file system operation of the kernel state needs to be transmitted to a user state program for processing firstly, and the processing result is returned to the kernel state and then transmitted to an original application program. Low recovery speed of a data block is mainly caused by the need of multiple times of switching between the kernel state and the user state, and the communication efficiency of the kernel state and the user state is low. In the present invention, all recovery operations are completed by the user state by virtue of a FUSE.

Abstract: Direct monitoring of a plurality of storage nodes in a primary cluster is performed based on connectivity with the storage nodes. Indirect monitoring of a first storage node is performed, in response to direct monitoring of the first storage node indicating failure of the connectivity with the first storage node, wherein a second storage node of the plurality of nodes is a backup node for the first storage node. The indirect monitor of the first storage node indicates failure of the first storage node in response to performance of storage access operations by the second storage node that were previously performed by the first storage node. A cluster-switch operation is initiated to switch to from the primary cluster to a backup cluster based on an occurrence of at least one cluster-failure condition that comprises the indirect monitor of the first storage node indicating failure of the first storage node.

Abstract: According to one aspect, a method for performance optimization of read functions in a memory system includes receiving, at the memory system, a read request including a logical address of a target data. The memory system includes a primary memory and a back-up memory that minors the primary memory. The method also includes searching a fault monitor table for an entry corresponding to the received logical address. The fault monitor table includes a plurality of entries that indicate physical locations of identified memory failure events in the primary memory and the back-up memory. Based on locating an entry corresponding to the received logical address, the method further includes selecting one of the primary memory and the backup memory for retrieving the target data. The selection is based on contents of the fault monitor table.

Abstract: A system and method for recovering stranded data from a non-volatile memory is provided. An example of a method includes copying data from a non-volatile memory (NVM) in a home node over a sideband interface and writing the data to a target memory region, wherein the target memory region is in a fail-over node.

Abstract: A simulation apparatus and a distribution simulation system are disclosed. The simulation apparatus, according to one example, includes a simulation executer configured to execute a simulation task, a data storage configured to store data related to the simulation task based on a data storage policy that is set in advance of the execution of the simulation tasks, and a data updater configured to update the data stored in the data storage to most recent data by comparing the data stored in the data storage with data stored in another simulation apparatus.

Abstract: The disclosed embodiments provide a system that facilitates testing of an insecure computing environment. During operation, the system obtains a real data set comprising a set of data strings. Next, the system determines a set of frequency distributions associated with the set of data strings. The system then generates a test data set from the real data set, wherein the test data set comprises a set of random data strings that conforms to the set of frequency distributions. Finally, the system tests the insecure computing environment using the test data set.

Abstract: A communication monitoring system includes a plurality of detecting portions each provided at a connector at an end of a communication cable or at a relay connector to be connected to the connector to branch, extract and output a portion of a signal transmitted through the communication cable, and a monitoring unit configured to monitor an existence of information communication through each of the communication cables provided with the detecting portions based on an output from the plurality of detecting portions.

Abstract: Verification is provided of a functional correctness of a graph-based coherency verification tool for logic designs of arrangements of processors and processor caches, the graph-based coherency verification tool using trace files as input for verifying memory ordering rules of a given processor architecture for accesses to the caches, wherein nodes in a graph represent memory accesses and edges represent dependencies between them. The verifying includes (i) providing a specification of a test case for a self-checking tool, the test case comprising a sequence of statements in a high-level description language format, representing memory access events and system events; and (ii) generating trace files with the self-checking tool for the graph-based coherency verification tool by producing permutations of trace events, which are defined by the sequence of statements of the test case.

Abstract: A computer optimizes the prospective generation of data used for analysis of a software problem. The computer generates data in accordance with data generation parameters and a software problem is analyzed with reference to the data so generated. The problem analysis produces a report that details specifics of the software problem, the data that was available for analysis, a flag to indicate success or failure of the analysis to identify a root cause, and information about whether the data supplied was insufficient, sufficient, or superfluous with respect to identifying a root cause of the software problem. The method then uses the analysis report to modify the data generation parameters, thereby iteratively optimizing the data that are generated for analysis of subsequent software problems.

Abstract: A computer optimizes the prospective generation of data used for analysis of a software problem. The computer generates data in accordance with data generation parameters and a software problem is analyzed with reference to the data so generated. The problem analysis produces a report that details specifics of the software problem, the data that was available for analysis, a flag to indicate success or failure of the analysis to identify a root cause, and information about whether the data supplied was insufficient, sufficient, or superfluous with respect to identifying a root cause of the software problem. The method then uses the analysis report to modify the data generation parameters, thereby iteratively optimizing the data that are generated for analysis of subsequent software problems.

Abstract: A pre-testing method adapted for environment updating is illustrated. The pre-testing method comprises following steps: while detecting an environment updating process should be performed to an operating system environment, determining whether an environment test should be executed; while the environment test is executed, selecting a plurality of pieces of system and software information of the operating system environment, wherein the system and software information of the operating system environment is extracted from the operating system environment; generating a virtual machine having a first clone environment according to the system and software information; performing the environment updating process to the first clone environment so as to cause the first clone environment to become a second clone environment of the virtual machine; and executing the environment test for the second clone environment.

Abstract: Embodiments provide a computerized method for adapting automating test scripts, said method including: utilizing at least one processor to execute computer code that performs the steps of: receiving, at an input device, an original test script created to test an application; utilizing the original test script to test, using the processor, a variant of the application; identifying, using the processor, failures in the original test script when the variant of the application is being tested; and modifying, using the processor, the original test script to overcome the identified failures.

Abstract: A computer-implemented method, computer program product, and system is provided for determining requirements for testing software. In an implementation, a method may include inspecting contents of a test case, including source code of the test case. The method may also include identifying at least one of: at least one characteristic of a test machine and at least one characteristic of a resource required to execute the test case correctly. The method may further include compiling a list of requirements for the test case to execute correctly based upon, at least in part, the at least one of the at least one characteristic of the test machine and the at least one characteristic of the resource.

Abstract: A computer-implemented method, computer program product, and system is provided for determining requirements for testing software. In an implementation, a method may include inspecting contents of a test case, including source code of the test case. The method may also include identifying at least one of: at least one characteristic of a test machine and at least one characteristic of a resource required to execute the test case correctly. The method may further include compiling a list of requirements for the test case to execute correctly based upon, at least in part, the at least one of the at least one characteristic of the test machine and the at least one characteristic of the resource.

Abstract: Simulating sensors can include hooking an application associated with sensory data and associating the sensory data with an automation instruction. Simulating sensors can include providing the sensory data to a support device having an ability to modify the application and automatically causing the support device to simulate a sensory input using the sensory data by executing the automation instruction.

Abstract: A method includes creating a macro plan for a test project, creating a micro plan for the test project, wherein the micro plan and the macro plan are based on at least one common parameter, and reconciling the macro plan and the micro plan by identifying deviations between the macro plan and the micro plan based on the at least one common parameter.

Abstract: Systems and methods that provide manual test cases and scripted test cases automatically based on metadata included in a software application. In an embodiment, an application may include elements that generate an output file containing information corresponding to one or more forms with one or more fields in an application. The information may be utilized by a test device or application to automatically generate manual test cases, automated scripted test cases, or a combination of manual and automated test cases based on the information. In an embodiment, a manual test case may include a sequence of instructions in a natural language format. In an embodiment, an automated test case may be in a script language configured to interact with the application or an appropriate application emulator.

Abstract: Verifying user interface conformance can include deriving a conformance rule set based on desired user interface characteristics identified through an examination of mockup data for the user interface. That mockup data includes a visual representation of the desired characteristics. Conformance data can then be generated based on differences between the desired characteristics and actual characteristics. Those differences are identified by processing the conformance rule set against screen capture data of the user interface as produced by an application under test. The screen capture data includes a visual representation of the actual characteristics of the user interface.

Abstract: Embodiments are directed to assigning a home memory location for a function call parameter. A method may include determining whether a caller is configured to allocate a memory location for a parameter passed to a callee. The caller is a module that includes a function call to the callee and the callee is a function. The method may include inserting instructions in the callee to allocate a home memory location for the parameter in response to determining that the caller is not configured to allocate a memory location for the parameter. In addition, the method may include inserting instructions in the callee to set the memory location as a home location for the parameter in response to determining that the caller is configured to allocate a memory location for the parameter.

Abstract: A method and a storage device for collecting garbage data, where the method includes separately recording a data volume of first data in each segment of a storage device at a current time and a variation of the first data in each segment of the storage device in a preset period of time before the current time; obtaining, by means of calculation, a predicted value of the first data according to the data volume of the first data in each segment and the variation of the first data in each segment; and determining, according to the predicted value of the first data in each segment, a segment whose garbage data needs to be collected. A segment that has more garbage data and whose garbage creating rate is lower is reclaimed preferentially.

Abstract: A memory control circuit has a request determination circuitry to determine whether a period without read-out request and write request to an i-th (i being an integer of 1 or more and of n or less, n being an integer of 2 or more) level cache memory among first to n-th level cache memories continues for a first period of time or longer, the i-th level cache memory comprising a first nonvolatile memory, and a power-supply controller to control a power cut-off timing to the i-th level cache memory based on a determination of the request determination circuitry.

Abstract: A method to merge one or more non-transactional stores and one or more thread-specific transactional stores into one or more cache line templates in a store buffer in a store cache. The method receives a thread-specific non-transactional store address and a first data, maps the store address to a first cache line template, and merges the first data into the first cache line template, according to a store policy. The method further receives a thread-specific transactional store address and a second data, maps the thread-specific store address into a second cache line template, according to a store policy. The method further writes back a copy of a cache line template to a cache and invalidates a third cache line template, which frees the third cache line template from a store address mapping.

Abstract: A method for caching and reading data to be programmed into a storage unit, performed by a processing unit, including at least the following steps. A write command for programming at least a data page into a first address is received from a master device via an access interface. It is determined whether a block of data to be programmed has been collected, where the block contains a specified number of pages. The data page is stored in a DRAM (Dynamic Random Access Memory) and cache information is updated to indicate that the data page has not been programmed into the storage unit, and to also indicate the location of the DRAM caching the data page when the block of data to be programmed has not been collected.

Abstract: A computer system according to the present invention is composed of a server 200 having a flash memory drive 204 for cache, a storage system 260 having storage tiers composed of an SSD 267 and an HDD 268, and a management server having a page tier determination program 503 for determining the storage tier to which data is to be stored. The page tier determination program 503 migrates data having a high read access rate out of the pages having a high cache rate to the flash memory drive 204 to a storage tier of the HDD 268, and confirms so that data is not stored in a duplicated manner to the flash memory drive 204 and the SSD 267. Further, the data having a relatively high write access rate is migrated to the storage tier of the SSD 267 so as to prevent deterioration of write process performance.

Abstract: A method to merge one or more non-transactional stores and one or more thread-specific transactional stores into one or more cache line templates in a store buffer in a store cache. The method receives a thread-specific non-transactional store address and a first data, maps the store address to a first cache line template, and merges the first data into the first cache line template, according to a store policy. The method further receives a thread-specific transactional store address and a second data, maps the thread-specific store address into a second cache line template, according to a store policy. The method further writes back a copy of a cache line template to a cache and invalidates a third cache line template, which frees the third cache line template from a store address mapping.

Abstract: According to an example, in a spinlock processing method, a value of a spinlock cache variable may be read from a cache and the value of the spinlock cache variable may be written into a register. A determination may be made as to whether the value of the spinlock cache variable is an initial value. If yes, the value of the spinlock cache variable in the register may be updated. A determination may also be made as to whether the spinlock cache variable is accessed by a core after the value of the spinlock cache variable is written into the register. If yes, a value of a spinlock cache variable may be obtained from the cache. If no, the updated value of the spinlock cache variable may be written into the cache. Moreover, an access speed of the cache may be larger than an access speed of an L2 cache.

Abstract: A system configuration is provided with multiple partitions that supports different types of address translation structure formats. The configuration may include partitions that use a single level of translation and those that use a nested level of translation. Further, differing types of translation structures may be used. The different partitions are supported by a single hypervisor.

Abstract: Methods and apparatus relating to processor extensions for execution of secure embedded containers are described. In an embodiment, a scalable solution for manageability function is provided, e.g., for UMPC environments or otherwise where utilizing a dedicated processor or microcontroller for manageability is inappropriate or impractical. For example, in an embodiment, an OS (Operating System) or VMM (Virtual Machine Manager) Independent (generally referred to herein as “OI”) architecture involves creating one or more containers on a processor by dynamically partitioning resources (such as processor cycles, memory, devices) between the HOST OS/VMM and the OI container. Other embodiments are also described and claimed.

Abstract: A processing device includes: a plurality of processing units that perform processes in accordance with data items read from a memory; a bus that connects the memory to the plurality of processing units; and a traffic monitor that monitors traffic on the bus with respect to the plurality of processing units, and when the traffic for one of the processing units that has been assigned access rights to the memory exceeds or reaches a prescribed upper limit, outputs a signal to the one of the processing units so as to reduce or suspend the traffic for the one of the processing units.

Abstract: An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

Abstract: A serial peripheral interface is configurable to operate in a I2S transmission mode. The interface has a transmission unit connected with external pins for data, bit clock, and left/right clock signal, a first-in-first-out (FIFO) buffer with a plurality of memory lines, and a control unit operable to read data portions from two memory lines, to assemble them into a transmission word, and to forward the assembled transmission word to the transmission unit, wherein the transmission unit is configured to serially transmit the assembled transmission word through the external data pin.

Abstract: An integrated circuit (IC) includes a first region being static and providing an interface between the IC and a host processor. The first region includes a first interconnect circuit block having a first master interface and a second interconnect circuit block having a first slave interface. The IC includes a second region coupled to the first region. The second region implements a kernel of a heterogeneous, multiprocessor design and includes a slave interface coupled to the first master interface of the first interconnect circuit block and configured to receive commands from the host processor. The second region also includes a master interface coupled the first slave interface of the second interconnect circuit block, wherein the master interface of the second region is a master for a memory controller.

Abstract: A data writing system is provided. A processing unit includes at least one core processor. The dynamic random access memory (DRAM) includes a user buffer storing data to be written to a storage device, a buffer cache and a direct memory access (DMA) buffer. The processing unit executes a plurality of write transactions for moving a portion of the data from the user buffer of the DRAM to the storage device via a first write path, and the remainder of the data from the user buffer of the DRAM to the storage device via a second write path. The first write path passes through the buffer cache of the DRAM, and the second write path does not pass through the buffer cache of the DRAM.

Abstract: Techniques for tracking, by a host system, virtual machine (VM) memory modified by a physical input/output (I/O) device that supports I/O virtualization are provided. In one embodiment, a hypervisor of the host system can receive a hardware interrupt from the physical I/O device, where the hardware interrupt indicates that a virtual function (VF) of the physical I/O device has completed a direct memory access (DMA) write to a guest memory space of a VM running on the host system. In response to the hardware interrupt, the hypervisor can invoke a function implemented by a physical function (PF) driver of the physical I/O device, where the function is configured to inspect the VF's state in order to identify memory portions modified by the DMA write. The hypervisor can then mark, in a hypervisor-level page table, one or more memory pages corresponding to the identified memory portions as dirty pages.

Abstract: A monolithic integrated circuit that supports multiple industrial Ethernet protocols, fieldbus protocols, and industrial application processing, providing a single hardware platform usable to build different automation devices/equipment implemented in an industrial network, such as controllers, field devices, network communication nodes, etc.

Abstract: Systems, methods, circuits and computer-readable mediums for peripheral sequencing using an access sequence are disclosed. In some implementations, a control register and status register in a peripheral are initialized with control data for selecting peripheral registers of the peripheral to be refreshed during an access sequence. For each peripheral register to be refreshed during the access sequence: a data register of the peripheral register is accessed; the peripheral register is refreshed; and the status register is updated with a current status of the access sequence. The access sequence is determined to be completed based on contents of the status register.

Abstract: A network subscriber comprises a plurality of individual functional units, each individual functional unit comprising an application interface. The network subscriber further comprises a network subscriber comprises at least a shared functional unit, a first interface for establishing a physical connection and a second interface for establishing a further physical connection.

Abstract: In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.

Abstract: An apparatus includes a multiport hub, a single bridge configured to communicatively couple together a plurality of hosts and to emulate a slave device to each such host, and a plurality of connection port. The apparatus further includes a configurable data path network coupled to the multiport hub, the single bridge, and the plurality of connection ports. The configurable data path network is configured to selectively provide for a connection port for which a host is detected, data communications through the single bridge between the multiport hub and the connection port, and for a connection port for which no host is detected, data communications between the multiport hub and the connection port that bypass the single bridge. Corresponding methods are also so disclosed.

Abstract: A network interface controller includes a media access controller and a host adapter. The host adapter includes a transmit route connected to receive an in-band packet from a host and further connected to transmit the in-band packet to the media access controller. The network interface controller also includes a sideband port controller connected to receive a sideband packet destined for a network from a sideband endpoint and further connected to transmit the sideband packet to the host adapter. The host adapter further includes a host buffer to store the in-band packet, a sideband buffer to store the sideband packet, and an arbiter connected to allow, at different times, the in-band packet to advance along the transmit route from the host buffer to the media access controller and the sideband packet to advance along the transmit route from the sideband buffer to the media access controller.

Abstract: A network interface controller includes a media access controller connected to receive an in-band packet and further connected to receive a sideband packet. The network interface controller includes a host adapter that includes a receive route connected to receive the in-band packet and the sideband packet from the media access controller, and further connected to transmit the in-band packet to a host. The network interface controller includes a sideband port controller comprising a sideband receive buffer. The host adapter further includes a first receive buffer to store the in-band packet and to store the sideband packet. The host adapter further includes an arbiter connected to allow, at a time, the in-band packet to advance from the first receive buffer along the receive route towards the host and further connected to allow, at a different time, the sideband packet to advance to the sideband receive buffer of the sideband port controller.

Abstract: A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.

Abstract: A PCIe Fabric that includes an IO tier switch, hub tier switches, and a target device connected to one of the hub tier switches. The IO tier switch is configured to receive a TLP from a client, make a determination that an address in the TLP is not associated with any multicast address range in the first IO tier switch and is not associated with any downstream port in the first IO tier switch, and, based on the determinations, route the TLP to the first hub tier switch via a upstream port on the IO tier switch. The hub tier switch is configured to make a determination that the TLP is associated with a multicast group, and, based on the determination, generate a rewritten TLP and route the rewritten TLP to a target device via a downstream port on the hub tier switch.

Abstract: A selectively transparent bridge facilitates a PCI device presenting itself to the host as a PCI-to-PCI bridge but selectively hiding and isolating hardware from the host bus. PCI configuration may be achieved through the standard PCI Express configuration mechanisms, but instead of configuring devices directly, a configuration processor in the selectively transparent bridge may intercept the configuration packets from the host, and create a virtual configuration to alter how the bus topology appears to the host. Devices are selectively hidden and managed by the configuration processor, resulting in simplified complexity and bus depth. Since the selectively transparent bridge appears to the host as a transparent bridge, no special drivers or resource preallocations are required, although the selectively transparent bridge fully supports special drivers and/or resource preallocations. Devices located/connected downstream of the bridge may therefore function with unmodified drivers.

Abstract: A system and method for facilitating communication. The system includes an adapter card and a first motherboard interface for coupling the adapter card to a motherboard. In some embodiments, the first motherboard interface is configured to transmit data between the adapter card and the motherboard. In some embodiments, the first motherboard interface is configured to supply power from the motherboard to the adapter card. The system further includes a second motherboard interface configured for communicative coupling of a component. In some embodiments, the adapter card comprises a portion configured for structurally coupling of the adapter card to the second motherboard interface. The system further includes an external interface for coupling the adapter card to an external environment of the system associated with the motherboard, where the external interface is configured to transmit data between the external environment of the system and the adapter card.

Abstract: A control method applied to an Operating-Mode Finite-State-Machine (OPFSM) arranged for deciding a behavior of a first port of an apparatus includes: controlling the OPFSM to enter a second local state from a first local state and controlling the first port to send a signal with a wakeup pattern to a link partner of the first port when the state of the OPFSM is the first local state, and a wakeup request bit is a first local value.

Abstract: A system and method for facilitating communication. The system includes an adapter card and a motherboard interface for coupling the adapter card to a motherboard. In some embodiments, the adapter card comprises an optical transmitter. In some embodiments, the motherboard interface is configured to transmit data between the adapter card and the motherboard. In some embodiments, the motherboard interface is configured to supply power from the motherboard to the adapter card. In some embodiments, the motherboard interface is a mini PCI express interface. The system may further comprise an external interface for coupling the adapter card to an external environment of a system associated with the motherboard. In some embodiments, the external interface is configured to transmit data between the external environment of the system and the adapter card.

Abstract: An interconnect assembly is disclosed herein. An example includes a cable including a first end and a cable head at the first end of the cable. The example also includes a wireless data transceiver disposed in the cable head to wirelessly communicate data to and from a device and a wireless power coupler disposed in the cable head to wirelessly supply power from the device to the wireless data transceiver.

Abstract: Provided is an application module provided with a stationary interface, and more particularly, an application module performing functions of a battery management system (BMS), which transceives data from an application module data control device or calls a service module included in a basic program (basic software (BSW) to increase compatibility regarding function execution among one or more modules.

Abstract: A receiver includes an analog-to-digital converter (ADC) module that receives a test signal via a transmission channel and provides a time domain representation of the test signal as received by the receiver, and a processor that determines a time domain representation of an impedance of the transmission channel based on the time domain representation of the test signal.