Abstract: A control apparatus for a voltage conversion apparatus includes: duty command signal generation means for generating a duty command signal corresponding to a duty ratio of switching elements carrier signal generation means for generating carrier signals corresponding to respective switching frequencies of the switching elements; switching control signal generation means for generating respective switching control signals of switching ON and OFF states of the switching elements, by comparing the duty command signal with the carrier signals; one arm driving control means for implementing one arm driving by alternatively turning on the first and second switching elements; and phase inverting means for bringing phases of portions, of the carrier signals, corresponding to switching at least right after arm switching, into a state where the phases are shifted from each other by 180 degrees between the first and second switching elements, at the time of the arm switching.

Abstract: The present application presents a power conversion control device that does not reduce electric power conversion efficiency. A mode judging section judges whether a direction of current flowing through an inductor has been reversed or not based on both an average value of current flowing through the inductor, the average value being calculated by an average current calculating section, and a difference (i.e peak current) between a maximum value and a minimum value of a current flowing through the inductor, the difference being calculated by a peak current calculating section. And then if the judging section has determined that the direction of current flowing through an inductor has been reversed, the power conversion control device makes the switching elements ON/OFF-operation corresponding to either one of a power running mode or an electric power regenerating mode.

Abstract: Transducer assemblies and associated methods are provided for facilitating alignment of ultrasonic transducers with respect to pipes onto which the transducers are installed. The transducer assembly can include a transducer housing having a track on along which the transducers can be slidingly engaged. The transducer assembly can include attachment structures having alignment features used to align the transducers parallel to the axial centerline of the pipe while ensuring that the reception/emission sides of the transducers are oriented normal to the outer surface of the pipe. In some embodiments a transducer assembly alignment system can be used to align two transducer assemblies on circumferentially opposite sides of a pipe.

Abstract: The control circuit includes: a first power supply, including a high-level output and a low-level output; a first circuit, including two inputs, a driver module and at least two braking switch units, the two inputs being respectively connected to the high-level output and the low-level output of the first power supply, and the driver module being in series connected to the at least two braking switch units, where the driver module includes two outputs that are the outputs of the control circuit; and braking circuits, which correspond to the braking switch units in a one to one manner, and are used to the control switching states of the braking switch units.

Abstract: A rotor position determination and tracking system for a dynamo electric machine includes a first AC power supply to inject a carrier wave into a main stator of the dynamoelectric machine and a second AC power supply to inject an excitation voltage or current into an exciter stator of the dynamoelectric machine. A plurality of current sensors and voltage sensors located at the exciter input lines sense current and voltage thereat. A first control logic receives the sensed current and voltage and outputs an estimated rotor position. A second control logic receives an estimated exciter field voltage or current rotating wave form angle and filtered sensed current or voltage signals from the first control logic and utilizes a known main stator carrier frequency to determine the rotor position. The rotor position is input into the first control logic to calibrate the first control logic for tracking of the true rotor position.

Abstract: Motor drive control apparatus and methods are presented for sensorless control of a driven motor using open loop current regulated control during low-speed operation and an EMF-based position observer for position estimation during higher speed operation, with zero feedback speed during low-speed open-loop operation and feedback speed estimated by the EMF-based observer during high-speed operation and with velocity mode control over the full speed range and mode control hysteresis for smooth transitions between open loop and EMF-based observer control.

Abstract: A motor driving circuit may include a timing detection circuit configured to receive a signal that corresponds to the Hall signal output from the Hall sensor, and to generate a timing signal which is asserted at a predetermined timing in every cycle of the Hall signal. The timing detection circuit may include a counter configured to perform a counting operation according to a clock signal; a reset unit configured to reset a count value of the counter for every cycle of the counter, to a value obtained by multiplying the count value obtained immediately before the reset operation by a negative coefficient; and a comparison unit configured to assert the timing signal at every timing at which there is a zero-crossing in the value of the counter.

Abstract: According to one embodiment, there is provided a generator excitation apparatus including a plurality of first power converters and a second power converter. The plurality of first power converters are electrically connected to windings of respective phases of rotors of a wound rotor type induction generator in which the windings of the rotors of the respective phases are electrically independent, and are configured to bidirectionally convert DC and AC. The second power converter is configured to bidirectionally convert DC and AC between DC sides of the first power converters and a three-phase DC power supply. The DC sides of the first power converters are electrically connected together to a DC side of the second power converter.

Abstract: A control apparatus for an AC motor includes a current sensor and an estimation section. The current sensor detects current flowing through one phase of the motor. The estimation section repeats an estimation process. In the estimation process, d-axis and q-axis current estimation values are calculated based on the presently detected current of the one phase and a previous current estimation value of another phase of the motor, and a present current estimation value of each phase is calculated based on smoothed values of the d-axis and q-axis current estimation values. The estimation section performs the estimation process based on a phase lag element. The phase lag element is a difference between the presently detected current and a previous current estimation value of the one phase or the previously detected current.

Abstract: A PWM output apparatus includes a calculating circuit configured to calculate an output width of a PWM output signal of a first signal and a second signal, which have phases different from each other, based on a command value of a PWM output. A comparing circuit compares the output width and a reference period which is set longer than a predetermined dead time period. A PWM output signal generating circuit outputs the PWM output signal to a dead time inserting block as a corrected PWM output signal, when a set/clear signal generating circuit outputs the set signal, and carries out a correction of setting the first signal of the PWM output signal to be inactive to output to the dead time inserting block as the corrected PWM output signal, when the set/clear circuit outputs the clear signal. The dead time inserting block corrects the corrected PWM output signal.

Abstract: A three-level power conversion apparatus can suppress fluctuation in a neutral point voltage even when operated as a reactive power regulator. The three-level power conversion apparatus is composed of first and second three-level converters connected to an AC power supply, positive side and negative side DC capacitors, a three-level inverter to drive an AC motor, and converter control unit for controlling the three-level converters. The converter control unit has first and second reactive current controllers for controlling so that reactive portions of input currents of each three-level converter become a prescribed reactive current reference, first and second neutral point voltage fluctuation suppressing units for controlling a PWM controller, to make a voltage difference of two DC capacitors zero, and an active current controller for supplying a prescribed circulating active current from one three-level converter to other three-level converter.

Abstract: An arrangement and a method are provided in connection with a solar energy system. The arrangement includes solar panels and a converter for converting the DC voltage from the solar panels. The converter is arranged inside a container or a similar closed structure. The arrangement includes means for producing heat from the energy produced by the solar panels. The means are arranged inside the container or a similar closed structure and are electrically connectable to the solar panels.

Abstract: An oscillator with a differential structure which is formed in an integrated circuit, including: a first transistor and a second transistor in each of which a drain electrode, a gate electrode, and a source electrode are sequentially arranged, a drain of the first transistor is connected with a gate of the second transistor through a first wiring, a drain of the second transistor is connected with a gate of the first transistor through a second wiring, and a first end of a source of the first transistor and a first end of a source of the second transistor are connected through a third wiring, and a second end of the source of the first transistor and a second end of the source of the second transistor are connected through a fourth wiring.

Abstract: A novel and useful LC-tank digitally controlled oscillator (DCO) incorporating a split transformer configuration. The LC-tank oscillator exhibits a significant reduction in area such that it is comparable in size to conventional ring oscillators (ROs) while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The oscillator incorporates an ultra-compact split transformer topology that is less susceptible to common-mode electromagnetic interference than regular high-Q LC tanks which is highly desirable in SoC environments. The oscillator, together with a novel dc-coupled buffer, can be incorporated within a wide range of circuit applications, including clock generators and an all-digital phase-locked loop (ADPLL) intended for wireline applications.

Abstract: An apparatus having a substrate with an inductor, a first die and a second die is disclosed. The first die may be (i) mounted on the substrate, (ii) configured to vary a frequency of a signal in the inductor, and (iii) fabricated with multiple first masks. The second die may be (i) mounted on the substrate, (ii) configured to excite the signal, and (iii) fabricated with multiple second masks. A particular one of the first masks generally has several designs that customize the first die to several configurations respectively. A particular one of the second masks may have several designs that customize the second die to several configurations respectively. The first die, the second die and the inductor may form a voltage-controlled oscillator. A selected first design and a selected second design generally establish multiple performances of the voltage-controlled oscillator.

Abstract: A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal.

Abstract: A power amplifier includes an amplification transistor which performs power amplification, a bias circuit which outputs a bias voltage to a base of the amplification transistor, a control terminal to which a control voltage is applied for controlling switching between an operating state and a stopping state of the bias circuit, and a bias voltage adjustment circuit connected to the control terminal. The bias voltage adjustment circuit includes a variable capacitance element which is connected to the control terminal and whose capacitance value decreases as the control voltage increases, a discharge circuit which discharges electric charge accumulated in the variable capacitance element to the control terminal, and a control circuit which is connected to the bias circuit and controls the bias voltage. The bias voltage adjustment circuit outputs, to the bias circuit, a bias voltage adjustment signal which increases the bias voltage for a predetermined period after the control voltage is applied.

Abstract: The linearity of a power amplifying module employing an envelope tracking scheme is improved. The power amplifying module includes a first bipolar transistor having a base to which a first radio frequency signal is input and an emitter grounded, and a second bipolar transistor having a base to which a first constant voltage is applied, a collector to which a first power supply voltage is applied, the first power supply voltage adapted to vary in accordance with an amplitude of the first radio frequency signal, and an emitter connected to a collector of the first bipolar transistor. The second bipolar transistor is configured to output a first amplified signal, obtained by amplifying the first radio frequency signal, from the collector of the second bipolar transistor.

Abstract: A multi-way Doherty power amplifier, DPA, is disclosed, comprising a first path comprising a carrier amplifier or at least one carrier amplifier segment partitioned from the carrier amplifier; a second to N-th paths each comprising at least one carrier amplifier segment and/or at least one peaking amplifier segment partitioned from a peaking amplifier; and a power splitter for splitting an input power signal to each of the at least one carrier amplifier segment and/or at least one peaking amplifier segment in a same path, wherein N is an integer not less than 2; a signal preparation unit configured for generating separately input power signal for the first path and each of the second path to N-th paths; and an impedance inverting network configured for combining output signal power from each path. The performance of each amplifier cell can be maximized independently without any compromises made for each other.

Abstract: An embodiment described herein includes a low noise amplifier (LNA) including a plurality of separate input terminals, a plurality of transistors, and an output network coupled to a first reference terminal and a single output of the LNA. Each transistor includes a conduction path and a control terminal coupled to one of the plurality of separate input terminals. The output network is also coupled to the conduction path of each of the plurality of transistors.

Abstract: A device includes a load circuit configured to receive an amplified communication signal, the load circuit having a center tapped inductor structure configured to divide the amplified communication signal into a first portion and a second portion, the load circuit configured to resonate at a harmonic of the amplified communication signal.

Abstract: Systems and methods for compensating for a non-linear characteristic of a non-linear filter in a transmit chain of a transmitter using predistortion are disclosed. In one embodiment, a transmitter includes a power amplifier configured to amplify a radio frequency input signal to provide an amplified radio frequency signal, a non-linear filter configured to filter the amplified radio frequency signal to provide an output signal of the transmitter, and a predistorter configured effect predistortion of the amplified radio frequency signal, where the predistortion compensates for a non-linear characteristic of the non-linear filter. In this manner, the output signal is as if the non-linear filter were a linear, or substantially liner, filter. The predistortion applied by the predistorter may be fixed or adaptive.

Abstract: This disclosure relates to a harmonic termination circuit that is separate from a load line. In one embodiment, the load line is configured to match an impedance at the power amplifier output at a fundamental frequency of the power amplifier output and the harmonic termination circuit is configured to terminate at a phase corresponding to a harmonic frequency of the power amplifier output. According to certain embodiments, the load line and the harmonic termination circuit can be electrically coupled to the power amplifier output external to a power amplifier die via different output pins of the power amplifier die.

Abstract: A current amplifier and a transmitter using the same. The current amplifier includes: a first transistor having a gate coupled to a former-stage circuit, a drain coupled to a current source, and a source biased at a constant voltage level; a second transistor having a gate coupled to the current source and having a source and a drain; a first impedance circuit coupled between the gate of the first transistor and the source of the second transistor; and a second impedance circuit coupled between the source of the second transistor and a ground terminal. The current amplifier receives an input current from the former-stage circuit and generates an output current at the drain of the second transistor. Note that no current source is connected to the source of the first transistor.

Abstract: The present disclosure provides a buffer circuit comprising a plurality of operational amplifiers and a switch module. Each operational amplifier forms a buffer. The operational amplifier has an output stage. The stage has a first transistor and a second transistor. The first transistor and the second transistor are connected to an output terminal. The first transistor has a first control terminal. The second transistor has a second control terminal. The switch module is connected to the first control terminal of the first transistor and the second control terminal of the second transistor. The switch module connects together at least two of the first terminals of the first transistor according to a control signal. The switch module connects together at least two of the second terminals of the second transistor according to the control signal.

Abstract: A power switch 307a is provided between a bias generation circuit 301 and a high potential power source, or a power switch 307b is provided between the bias generation circuit 301 and a low potential power source. A bias potential Vb output from the bias generation circuit 301 is held by a potential holding circuit 300. The bias potential Vb held by the potential holding circuit 300 is input to a bias generation circuit 301a, and a bias potential Vb2 output from the bias generation circuit 301a on which an input signal IN is superimposed is input to an amplifier circuit 302. The potential holding circuit 300 is constituted of a capacitor 306 and a switch 305 formed of, for example, a transistor with a low off-state current that is formed using a wide band gap oxide semiconductor. Structures other than the above structure are claimed.

Abstract: Provided is a differential amplifier including: an operational amplifier (OP AMP) having an inverting input, a non-inverting input, an inverting output, and a non-inverting output, a first feedback capacitor connected to the non-inverting input and the inverting output. A second feedback capacitor connected to the inverting input and the non-inverting output, a first four-terminal transistor connected to the non-inverting input and the inverting output. A second four-terminal transistor connected to the inverting input and the non-inverting output. One of source and drain of the first transistor and a gate thereof are connected to the inverting output, the other one of the source and drain and a bulk terminal are connected to the non-inverting input, one of source and drain of the second transistor and a gate thereof are connected to the non-inverting output, and the other one of the source and drain terminals and a bulk terminal are connected to the inverting input.

Abstract: A differential amplifier may, when connected to a positive or negative supply voltage and to a ground voltage, provide a differential pair of outputs signals at a differential output that are an amplification of a differential pair of input signals at a differential input. A differential input stage may receive the differential pair of input signals from the differential input and may include a first transistor associated with one of the input signals and a second transistor associated with the other input signal. A differential output stage may generate the differential pair of output signals at the differential output and may include a third transistor associated with one of the output signals and a fourth transistor associated with the other output signal. The first, second, third, and fourth transistors may be all P type or all N type.

Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.

Abstract: A method, system and apparatus for voice coil protection using damping are provided. At a device and/or a system comprising: a processor; a sound transducer comprising a voice coil; a power supply; an amplifier in communication with the voice coil; and a circuit configured to apply an electromotive force (“EMF”) to the voice coil under control of the processor, the amplifier is placed into a standby state. When the amplifier is in the standby state, the circuit is controlled to apply the EMF to the voice coil using the power supply so that the voice coil has restricted excursion.

Abstract: A resistor network comprises one or more switched resistor branches. Each switched resistor branch comprises a first resistor connected in series with a first switch, wherein a first terminal of the first resistor is connected to the input terminal of the resistor network, a second terminal of the first resistor is connected to a first terminal of the first switch forming a middle node, and a second terminal of the first switch is connected to the output terminal of the resistor network. Each switched resistor branch further comprises a second resistor connected in series with a second switch, wherein the series connected second resistor and second switch is connected between the middle node and a third terminal of the one or more switched resistor branches. The resistor network further comprises a third resistor connected between the input and output terminals of the resistor network.

Abstract: An arrangement of overlapping filter banks comprises a synthesis stage and an analysis stage. The synthesis stage receives a first signal segmented into time blocks and outputs, based thereon, an intermediate signal to be received by the analysis stage forming the basis for the computation of a second signal segmented into time frames. In an embodiment, the synthesis stage is operable to release an approximate value of the intermediate signal in a time block located L?1 time blocks ahead of its output block, which approximate value is computed on the basis of any available time blocks of the first signal, so that the approximate value contributes, in the analysis stage, to the second signal. The delay is typically reduced by L?1 blocks. Applications include audio signal processing in general and real-to-complex conversion in particular.

Abstract: A hybrid, translinear amplifier has at least one gain stage including first and second gain transistors, at least a first load transistor electrically coupled to the first gain transistor and at least a second load transistor electrically coupled to the second gain transistor, and load resistors electrically coupled to the load transistors. A hybrid, translinear amplifier with selectable gain has a first hybrid, translinear amplifier cell having at least first and second load transistors, each load transistor having a load resistor, at least one additional hybrid, translinear amplifier cell having at least third, fourth, fifth and sixth load transistors, each load transistor having a load resistor, at least two switches electrically coupled to the amplifier cells to allow selection of one of the amplifier cells, and a differential output signal having a gain corresponding to a selected amplifier cell.

Abstract: A device or system for transmission and reception for voice or data communication applications. The device or system is capable of duplex operation and adapted to operate in an environment using a plurality of frequency bands. The present disclosure also relates to a communication means including a transmitter and receiver arrangement and to antennas.

Abstract: An echo caused by sound leakage from a housing that vibrates due to a vibrating body is reduced. An electronic device (1) according to the present invention includes a piezoelectric element (30), a vibrating plate (10) that vibrates due to the piezoelectric element (30), microphones (42, 43), and an equalizer (44), the electronic device (1) causing the vibrating plate (10) to generate air-conducted sound and vibration sound that is transmitted by vibrating a part of a human body. The equalizer (44) makes a low-range emphasis setting, to emphasize a low frequency range more than a high frequency range of the air-conducted sound, when the volume of the air-conducted sound collected by the microphones (42, 43) exceeds a predetermined threshold.

Abstract: An impedance matching device includes a matching element array unit with a matching element array to which a transmission pulse and a received pulse pass, an extraction/calculation unit extracting pulse information from the transmission pulse and the received pulse, calculating impedance values corresponding to the pulse information, and calculating an impedance value having best response characteristics of the received pulse with respect to the transmission pulse as a matching impedance value, an array control unit routing the matching element array unit according to the matching impedance value, a first converter converting a frequency of the transmission pulse into a carrier frequency and outputting the transmission pulse to the matching element array unit, a second converter converting the carrier frequency into a low frequency, and a converter control unit outputting a signal for controlling the frequency converting of the first converter and the second converter.

Abstract: An acoustic resonator comprising a substantially horizontal membrane of piezoelectric material with upper and lower metal electrodes on its upper and lower faces, said membrane being attached around its perimeter to the inner side walls of a rectangular interconnect frame by an attaching polymer, the side walls of the package frame being substantially perpendicular to the membrane and comprising conducting vias within a dielectric matrix, the conducting vias running substantially vertically within the side walls, the metal electrodes being conductively coupled to the metal vias by a feature layer over the upper surface of the membrane and top and bottom lids coupled to top and bottom ends of the interconnect frame to seal the acoustic resonator from its surroundings.

Abstract: A piezoelectric thin film resonator includes: a substrate; a piezoelectric film that is located on the substrate and includes a first film made of an aluminum nitride film containing an additive element and second films located on an upper surface and a lower surface of the first film and made of an aluminum nitride film containing the additive element at a concentration lower than that of the first film; and a lower electrode and an upper electrode that are located to sandwich the piezoelectric film.

Abstract: Methods of designing band-pass filters and filters are disclosed. A baseline filter design meeting first design criteria may be established, the baseline filter design including a plurality of series surface acoustic wave resonators and a plurality of shunt surface acoustic wave resonators, each surface acoustic wave resonator having a respective resonant frequency. A performance metric based on an input impedance of the baseline filter design over a pass band may be determined. One or more alternate filter designs may be established and respective performance metrics determined, each alternative filter design established by reordering the resonant frequencies of two or more of the plurality of series surface acoustic wave resonators and/or two or more of the plurality of shunt surface acoustic wave resonators. A final filter design may be selected from the baseline design and the one or more alternate filter designs based on the respective performance metrics.

Abstract: An elastic wave filter device includes a transmission elastic wave filter chip and a reception elastic wave filter chip. The transmission elastic wave filter chip includes an insulating support substrate, a piezoelectric layer directly or indirectly supported by the support substrate, and an IDT electrode in contact with the piezoelectric layer. The reception elastic wave filter chip includes a piezoelectric substrate and an IDT electrode provided on the piezoelectric substrate. The thermal conductivity of the support substrate is higher than the thermal conductivity of either of the piezoelectric layer and the piezoelectric substrate.

Abstract: The present invention discloses a gain-boosted N-path SC bandpass filter (GB-BPF) with a number of sought features. It is based on a transconductance amplifier (Gm) with an N-path SC branch as its feedback network, offering 1) double RF filtering at the input and output of the Gm in one step; 2) customized passband gain and bandwidth with input-impedance match, and 3) reduced physical capacitance thanks to the loop gain offered by Gm. All have been examined using a RLC model of the SC branch before applying the linear periodically time-variant (LPTV) analysis to derive the R, L and C expressions and analytically study the harmonic selectivity, harmonic folding and noise. The latter reveals that: 1) the noise due to the switches is notched at the output, allowing smaller switches to save the LO power; and 2) the noises due to the source resistance and Gm are narrowband at the output, reducing the folded noise during harmonic mixing.

Abstract: A series-structure, parallel-structure and combined structure of micro-step resistance network circuits is disclosed. Micro-step resistance is maintained, while the programming switches on-state resistance impact and its VC and TC effect are minimized. The programming switch area size is greatly reduced as compared to conventional systems.

Abstract: A first transistor and a second transistor cascade-connected, a wiring which connects a drain of the first transistor and a gate of the second transistor, a capacitor whose one terminal is connected between the first transistor and the second transistor cascade-connected and whose other terminal is grounded, and a control circuit are included. The control circuit adjusts an inductance value by controlling a capacitance value of the capacitor or gate voltage of the first transistor or the second transistor.

Abstract: This document discusses, among other things, a resistance multiplier configured to provide a more specific and controllable resistance value, the resistance multiplier including an amplifier configured to control a resistance across a first transistor using a received reference resistance value and to control a resistance across a second transistor using the resistance across the first transistor and a relationship between the first and second transistors.

Abstract: A method and system for the design and implementation of an optimally factored interpolated finite impulse response (IFIR) filter is presented. Techniques used to increase the implementation efficiency of the filter include joint sequencing of the filter stages, use of an nested IFIR filter, taming of a stage by relocation of that stage, fusing two or more stages together to form a single stage, and manual manipulation of a post-stage multiplier. IFIR filters using this approach may be realized as low pass filters or high pass filters, and in either analog or digital form.

Abstract: A circuit system having at least two inverter modules connected in parallel, each of which includes an inverter circuit having power semiconductor circuit breakers and a gate driver circuit for controlling the power semiconductor circuit breakers; the gate driver circuit of a first inverter module includes a signal transmission circuit via which a control signal is transmittable from a low-voltage side to a high-voltage side, and a first driver output terminal which is electrically connected to the first driver input terminals of the gate driver circuits of the inverter modules connected in parallel, and via which the high-voltage side control signal or a control signal deduced therefrom is transmittable to the gate driver circuits of the inverter modules connected in parallel. The power semiconductor circuit breakers of the inverter circuits of the inverter modules, connected in parallel to the first inverter module, are controlled based on the transmitted control signal.

Abstract: A method of processing an amplitude-modulated analog signal at a carrier frequency Fc comprises: digitizing the analog signal to produce an input bit stream that represents the amplitude of the analog signal; generating an in-phase reference bit stream that is synchronous to the carrier frequency Fc and represents an in-phase digital reference signal substantially in the form of a sine and/or cosine wave; and multiplying the input bit stream with the in-phase reference bit stream to produce an output bit stream representing the amplitude modulation of the analog signal.

Abstract: A ramp generator circuit includes: a reference signal generator circuit which generates a ramp waveform having a slope obtained by multiplication using a power of 2 according to a value of a higher order bit of a gain control signal; a clock control circuit which selectively outputs 2^m kinds of fractional-N clocks according to one of 2^m (natural number) areas obtained by dividing a code range represented by a lower order bit, when a negative gain is set; and a variable gain circuit which sets a ramp waveform according to the value of the gain control signal, and sets a ramp signal amplitude in each area so that a period ratio between ramp driving clocks for adjacent areas and a ratio between an amplitude of a ramp signal when the standard gain is set and a largest amplitude of a ramp signal are equal.

Abstract: A delay circuit of a semiconductor apparatus includes a control signal generation block configured to output a control signal having an analog voltage level in response to an input signal, and an input/output block configured to delay the input signal by a delay amount based on the analog voltage level of the control signal, and output a resultant signal.

Abstract: An integrated circuit 2 includes a transistor 26 which has a normal switching speed arising during normal operations of that transistor that apply electrical signals within normal ranges. If it is desired to change the speed of operation of the transistor, then speed tuning circuitry 12 applies a tuning electrical signal with a tuning characteristic outside of the normal range of characteristics to the transistor concerned. The tuning electrical signal induces a change in at least one of the physical properties of that transistor such that when it resumes its modified normal operations the switching speed of that transistor will have changed. The tuning electrical signal may be a voltage (or current) outside of the normal range of voltages applied to the gate of a transistor so as to induce a permanent increase in the threshold of that transistor and so slow its speed of switching. Temperature of a transistor may also be controlled to induce a permanent change in performance/speed.