Abstract: The present invention provides a clock signal controller structure. The invention allows for the large-skew clock signals to be converted into small-skew clock signals. The technical solution of the present invention may be adopted to synchronize two large-skew clock signals.

Abstract: The highest voltage of a power supply voltage, a ground potential, and a signal voltage is output as a selection voltage from a terminal on the output side. In this case, terminals on the input side and the terminal on the output side are connected to each other through MOS transistors in the ON state. Therefore, it is possible to suppress a voltage drop due to a parasitic diode of each MOS transistor.

Abstract: An input apparatus may include a pulse width control circuit, a reception circuit, and a latch circuit. The pulse width control circuit may be configured to generate a pulse width control signal by performing a logical operation on a pulse width detection signal and a clock signal. The reception circuit may be configured to selectively provide a received input signal as a period signal on the basis of the clock signal and the pulse width control signal. The latch circuit may be configured to provide an output signal by inverting the period signal, and provide the output signal as the pulse width detection signal in response to the clock signal.

Abstract: A solid state relay and method for enabling and disabling power to a load are disclosed. A fast turn-on circuit and fast turn-off circuit receive control signals in an isolated manner. The control signals allow only one of the fast turn-on circuit and fast turn-off circuit to be enabled at a time. A power switching circuit that enables power to be supplied to a load when the fast turn-on circuit is enabled and the fast turn-off circuit is disabled state, and disables the power from being supplied to the load when the fast turn-on circuit is disabled and the fast turn-off circuit is enabled. A power supply circuit provides isolated power used by the fast turn-on and fast turn-off circuits to drive or discharge a gate in the power switching circuit.

Abstract: There is provided a semiconductor device capable of preventing the passage of current that is unexpected in a circuit operation even in the case of reverse connection, thus ensuring higher safety. The semiconductor device has a switch circuit which includes: a first transistor; a second transistor having a drain thereof connected to a drain of the first transistor, a source and a back gate thereof connected to a back gate of the first transistor, and a gate thereof connected to a source of the first transistor; and a third transistor having a drain thereof connected to the source of the first transistor, a source and a back gate thereof connected to the back gate of the first transistor, and a gate thereof connected to the drain of the first transistor.

Abstract: Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, insertion loss and parasitic capacitance common to thermometer-coded step devices having equivalent range and resolution.

Abstract: A level jump reset IC design circuit is provided, comprising a reset IC, a reset circuit, and a switching circuit. The reset circuit and the switching circuit both are connected to signal input pins of the reset IC. The level jump reset IC design circuit can make mobile phones effectively realize reset shutdown and restart, and make the mobile phones enter a Recovery model. Reset pulse time can be set by a user according to requirements, so that the user can distinguish two different operations of reset shutdown and restart. When the model phones enter the Recovery model, the switching circuit deactivates the reset circuit, so the mobile phones can enter the Recovery mode normally and effectively.

Abstract: A method and apparatus is provided for outputting a reset signal during power-up until two conditions are satisfied. In one embodiment, the method and apparatus includes a voltage detector that provides a first output (“VO1”) when an output voltage of a regulator (“VREG”) exceeds a threshold voltage, thereby satisfying a first condition, a comparator receiving a first input voltage and a second input voltage, the comparator providing a second output (“VO2”) when the first input voltage exceeds the second input voltage, thereby satisfying a second condition, and a release circuit that outputs the reset signal unless the voltage detector provides VO1 while the comparator provides VO2.

Abstract: An electronic switch includes a load path connected in series with the load and a drive terminal for receiving a drive signal. The electronic switch is operable to switch between a first operation state and a second operation state dependent on the drive signal. In a first switching cycle, the electronic switch is switched from the first operation state to the second operation state and a voltage across the load is evaluated during the first switching cycle in order to obtain a measured switching profile. The measured switching profile is compared with a reference profile. A drive profile dependent on the comparison is provided. The drive profile is used to drive the electronic switch in a second switching cycle after the first switching cycle. At least two drive parameters are used at different times in the at least one second switching cycle to drive the electronic switch.

Abstract: A clock control device and method are provided. The clock control device includes a stable time controller which receives an operational condition and generates an expiration counting value based on the operational condition; a stable time counter which receives the expiration counting value and activates a clock gating enable signal after a count value of the stable time counter is equal to the expiration counting value; a clock gating cell which transmits a clock signal after receiving the clock gating enable signal; and an oscillator which generates an oscillator clock signal and transmits the oscillator clock signal to the clock gating cell and the stable time counter.

Abstract: The switching current control circuit includes a switching pulse supply circuit, a comparator circuit, and analog circuit unit, a digital circuit unit, etc. The A/D converter (2) detects a load current in an ON period of a switching pulse as a detected current, and converts it into digital data. The arithmetic control circuit (3) calculates a lower limit of the detected current for providing a timing of switching from OFF to ON of the switching pulse, based on the converted data. Continuation/discontinuous modes are determined whether the lower limit is equal to or greater than 0.

Abstract: Methods, systems, circuits, and devices for power-packet-switching power converters using bidirectional bipolar transistors (BTRANs) for switching. Four-terminal three-layer BTRANs provide substantially identical operation in either direction with forward voltages of less than a diode drop. BTRANs are fully symmetric merged double-base bidirectional bipolar opposite-faced devices which operate under conditions of high non-equilibrium carrier concentration, and which can have surprising synergies when used as bidirectional switches for power-packet-switching power converters. BTRANs are driven into a state of high carrier concentration, making the on-state voltage drop very low.

Abstract: Methods, systems, circuits, and devices for power-packet-switching power converters using bidirectional bipolar transistors (BTRANs) for switching. Four-terminal three-layer BTRANs provide substantially identical operation in either direction with forward voltages of less than a diode drop. BTRANs are fully symmetric merged double-base bidirectional bipolar opposite-faced devices which operate under conditions of high non-equilibrium carrier concentration, and which can have surprising synergies when used as bidirectional switches for power-packet-switching power converters. BTRANs are driven into a state of high carrier concentration, making the on-state voltage drop very low.

Abstract: A method of electrically coupling a first node and a second node of a switch cell includes biasing the second node and a bias node of the switch cell at a direct current (DC) voltage level of a second voltage level greater than a first voltage level. A first switch unit coupled between the first node and the second node is tuned on by a first control signal having a third voltage level. The third voltage level being greater than the first voltage level, and a difference between the third voltage level and the first voltage level is about twice a difference between the second voltage level and the first voltage level. Also, a second switch unit coupled between the second node and the bias node is turned off by a second control signal having the first voltage level.

Abstract: A virtual world processing apparatus and method. Information on sensor capability is converted to binary data and then transmitted, or converted to eXtensible Markup Language (XML) data, or the XML data is further converted to binary data and then transmitted. Accordingly, data transmission rate may be increased and a low bandwidth may be used. In a data-receiving adaptation real world to virtual world (RV) engine, complexity of the adaptation RV engine may be reduced by omitting an XML parser.

Abstract: An impedance calibration apparatus of a semiconductor integrated circuit includes: a D/A conversion unit configured to receive a code and generate an analog voltage depending on the code; a virtual code voltage generation unit configured to detect a level of the analog voltage and generate a plurality of virtual code voltages based on the level of the analog voltage; a comparison unit configured to receive the plurality of virtual code voltages and a reference voltage as inputs, and compare the plurality of virtual code voltages with the reference voltage to generate a plurality of comparison signals; and a code generation unit configured to receive the plurality of comparison signals and generate the code using the plurality of comparison signals.

Abstract: An embodiment of the invention provides an isolation cell for isolating a second power domain from a first power domain. The isolation cell includes an input terminal capable of receiving a first signal of the first power domain, an output terminal capable of outputting an output signal with a predetermined logic state to the second power domain, a first power terminal and a second power terminal. The first power terminal is capable of receiving a voltage from a power source, the power source is different from a first power source of the first power domain, and the isolation cell is powered by the voltage.

Abstract: A circuit arrangement may be provided including a level shifting stage configured to be coupled to a first reference voltage and a second reference voltage. The circuit arrangement may also include a first input electrode in electrical connection with the level shifting stage for coupling a first input voltage and a second input electrode in electrical connection with the level shifting stage for coupling a second input voltage. The level shifting stage may be configured to generate an output voltage above a predetermined output level at the output node due to the first reference voltage when the first input voltage is in the first logic state and the second input voltage is in the second logic state. The circuit arrangement may also include a feedback circuit coupled to the output stage and the level shifting stage and a voltage stabilization circuit coupled to the level shifting stage.

Abstract: The invention relates to an input circuit arrangement (11), which is designed for operation either in a first or a second operating mode (A, B) and comprises a connection (13) for supplying a connection signal (SWI) and a detection circuit (14). The detection circuit (14) is coupled on the input side to the connection (13) and is designed to put the input circuit arrangement (11) into an operating mode from a group comprising the first and second operating modes (A, B) depending on the steepness of a change of the connection signal (SWI).

Abstract: An internal voltage compensation circuit is provided which includes a power up signal generator configured to generate a power up signal, a select signal generator configured to compare a level of a first external voltage with a level of a second external voltage to generate first and second select signals, wherein the second select signal is generated in response to the power up signal, and a voltage compensation unit configured to electrically connect an internal voltage to the first external voltage or the second external voltage in response to the first and second select signals.

Abstract: A buffer circuit comprising a capacitor, the capacitor comprising a first terminal and a second terminal, an input signal being coupled to the first terminal; a first buffer stage coupled to the second terminal of the capacitor such that the input signal is capacitively coupled to the first buffer stage; and, a pulse generator coupled to control the first buffer stage, the pulse generator being configured to generate a control pulse corresponding to a hold time of the first buffer stage such that the buffer circuit detects a transition of the input signal during the hold time.

Abstract: A 3D field programmable gate array (FPGA) system, and method of manufacture therefor, includes: a field programmable gate array (FPGA) die having a configurable power on reset (POR) unit; a heterogeneous integrated circuit die coupled to the FPGA die; and a 3D power on reset (POR) output configured by the configurable POR unit for initializing the FPGA die and the heterogeneous integrated circuit die.

Abstract: A counter circuit includes a lower count signal generation unit suitable for generating a lower bit, an upper count signal generation unit suitable for generating an upper bit, and a control unit suitable for determining a counting route in response to a control signal and controlling the lower and upper count signal generation units based on a determined route, wherein in a first route, the upper bit is generated in response to the lower bit, and in a second route, the lower bit is generated in response to the upper bit.

Abstract: A semiconductor apparatus includes a clock division block suitable for generating a first internal clock and a second internal clock having a first phase difference at which active sections of the first internal clock and the second internal clock overlap with each other by dividing a phase of a source clock at a predetermined rate, and a phase detection block suitable for outputting detection result information generated by combining a result obtained by detecting a phase of the first internal clock at a predetermined edge of a strobe signal and a result obtained by detecting a phase of the second internal clock at the predetermined edge of the strobe signal.

Abstract: A data processor including: a reference signal generator to generate a reference signal, used to convert a level of an analog processing signal into digital data; a comparator to compare the processing signal with the reference signal; and a count period controller to perform a real number count operation or a complement number count operation, on the basis of the comparison result of the comparator. The count period controller independently controls the real number count operation and the complement number count operation of the counter on the basis of a predetermined criterion.

Abstract: A system and method for transmitting includes a plurality of multiplexers each configured to combine a pseudo random bit sequence (PRBS) with at least one input stream according to the data control clock. At least one storage device is coupled to an output of each of the plurality of multiplexers and is configured to latch data according to the data control clock. An output multiplexer is coupled to each of the at least one storage device and is configured to select between storage paths according to the data serializer clock. A PRBS checker is configured to compare a PRBS pattern on an output of the output multiplexer with a predicted PRBS pattern. A phase rotator is configured to adjust the data serializer clock based upon the comparison of the PRBS checker to reduce latency of the transmitter.

Abstract: An oscillating signal generator includes: a controllable oscillator arranged to output an oscillating signal according to a control signal and a band adjusting signal; a control circuit arranged to generate a continuous signal having a specific slew-rate when the control signal reaches a boundary of a control signal interval; and a current mirror arranged to generate the band adjusting signal according to at least the continuous signal.

Abstract: A local oscillator communicates a signal of relatively low frequency across an integrated circuit to the location of a mixer. Near the mixer, a frequency-multiplying SubHarmonically Injection-Locked Oscillator (SHILO) receives the signal and generates therefrom a higher frequency signal. If the SHILO outputs I and Q quadrature signals, then the I and Q signals drive the mixer. If the SHILO does not generate quadrature signals, then a quadrature generating circuit receives the SHILO output signal and generates therefrom I and Q signals that drive the mixer. In one advantageous aspect, the frequency of the signal communicated over distance from the local oscillator to the SHILO is lower than the frequency of the I and Q signals that drive the mixer locally. Reducing the frequency of the signal communicated over distance can reduce power consumption of the LO signal distribution system by more than fifty percent as compared to conventional systems.

Abstract: Provided is a sensor device including: a sensor unit converting a voltage of a periodically switched capacitor into a pulse signal by referring to a clock signal to provide the pulse signal as a first sensing signal; and a high-resolution analog to digital converter (ADC) amplifying a period of the first sensing signal 2n times (n is an integer), amplifying a period of the clock signal 2n?1 times, and generating a second sensing signal where a switching time of the capacitor is removed by removing the amplified clock signal from the amplified first sensing signal.

Abstract: A method and apparatus are configured to receive at a control input of an analog to digital converter (ADC) circuit, from a control output of a control circuit, a first instance of control information that indicates a conversion characteristic of the ADC, wherein the conversion characteristic is one of a first conversion rate and a first conversion resolution, to provide at a status output of the ADC status information regarding the conversion of a first analog signal by the ADC circuit, to receive at the control input of the ADC a second instance of the control information that adjusts the conversion characteristic to allocate a first portion of an ADC circuit bandwidth of the ADC circuit to continuing receiving the first analog signal and to allocate a second portion of the ADC circuit bandwidth to receiving a second analog signal.

Abstract: In some embodiments, a digital-to-analog converter (DAC) system includes an output segment, a main branch, first and second edge segments, and a sub-segment. The output segment includes secondary switches that selectively connect conductive paths to an output. The main branch includes unit resistance elements, each including a resistor and a switch. The first and second edge segments each include a respective group of secondary switches that selectively connect a respective conductive path to a unit resistance element. The sub-segment includes terminal resistors connected to at least one conductive path and includes main switches that selectively connect respective terminal resistors to the unit resistance element. The main switches and the unit resistance element switches use a single switch design. The DAC system may have an improved differential non-linearity (DNL), as compared to a DAC system that does not include the unit resistance element switches or the first and second edge segments.

Abstract: There is provided a pipelined A/D converter in which plural stages Stage 1 to Stage N each including an MDAC (i.e., Multiplying DA Converter) are connected. The pipelined A/D converter is configured with a Gain-AMP (12) included in the MDAC for the SPM, MOS transistors (Mx1) and (Mx2) as a differential pair having output ends connected to a sampling capacitor CsI on a subsequent stage, MOS transistors (My1) and (My2) as a load unit connected to the differential pair, a current source (I3) configured to supply a current to the MOS transistors (Mx1) and (Mx2) as the differential pair, and current sources (I1) and (I2) configured to adjust the current flown across the MOS transistors (My1) and (My2) as the load unit.

Abstract: A converter may generate an analog output that is representative of a time-encoded signal. The circuit may include an input port receiving the time-encoded signal; a time-encoded to digital converter coupled to the input port; and a digital-to-analog converter coupled to the time-encoded to digital converter.

Abstract: A hardware accelerator receives a request to decompress a data stream that includes multiple deflate blocks and multiple deflate elements compressed according to block-specific compression configuration information. The hardware accelerator identifies a commit point that is based upon an interruption of a first decompression session of the data stream and corresponds to one of the deflate blocks. As such, the hardware accelerator configures a decompression engine based upon the corresponding deflate block's configuration information and, in turn, recommences decompression of the data stream at an input bit location corresponding to the commit point.

Abstract: An LDPC decoder includes a check node processor. The check node processor is configured to implement an n-degree check node, where n is a predetermined number. The degree of a check node is the number of edges coupled to the check node. The LDPC decoder also includes a plurality of n time division multiplexers coupled to the check node processor to couple different edge connection input values to the check node processor at different times so as to allow the check node processor to be time division multiplexed for use in implementing different check nodes with the same check node processor. Each of the multiplexers is configured to provide no more than one edge connection input value to the check node processor at any given time. Each edge connection is used to implement an edge into a check node.

Abstract: A method, system, and computer program product for performing robust, parallel data transfer by a processor device. Data is segmented into k-bit segments, where k?1. The k-bit segments are convolution encoded, using m?1 stages of delay. The n output streams are transmitted in parallel for increased effective data rate, where n>k. The n output streams are received. The n output streams are exclusive-or'ed with pathing allowed by the convolution encoding, in a trellis-decoding diagram. Error-corrected data is identified as an overall path in the trellis-decoding diagram with zero Hamming radius.

Abstract: A quadratic permutation polynomial (QPP) interleaver is described for turbo coding and decoding. The QPP interleaver has the form: ?(n)=ƒ1n?ƒ2n2 mod K, where the QPP coefficients ƒ1 and ƒ2 are designed to provide good error performance for a given block length K.

Abstract: Disclosed are a multimode decoder method and device. The method includes: interleaving pre-stored to-be-decoded data to obtain an interleaving address; and based on the interleaving address, using a Radix-4 algorithm architecture, multiplexing a set of MAP decoding units under different standards, and in a parallel processing method, performing MAP iterative decoding processing on the to-be-decoded data according to standard types.

Abstract: A linear transform can be performed using a passive analog multi-stage charge re-use linear transform circuit. The passive analog multi-stage charge re-use linear transform circuit transforms an input analog circuit to generate a transformed analog output signal. The passive analog multi-stage charge re-use linear transform circuit may be included in a software defined radio (SDR), where the transformed analog output signal may be output to an analog-to-digital converter (ADC) of the SDR device so as to enable the ADC to perform wideband spectrum sensing. The passive analog multi-stage charge re-use linear transform circuit may also be included in a beamforming device so as to enable the device to perform spectral shifting and spatial shifting of signals. This passive analog multi-stage charge re-use linear transform circuit may promote reduced power consumption in comparison to other circuits while also supporting wideband applications at high sampling rates.

Abstract: A digital pre-distortion component includes: a first capturing component that captures a first sample set of data; a first generating component that generates a first change matrix associated with a portion of the first sample set of data; a first memory component that stores the first change matrix; a second capturing component that captures a second sample set of data; a second generating component that generates a second change matrix associated with a portion of the second sample set of data; a second memory component that stores the second change matrix; a third capturing component that captures a third sample set of data; a third generating component that generates a third change matrix associated with a portion of the third sample set of data; a comparing component that compares the third change matrix with the first change matrix to obtain a first comparison, and compares the third change matrix with the second change matrix to obtain a second comparison; and an adapting component that adapts the digi

Abstract: A system that incorporates teachings of the present disclosure may include, for example, determining, by a controller of a mobile communication device, a phase shift criteria and an amplitude shift criteria associated with a modulation being implemented by the mobile communication device. The controller can determine a group of tuning steps that satisfies the phase and amplitude shift criteria and that provides a desired tuning step for a matching network of the mobile communication device. Additional embodiments are disclosed.

Abstract: A receiver apparatus includes a receiver path and a blocker detection path. The receiver path includes a down-converting stage. The blocker detection path includes a sensing circuit and a blocker detection circuit. The sensing circuit is arranged to sense a received radio frequency signal which has not yet been processed by the down-converting stage and generate a sensed signal accordingly. The blocker detection circuit is arranged to detect existence of a blocker signal according to the sensed signal and generate a blocker detection result indicative of the existence of the blocker signal when receiving the sensed signal.

Abstract: A method in a base station is provided for reducing distortion of an uplink signal received in a receiver part (20) of the base station, said distortion being caused by intermodulation, IM, products. The method comprises: generating (106), from a transmitter source signal, a modeled signal of IM components, as nth order IM components of the transmitter source signal, n being an integer value of 2, 3, 4 and/or 5 etc., and detecting (110) IM products of the received uplink signal, the received uplink signal comprising UL traffic components and the IM products, by correlating the received uplink signal with the IM components of the modeled signal. The method further comprises producing (112) a cancellation signal based on the detected IM products of the received uplink signal, and subtracting (114) the cancellation signal from the received uplink signal. Also, a similar apparatus in a base station is provided.

Abstract: A modulated signal is demodulated to obtain a modulation signal. The modulated signal is contained within an input signal. A periodic time segment sequence is defined having a plurality of ordered time segments. Signal values are acquired, from the input signal, during each ordered time segment. Signal values acquired during each ordered time segment are combined with signal values acquired during the same ordered time segment over multiple periods of the periodic time segment sequence. The modulated signal is demodulated by executing mathematical steps on the combined signal values to obtain the modulation signal.

Abstract: A system for decoding a stereo multiplex signal, including one or more devices operable to convert the stereo multiplex signal into a sum signal (L+R) and a difference signal (L?R). The sum signal and the difference signal may be derived from a left stereo signal (L) and right stereo signal (R). The system may also be operable to determine a first transfer function HL(f) and a second transfer function (HR(f)) from the sum signal (L+R) and the difference signal (L?R). Further, the system may be operable to filter the sum signal (L+R) according to the first transfer function to provide the left stereo signal (L), and filter the sum signal (L+R) according to the second transfer function to provide the right stereo signal (R).

Abstract: A drawer-type SIM card structure and an electronic product is provided, and the drawer-type SIM card structure is mounted in the interior of a containing cavity of a housing of an electronic product, including: a containing means for carrying a subscriber identification module (SIM) card, which can be relatively slidably mounted in the interior of the containing cavity; a connector which is fixedly mounted in the interior of the containing cavity and configured to be in a fit connection with the SIM card within the containing means; and a sensor which is fixedly mounted in the interior of the containing cavity, electrically connected with the connector, and configured to control the connection and disconnection of the connector and SIM card according to the position of the containing means.

Abstract: A communication device is provided. The communication device includes an antenna unit, a sensing unit and a radio frequency unit. The antenna unit is configured to transmit a radio frequency signal. The sensing unit is coupled to a ground terminal through a first capacitor. The sensing unit is configured to sense a capacitance value through the antenna unit. The radio frequency unit is configured to generate the radio frequency signal and to regulate the energy of the radio frequency signal according to the capacitance value.

Abstract: A medication pocket and cellular phone case assembly includes a housing that has a back wall having a front side, a back side and a perimeter edge. A perimeter wall is attached to and is continuous with respect to the perimeter edge. The perimeter wall extends forward of the front side and the perimeter wall has a distal edge with respect to the back wall. A perimeter lip is attached to the distal edge and extends inwardly over the back wall. A space between the perimeter lip and the back wall receives a cellular phone. A container is attached to the back side of the back wall and a case, containing medication, is removably positioned in the container.

Abstract: Transceivers implemented with a combination of super-heterodyne and zero intermediate frequency (ZIF) topologies are disclosed. In an exemplary design, an apparatus includes a frequency conversion circuit and a local oscillator (LO) generator. The LO generator generates a first LO signal and a second LO signal. The frequency conversion circuit performs frequency conversion (i) between intermediate frequency (IF) and baseband, based on the first LO signal, for an IF signal and (ii) between radio frequency (RF) and baseband, based on the second LO signal, for an RF signal. The frequency conversion circuit may perform frequency downconversion (i) from IF to baseband for a super-heterodyne receiver and (ii) from RF to baseband for a ZIF receiver. Alternatively or additionally, the frequency conversion circuit may perform frequency upconversion (i) from baseband to IF for a super-heterodyne transmitter and (ii) from baseband to RF for a ZIF transmitter.

Abstract: An electrical balancing network combined with coupled inductors (EBN) replaces a transmit/receive switch was used for isolation for time division duplexing transmission techniques. The EBN allows simultaneous transmit operation, or simultaneous receive operation, of multiple wireless technologies that would otherwise have to be scheduled for transmit or receive in a time division multiplexing manner. The wireless technologies may be WLAN, LTE, Bluetooth or other wireless technologies.