Abstract: Disclosed herein are diagnostic assays for identifying individuals that are protected against Plasmodium falciparum caused malaria. Such assays are particularly useful for determining not only the protective efficacy of Pf whole parasite vaccines for individual subjects, but also within populations of vaccinated subjects. The assays comprise the use of proteomes representing at least 50% of Pf, preferably coupled to a solid phase as a fixed array. The arrays are used to probe the sera of human subjects, particularly subjects of human clinical trials of whole parasite malaria vaccines as well as public health vaccination campaigns. Serum samples with antibody profiles most strongly reactive in multiplex to CSP and MSP5 demonstrate a sensitivity of from 92% to 100% and a specificity of from 84% to 89%.

Abstract: A method of classifying a subject having idiopathic scoliosis (IS) or at risk of developing IS comprising: determining the cellular response to Gi stimulation in a cell sample from the subject in the presence of OPN; determining the cellular response to Gi stimulation in a cell sample from the subject in the absence of OPN; and comparing the cellular response obtained in the presence of OPN with the cellular response obtained in the absence of OPN, whereby the comparing step enables the classification of the subject into one IS functional group. Also provided is the use of the foregoing method to classify borderline subjects and kits for applying the methods.

Abstract: The present invention provides methods and solid state devices for detecting and staging chronic kidney disease in a patient, where the levels of biomarkers in a sample obtained from a patient are elevated or reduced compared to the levels in a sample obtained from healthy subject. The invention also relates to the use of methods and solid state devices for measurement of specific biological markers for determining the efficacy of a treatment for chronic kidney disease and for determining a drug treatment protocol for a subject suffering from chronic kidney disease.

Abstract: ATM kinase is shown to regulate proteasome-mediated protein turnover through suppression of the expression of the ubiquitin-like protein ISG15 (Interferon Stimulated Gene 15). Silencing of the ISG15 pathway restored both the ubiquitin and autophagy pathways, and the UV-mediated degradation of their substrates in A-T cells. The ATM kinase negatively regulates the ISG15 pathway, and the constitutively elevated ISG15 pathway induces proteinopathy in A-T cells, and in A-T patients. These findings indicate that proteasome-mediated protein degradation is impaired in A-T cells due to elevated expression of the ISG15 conjugation pathway, which contributes to progressive neurodegeneration in A-T patients. The ISG15 pathway is a new target for both detection and treatment of A-T Inhibitors if ISG15 expression can be used to inhibit or attenuate neurodegeneration in A-T patients.

Abstract: The disclosure provides methods, kits, and devices for determining an amount of hemoglobin S and/or an amount of total hemoglobin, and optionally, expressing the amount of hemoglobin S as a percentage. Devices of the disclosure may be used as point-of-care diagnostic systems accessible for use to a layperson, i.e., an individual with minimal or no medical training or expertise.

Abstract: Novel splice variants, amino acid sequences and nucleotide sequences thereof, and methods of using same.

Abstract: A system for determining a level of Cotinine and Anabasine in a sample includes a test strip configured to receive a sample; and a meter configured to receive the test strip wherein the meter is configured to read the test strip and detect a level of Anabasine and Cotinine.

Abstract: A calibration sample includes serum/plasma having a known level of a first analyte and a plurality of particles that mimic the characteristics of red blood cells.

Abstract: A cartridge, analyzer for use therewith, and system including the cartridge and analyzer. The cartridge is configured to receive a biological fluid to be analyzed and includes a plate defining a main channel, a hemolysis chamber, and an oximetry chamber consecutively interconnected with one another. The analyzer is configured to perform analysis of sample disposed within the main channel, hemolyze sample disposed within the hemolysis chamber, and perform oximetry on sample disposed within the oximetry chamber. The cartridge and analyzer may further include alignment and clamping structures for maintain the cartridge in fixed position and alignment during testing or may further include cooperating features for moving the cartridge relative to the analyzer into a testing position or between various different testing positions.

Abstract: Disclosed is a test strip pickup mechanism configured to pick up test strips for liquid sample analysis one by one from a test strip bottle, the test strip pickup mechanism including: a pickup head configured to suck and hold a test strip; and a motor for rotating the pickup head, wherein the pickup head is provided with a suction hole for sucking and holding the test strip, and the motor is a hollow motor, a hollow portion thereof being connected to the suction hole.

Abstract: Systems and methods are provided for sample processing. A device may be provided, capable of receiving the sample, and performing one or more of a sample preparation, sample assay, and detection step. The device may be capable of performing multiple assays. The device may comprise one or more modules that may be capable of performing one or more of a sample preparation, sample assay, and detection step. The device may be capable of performing the steps using a small volume of sample.

Abstract: Systems and methods are provided for sample processing. A device may be provided, capable of receiving the sample, and performing one or more of a sample preparation, sample assay, and detection step. The device may be capable of performing multiple assays. The device may comprise one or more modules that may be capable of performing one or more of a sample preparation, sample assay, and detection step. The device may be capable of performing the steps using a small volume of sample.

Abstract: In some aspects, a device for apportioning granular samples includes a sample feeder defining a conduit, the conduit including a first opening to receive the granular samples and a second opening. The device includes a shuttle operably coupled to the sample feeder to receive the granular samples from the conduit via the second opening. The shuttle is configured to apportion the granular samples to incrementally enter a sample chamber to be analyzed. The device includes an outlet conduit fluidly coupled to the sample chamber and configured to permit the sample chamber to be evacuated.

Abstract: A method of performing a measurement of an analyte in a sample using an automatic analyzer is provided. The automatic analyzer comprises: a cartridge for dispensing a fluid, a measurement unit for performing the measurement, a sample holder for receiving the sample, and a pump for pumping the fluid out of the cartridge and into the sample holder. The cartridge comprises: a rigid portion, a flexible bladder, and an outlet. The rigid portion comprises an opening, which is connected to an inner cavity. The flexible bladder seals the opening to form a fluid chamber from the inner cavity. The fluid chamber is at least partially filled with the fluid. The pump is connected to the outlet. The method comprises: placing the sample into the sample holder, controlling the pumping of the fluid from the cartridge into the sample holder, and performing the measurement of the analyte using the measurement unit.

Abstract: A MEMS device comprises a substrate, a proof mass spaced apart from a surface of the substrate, and an over-travel stop structure. The over-travel stop structure includes a lateral stop structure and a cap coupled to the lateral stop structure. The MEMS device is fabricated to include relatively small gap sections and relatively large gap regions separating the lateral stop structure from the proof mass. The larger gap regions are covered by the cap and the smaller gap sections are exposed from the gap. During fabrication, removal of particles from the smaller gap sections is facilitated by their exposure from the cap and removal of particles from the larger gap regions underlying the cap is facilitated by their larger size. The lateral stop structure may be cross-shaped to limit deflection of the proof mass along two in-plane axes. The cap limits deflection of the proof mass along an out-of-plane axis.

Abstract: A method of processing signals from an accelerometer/gyroscopic-based input device includes providing the input device within a vehicle. An accelerometer/gyroscopic-based second device is also provided within the vehicle. The input device is manually actuated while the vehicle is in motion. First signals are transmitted from the input device in response to the manually actuating step. Second signals are transmitted from the second device in response to the motion of the vehicle. The first signals are adjusted dependent upon the second signals.

Abstract: A hot wire anemometer circuit has a calibrate subcircuit and an operate subcircuit which are selectively invoked via a user-activate mode switch. The calibrate subcircuit includes a detector configured to compare an amplified sensor voltage with an amplified drive voltage and output an indicator signal when the two voltages match. The drive voltage is derived from a user-adjusted drive resistance of a bridge subcircuit. The operate circuit includes a feedback loop which provides a signal to a bride node of a bridge circuit. After a sensor is connected to the anemometer circuit, the drive resistance is adjusted until the indicator signal is produced, signifying that the circuit is tuned and impedances are matched to prevent oscillations. A slewing network protects the sensor by shorting the drive resistance upon switching the anemometer circuit to the calibrate mode from the operate mode, and gradually restoring the drive resistance when switching back.

Abstract: A scanning probe microscope includes a cantilever having a probe at a free end thereof; a scanner to three-dimensionally relatively move the probe and a sample; a vibrator to vibrate the cantilever based on a vibrating signal; a displacement detector to detect a displacement of the cantilever and to output a displacement signal indicating the displacement; and a phase difference information detecting section to generate a phase signal including information of a phase difference between the vibrating signal and the displacement signal. The phase difference information detecting section includes a phase regulating portion to provide, to the phase difference, a phase offset to cancel an initial phase difference present in a state in which the probe is not in contact with the sample.

Abstract: An improved spring probe for a connector assembly includes an elongated electrically conductive contact and an elongated helical compression spring disposed about and attached to the contact. The compression spring includes a stabilization section configured to stabilize the spring probe in a cavity of a test socket body during assembly of the test socket body. The spring stabilization section includes integrated opposed stabilization coils to vertically stabilize the spring probe in the cavity. An insulated spacer is disposed on the conductive contact and has an annular surface configured to contact a wall of the cavity to stabilize and isolate the contact within the cavity to provide a controlled impedance coaxial probe.

Abstract: A test and measurement instrument includes a coefficient storage facility coupled to a programmable filter. The coefficient storage facility is configured to store at least two pre-determined filter coefficient sets, and configured to pass a selected one of the at least two pre-determined filter coefficient sets to the filter based on a measurement derived using a compensation oscillator. The measurement may include clock delay and clock skew. In some examples the test and measurement instrument may additionally adjust clock delay and/or clock skew in addition to selecting appropriate filter coefficients.

Abstract: A Hall element driving circuit includes: a signal switching unit which is disposed between a power supply, which outputs a current, and a Hall element having first and second terminals and performs switching control between a first switching state that supplies the current to the first terminals and a second switching state that supplies the current to the second terminals; a switching control unit that controls transitions between the first switching state and the second switching state; and a switching unit that is disposed between the power supply and the signal switching unit and controls switching between an on state where the current is supplied and an off state where the current is stopped. The switching control unit controls transitions between the on and off states and executes switching control over the signal switching unit only when the switching unit is in the off state.

Abstract: An apparatus for detecting noise in a power supply of a PLC analog input/output module is provided. The apparatus may include a capacitor configured to extract a noise determination target voltage from a driving voltage outputted from the power supply; a voltage conversion unit configured to convert the noise determination target voltage outputted from the capacitor and to output the converted noise determination target voltage; a comparison unit configured to compare the noise determination target voltage converted by the voltage conversion unit with a reference voltage; and a determination unit configured to determine whether the noise determination target voltage is a noise, based on a comparison result by the comparison unit.

Abstract: A method of measuring electrical power including the steps of measuring a first electrical input variable at an input to a power conditioner connected to an electricity supply, measuring one or more electrical output variables at an output of the power conditioner, calculating a second electrical input variable at the input to the power conditioner according to the one or more electrical output variables measured at the output and the first electrical input variable measured at the input, calculating an estimated power according to the measured first electrical input variable and the calculated second electrical input variable, and sending the estimated power via a data interface.

Abstract: A remotely readable apparatus for metering of a plurality of electricity consumer lines, comprising: (a) a meter head that measures electricity usage for each of the plurality of electricity consumer lines; and (b) sensors that sense environmental conditions in a second housing enclosing a distribution transformer that steps down voltage from a distribution level to a consumer level, said one sensors in communication with said meter head and not operable to sense environmental conditions in said first housing, and wherein said meter head connects and disconnects service on said plurality of electricity consumer lines in response to information received from said sensors; wherein a transponder transmits data received to/from said meter head to/from a remotely located computer, and said meter head is operable, based on data received from said transponder, to connect/disconnect service on said electricity consumer lines.

Abstract: The present disclosure provides a method and a phase lock detection apparatus for detecting whether a phase of an output signal is locked to the phase of a reference signal. The apparatus includes a first divider that individually frequency-divides first and second pulse signals, a phase frequency detector that outputs third and fourth pulse signals that correspond to a phase difference between the frequency-divided first and second pulse signals, a second divider that individually frequency-divides the third and fourth pulse signals, and a determiner that determines whether a phase of the second pulse signal is locked, based on the frequency-divided third and fourth pulse signals.

Abstract: An apparatus for testing an impedance range of a wireless power transmitter is provided. The apparatus comprises an adjustable impedance circuit configurable to be connected to a power source. The apparatus further comprises a transformer coupled the adjustable impedance circuit. The apparatus further comprises a sensing circuit configured to sense a parameter indicative of a parasitic impedance of the adjustable impedance circuit. The apparatus further comprises a driver circuit configured to drive the transformer with a signal based on the sensed parameter that causes the transformer to apply a first voltage to the adjustable impedance circuit. The first voltage has a substantially same amplitude as a voltage drop caused by the parasitic impedance. The second voltage is out of phase with the voltage drop. The sensed parameter is a current circulating in the adjustable impedance circuit or a voltage across at least a portion of the adjustable impedance circuit.

Abstract: A method for determining current return path integrity in an electric device with a plurality of signal lines and supply lines. A library with at least one reference signal pattern of a near end crosstalk signal on a defined signal line arising from an input signal on another defined signal line is provided, a predetermined signal to a selected signal line of the electric device is applied, the near end crosstalk signal on at least one further signal line of the electric device is detected, said near end crosstalk signal is compared with the corresponding reference signal pattern from the library, and if there is a deviation between the near end crosstalk signal and the corresponding reference signal pattern, an information that there is any defect in the electric device is displayed.

Abstract: An audio plug detection structure is disclosed, which is adapted for an audio jack corresponding to an audio plug and includes a first and second connection points, a time-varying signal generation circuit, and a comparison circuit. The time-varying signal generation and comparison circuits are connected to the first connection point. When the audio plug is inserted into the audio jack, the first connection point is connected to a first pole of the audio plug and the second connection point is connected to a second pole different from the first pole of the audio plug. Therefore, the time-varying signal generation circuit, the first connection point, an inner impedance circuit of the audio plug and the second connection plug form a loop. The comparison circuit outputs a determination signal indicating the audio plug is inserted by detecting a change of a time-varying signal generated by the time-varying signal generation circuit.

Abstract: Methods and configurations are disclosed for DNV application in rapid and cost-effective inspection of power transmission and power distribution lines.

Abstract: An arc fault detection system includes a first current sensor, a second current sensor, a band-pass filter, and a comparator module. The first current sensor, the second current sensor, and the comparator module are each connected to the comparator module by direct leads for biasing a current differential between the first current sensor and the second current sensor using a bias calculated from a frequency component indicative of arc events received from the frequency selector.

Abstract: A method of processing current transformer data, performed by an electronic trip unit, includes obtaining first current data based on a first current signal from a first current transformer, second current data based on a second current signal from a second current transformer, and third current data based on a third current signal from a third current transformer. Using the current data, it is determined whether one of the current transformers is connected to the electronic trip unit with an improper polarity. Upon determining that one of the current transformers is connected to the electronic trip unit with an improper polarity, the obtained current data corresponding to the current transformer that is connected with improper polarity is automatically inverted. A ground fault calculation is performed using the automatically inverted current data.

Abstract: Provided is a detection circuit configured to avoid erroneous detection that may occur immediately after a detection circuit is powered on. The detection circuit includes: an output transistor connected between a voltage input terminal and a voltage output terminal; and a load open-circuit detection circuit configured to detect an open circuit of a load connected to the voltage output terminal, in which an output circuit of the load open-circuit detection circuit includes a first transistor and a second transistor connected in series, the first transistor having a gate connected to the output transistor in common, the second transistor having a gate to which a signal indicating that the open-circuit of the load is detected, and in which the first transistor is in an off state when the output transistor is in an off state.

Abstract: A method of evaluating one or more capacitor banks in an electrical power system includes: (a) acquiring data representing a signal of interest of the power system, where the data describes a plurality of power system events; and (b) based on one or more patterns contained in the data, identifying at least one of the power system events as being associated with capacitor operation.

Abstract: The present invention provides a partial-discharge measurement method in which a partial-discharge defect signal and noise are separated, a partial-discharge defect position is detected, and the risk of a detected partial discharge defect is diagnosed. Further, this method provides a highly reliable high-voltage device. An electromagnetic wave generated by a sample is simultaneously measured by a plurality of sensors. A partial discharge and noise are separated through the comparison of the spatial intensity distribution of measured signals and a spatial signal intensity distribution measured beforehand at the time of the occurrence of a partial discharge, and a defect position is detected using a peak position. Further, the risk of a defective site is diagnosed on the basis of a simultaneously measured charge amount signal.

Abstract: The present disclosure relates to calculating a fault location in an electric power transmission system based on traveling waves. In one embodiment, a system consistent with the present disclosure may be configured to detect a fault in an electric power transmission system. The system may include a traveling wave detection subsystem configured to detect and measure traveling waves on a transmission line and a fault location estimation subsystem. The fault location estimation subsystem may receive from the traveling wave detection subsystem a first plurality of traveling waves on the transmission line generated during a reference event. The fault location estimation subsystem may receive from the traveling wave detection subsystem a second plurality of traveling waves generated during an unplanned event. An unmatched traveling wave in the second plurality of waves may be detected and a location of the unplanned event based on the unmatched traveling wave.

Abstract: A method for identifying a faulted DC power transmission medium in a multi-terminal DC electrical network is provided. The DC electrical network includes multiple terminals connected via DC power transmission media. The method includes detecting a fault occurring in the DC power transmission media and, after detecting the fault, measuring a surge arrival time at each terminal, each surge arrival time being the difference between the time of detecting the fault and the time of arrival of an electrical wave surge generated by the fault at the corresponding terminal. The method further includes comparing the surge arrival times between the terminals to identify DC power transmission media in which the fault is not located, allocating a healthy status to the media in which the fault is not located, and identifying the faulted DC power transmission medium as being the DC power transmission medium/media without a healthy status.

Abstract: A test device of a semiconductor device for testing semiconductor device including a plurality of interface pads includes a plurality of coupling units each configured to be coupled to a corresponding one of the plurality of interface pads, a channel configured to be coupled to the plurality of coupling units, a voltage generating unit configured to generate a test voltage applied to the channel, and a current measuring unit configured to measure a current that flows on the channel in response to the test voltage.

Abstract: A transistor testing circuit for measuring a breakdown voltage of a transistor included in a semiconductor apparatus with high accuracy for each chip is provided. The transistor testing circuit is disposed on a semiconductor chip to measure the breakdown voltage of a MOS transistor. The transistor testing circuit includes: a voltage applying apparatus, a current detecting circuit, a current mirror voltage outputting circuit, and a comparator circuit. The voltage applying apparatus applies a predetermined testing voltage to at least one of a drain, a source, and a gate of the MOS transistor. When the testing voltage is applied, the current detecting circuit detects a current flowing from the MOS transistor to a load circuit. The current mirror voltage outputting circuit generates a mirror current corresponding to the detected current and outputs the same. The comparator circuit compares the mirror current with a predetermined reference current to output a comparison result signal.

Abstract: Current Voltage and Capacitance Voltage (IV and CV) measurements are critical in measurement of properties of electronic materials especially semiconductors. A semiconductor testing device to accomplish IV and CV measurement supports a semiconductor wafer and provides a probe for contacting a surface on the wafer under control of an atomic Force Microscope or similar probing device for positioning the probe to a desired measurement point on the wafer surface. Detection of contact by the probe on the surface is accomplished and test voltage is supplied to the semiconductor wafer. A first circuit for measuring capacitance sensed by the probe based on the test voltage and a complimentary circuit for measuring Fowler Nordheim current sensed by the probe based on the test voltage are employed with the probe allowing the calculation of characteristics of the semiconductor wafer based on the measured capacitance and Fowler Nordheim current.

Abstract: A degradation detection circuit may include a degradation unit including multiple delay elements driven by a high voltage for degradation. The high voltage for degradation value may be higher than an operation voltage. The degradation unit may be configured to provide a first delayed signal after passing a test signal through the degradation unit, wherein the test signal retains a pulse for a preset time. The degradation detection circuit may include a reference unit including a plurality of delay elements driven by the operation voltage, and configured to provide a second delayed signal after passing the test signal through the reference unit, a delay setting unit configured to provide a third delayed signal by selectively adding delay elements with respect to the second delayed signal, and a delay checking logic configured to detect a delay of the test signal by comparing the first delayed signal and the third delayed signal.

Abstract: A method of performing a static timing analysis on an integrated circuit includes loading a library that includes local random variation information of the integrated circuit and global variation information of the integrated circuit that is obtained based on a set of a plurality of global variation parameters of the integrated circuit, calculating delays of timing arcs included in the integrated circuit based on the library, and determining whether at least one timing path of a plurality of timing paths included in the integrated circuit violates a timing constraint based on the delays of the timing arcs in the at least one timing path, the local random variation information of the integrated circuit and the global variation information of the integrated circuit.

Abstract: In one embodiment, a method for operating a receiver having a first receiver input and a second receiver input is described herein. The method comprises receiving a data signal via the first and second receiver inputs in a mission mode, AC-coupling the received data signal to an amplifier, and amplifying the AC-coupled data signal using the amplifier. The method also comprises receiving one or more test signals via one or both of the first and second receiver inputs in a test mode, DC-coupling the received one or more test signals to a test receiver, and determining whether there are one or more defects based on the one or more test signals received by the test receiver.

Abstract: An integrated circuit (IC) having a heat-generating element, such as a power MOSFET, a current-carrying conductor coupled to the heat-generating element, a sense conductor adjacent the current-carrying conductor, and a failure-detection circuit coupled to the sense conductor. When thermal cycling of the IC causes the resistance of the sense conductor to become greater than a temperature-dependent threshold value, the failure-detection circuit generates a signal indicating that the integrated circuit will soon fail. The resistance of the sense conductor is determined by injecting a current into the sense conductor to generate a voltage. The temperature-dependent threshold value is a voltage generated by injecting a current into a reference conductor disposed away from the current-carrying and sense conductors. A voltage comparator compares the two voltages to generate the output.

Abstract: An integrated circuit including first pads and second pads, a first receiver circuit and a first driver circuit respectively connected to the first pad, a second receiver circuit and a second driver circuit respectively connected to the second pad, and a first loopback circuit having a first input terminal electrically connected to the first receiver circuit, a first output terminal electrically connected to the first driver circuit, a second output terminal electrically connected to the second driver circuit, and a second input terminal electrically connected to the second receiver circuit may be provided. At a normal mode, the first loopback circuit electrically connects the first input terminal to the second output terminal and electrically connects the second input terminal to the first output terminal. At a test mode, the first loopback circuit electrically connects the first input terminal to the first output terminal.

Abstract: A browser probe has a probe body including a signal line, a nose of electrical insulating material integral with and projecting from the probe body, a pin supported by the probe body and electrically conductively connected to the signal line, a spring exerting a biasing force on the pin, an electrically conductive probe tip supported by the nose at a distal end of the nose remote from the probe body, and a plurality of discrete resistors interposed between the pin and the probe tip within the nose. The resistors are supported independently of another so as to be slidable within the nose. The probe tip is electrically conductively connected to the signal line via the resistors and the pin under the biasing force exerted by the spring.

Abstract: A wafer probing system includes a probe card assembly having a plurality of individual probe structures configured make contact with a semiconductor wafer mounted on a motor driven wafer chuck, with each probe structure configured with a pressure sensing unit integrated therewith; and a controller configured to drive the probe card assembly with one or more piezoelectric driver units response to feedback from the pressure sensing units of the individual probe structures.

Abstract: A test handler comprises a main rotary turret and a loading station operative to convey electronic components to functional modules of the main rotary turret. An auxiliary rotary turret incorporating multiple carrier modules then receives electronic components from the functional modules of the main rotary turret. Multiple testing stations located along a periphery of the auxiliary turret are operative to receive electronic components from the carrier modules for testing while the loading station is concurrently conveying electronic components to the functional modules of the main rotary turret, so that the impact of transfer time is reduced or eliminated in a test process cycle of the test handler.

Abstract: A method and system for implementing enhanced scan chain diagnostics via a bypass multiplexing structure. A full scan chain structure is partitioned into a plurality of separate chains, such as three separate partitioned chains, with bypass multiplexers for implementing enhanced scan chain diagnostics. Each of the separate partitioned chains includes bypass multiplexers with independent controls enabling scan data being routed through multiple different independent scan paths, potentially bypassing failing latches. The information acquired from a combination of full scans and partitioned scans is used for scan failure isolation to enable pinpoint identification of stuck-at-zero (SA0) and stuck-at-one (SA1) faults in the scan chain.

Abstract: A method and system for implementing enhanced scan chain diagnostics via a bypass multiplexing structure. A full scan chain structure is partitioned into a plurality of separate chains, such as three separate partitioned chains, with bypass multiplexers for implementing enhanced scan chain diagnostics. Each of the separate partitioned chains includes bypass multiplexers with independent controls enabling scan data being routed through multiple different independent scan paths, potentially bypassing failing latches. The information acquired from a combination of full scans and partitioned scans is used for scan failure isolation to enable pinpoint identification of stuck-at-zero (SA0) and stuck-at-one (SA1) faults in the scan chain.

Abstract: A test mode circuit of a semiconductor device includes a test mode activating signal generation unit suitable for generating a test mode activating signal in response to a test signal; a test clock generation unit suitable for generating a plurality of test clocks in response to the test mode activating signal and a control clock; a test control signal generation unit suitable for generating test control signals based on the plurality of test clocks of a control signal input cycle, wherein the plurality of test clocks have the control signal input cycle and a data input cycle; and an internal control signal generation unit suitable for generating a plurality of control signals to perform a test operation in response to the test control signals and input data.