Abstract: A message queue processing method is provided, which includes receiving messages that need to be processed; classifying the messages according to a dependency relationship between the messages, and placing the classified messages in a corresponding processing queue group, where the processing queue group includes a parallel processing queue group and a serial processing queue group; acquiring a head node linked list in the processing queue group, where the head node linked list is a linked list obtained by connecting nodes of message linked lists corresponding to all different processing times in the corresponding processing queue group; and when a processing time of a corresponding node in the head node linked list arrives, performing processing on a message linked list of the node in the head node linked list.

Abstract: A method to optimize calls to a service by components of an application running on an application server is provided. The method includes receiving a first call and a second call, the first call made to a service by a first one of a plurality of components included in the application, and the second call made to the service by a second one of the plurality of components; selecting one of a plurality of optimizations, the plurality of optimizations including orchestrating the first call and the second call into a third call to the service; and, in response to the selecting of the orchestrating of the first call and the second call into the third call as the one of the plurality of optimizations, orchestrating the first call and the second call into the third call.

Abstract: A mechanism is provided for reusing importance sampling for efficient cell failure rate estimation of process variations and other design considerations. First, the mechanism performs a search across circuit parameters to determine failures with respect to a set of performance variables. For a single failure region, the initial search may be a uniform sampling of the parameter space. Mixture importance sampling (MIS) efficiently may estimate the single failure region. The mechanism then finds a center of gravity for each metric and finds importance samples. Then, for each new origin corresponding to a process variation or other design consideration, the mechanism finds a suitable projection and recomputes new importance sampling (IS) ratios.

Abstract: Systems and methods for identifying a faulty node in a Hadoop cluster using an interface to the Hadoop cluster are described. A method may include receiving, at an interface to a Hadoop cluster, an input requesting diagnostic information for one or more nodes in the Hadoop cluster. The input may also specify the one or more nodes in the Hadoop cluster for which diagnostic information is requested. The method may further include initiating a diagnostic analysis of the one or more nodes, and displaying, at the interface, the diagnostic information for the one or more nodes. The diagnostic information may identify a node exhibiting a fault and be displayed while the diagnostic analysis is in progress.

Abstract: A method for automated qualification of a safety critical system including a plurality of components is provided. A functional safety behavior of each component is represented by an associated component fault tree element. The method includes automatically performing a failure port mapping of output failure modes to input failure modes of component fault tree elements based on a predetermined generic fault type data model stored in a database.

Abstract: A method for linking information related to a computer crash. The method includes establishing a network of computing resources communicatively coupled to a network, wherein each computing resource is associated with a corresponding hardware configuration capable of executing and displaying at least one application, wherein each of the network of computing resources is associated with a globally unique identifier (GUID). The method includes receiving configuration information relating to the network of computing resources. The method includes receiving a crash report of a crash occurring on a crashed computing system within the network of computing resources. The method includes extracting a GUID from the crash report, wherein the GUID identifies said crashed computing resource. The method includes determining configuration information for the crashed computing resource, and correlating the configuration information with the crash information.

Abstract: Systems, methods and apparatuses for mitigating a wireless networking problem of a wireless network are disclosed. One method includes determining, by an analytics engine, a problem associated with the wireless network, wherein the analytics engine is operative as a central intelligence for detection, analyzing, classifying, root-causing, or controlling the wireless network. The method further includes receiving, by the analytics engine, a collected user input and state information, mapping, by at least the analytics engine, a problem signature of the user input and the state information to at least one of a number of possible problem network conditions, determining, by the analytics engine, instructions for alleviating the problem based on the mapping of the problem signature, and providing, by the analytics engine, the instructions.

Abstract: A memory system includes a memory and a controller. The memory includes a first memory chip and a second memory chip. The controller controls the memory. Each of the first and second memory chips includes string units and blocks including the string units. The memory holds information indicating a partial bad block including a bad string unit, and indicating which one of string units is the bad string unit in the partial bad block.

Abstract: Data lifecycle management is performed by managing metrics from a monitored system. A fault is identified from the monitored system. One or more metrics that are directly related to the fault and one or more metrics that are indirectly related to the fault by virtue of being directly or indirectly related to the one or more directly related metrics are identified and stored in a memory. A lifespan condition associated with the fault is identified. A lifespan for each of the directly and indirectly related metrics based on the identified lifespan condition is added or changed. A metric that is critically related to another metric will inherit the same lifespan, and a metric that is related but not critically related to another metric will not inherit the other metric's lifespan. Metrics are removed from the memory if their associated lifespans are over.

Abstract: The disclosed embodiments relate to systems and methods for coordinating management of a shared disk storage between nodes. Particularly, a messaging protocol may be used to communicate notifications regarding each node's perception of the shared storage's state. The nodes may use the messaging protocol to achieve consensus when recovering from a storage device failure. Some embodiments provide for recovery when localized failures, such as failures at an adapter on a node, occur.

Abstract: A computer hardware-implemented method, system, and/or computer program product prevents a cascading failure in a complex stream computer system causing an untrustworthy output from the complex stream computer system. Multiple upstream subcomponents in a complex stream computer system generate multiple outputs, which are used as inputs to a downstream subcomponent, wherein the multiple upstream subcomponents execute upstream computational processes. An accuracy value is assigned to each of the multiple outputs from the upstream subcomponents, and weighting values are assigned to each of the inputs to the downstream subcomponent. If using the accuracy values and weighting values fails to adjust the downstream subcomponent to meet a predefined trustworthiness level for making a first type of prediction, then a new downstream computational process that produces a different second type of prediction is executed.

Abstract: An apparatus for comparing strings comprises a first and a second set of input registers, a matrix of comparator circuits wherein rows of the matrix correspond to the first set of input registers and columns of the matrix correspond to the second set of input registers, a set of row control registers wherein each register corresponds to a row of the matrix of the comparator circuits, the matrix of comparator circuits configured to compare data provided by the first set of registers with data provided by the second set of registers according to the row control registers, and an error detection circuit configured to compare results from four comparator circuits corresponding to two adjacent rows and two columns of the matrix of comparator circuits. A method that invokes the above mentioned apparatus is also disclosed herein, along with a computer program product corresponding to the method.

Abstract: An information processing apparatus includes a storage device; and a processing unit coupled to the storage device and configured to: execute a first kernel and, after occurrence of a failure in the first kernel, a second kernel to output a kernel dump of first data stored in the storage device to another device; and through the second kernel, using a first storage area in the storage device, output a kernel dump of second data stored in a second storage area in the storage device to the other device, and then, using the first storage area and the second storage area, output a kernel dump of third data stored in a third storage area in the storage device to the other device.

Abstract: Embodiments of the present invention provide a method, system and computer program product for trace capture of successfully completed transactions for trace debugging of failed transactions. In an embodiment of the invention, a method for trace capture of successfully completed transactions for trace debugging of failed transactions is provided. The method includes storing entries in a log with information pertaining to successfully completed transactions in a transaction processing system executing in memory of a host server, detecting a failed transaction in the transaction processing system, generating a trace for the failed transaction, and providing with the generated trace an entry from the log with information pertaining to a successful completion of the failed transaction.

Abstract: Methods, systems, and devices are described for providing proactive cloud orchestration services for a cloud hardware infrastructure. A health management system may monitor component(s) of the cloud hardware infrastructure. The health management system may determine a failure probability metric for the component(s) based on the monitoring of the component and in consideration of historical information associated with the component, or similar components. The health management system may determine an optimization strategy for the component and, when an optimization decision has been reached, initiate a reconfiguration procedure to implement the optimization strategy. The optimization strategy may provide for mitigating or eliminating the consequences of the component failure associated with data loss, downtime, and the like.

Abstract: Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring a pipeline of a processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.

Abstract: A programmable logic circuit device has a configuration memory that stores configuration data; a programmable logic circuit in which a logic circuit is configured based on the configuration data stored in the configuration memory; a control circuit that sequentially and repeatedly reads, from the configuration memory, target configuration data corresponding to an error-check-target circuit in the programmable logic circuit, from among the configuration data in the configuration memory and; and an error detection circuit that executes an error check on the target configuration data read by the control circuit.

Abstract: A storage device may include a non-volatile memory; and a controller. The controller may be configured to store a plurality of blocks of data in the memory, determine exclusive-or (XOR) parity data for the plurality of blocks, and store the XOR parity data in the memory; store a second block of data in the memory. The controller may be further configured to generate updated XOR parity data by at least XORing a first block of the plurality of blocks and the second block of data with the XOR parity data to remove the first block from the XOR parity data and to add the second block to the XOR parity data, and store the updated XOR parity data in the memory.

Abstract: A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).

Abstract: Disclosed is a memory device including: a plurality of memory blocks suitable for storing data; peripheral circuits suitable for temporarily storing data read from a selected memory block, performing a randomization operation to the read data, and performing an ECC decoding operation to the randomized data; and a control logic suitable for controlling the peripheral circuits to repeat the randomization operation and the ECC decoding operation until the ECC decoding operation is successful, and a system including the same.

Abstract: According to an embodiment, a row decoder to perform row decoding by using, as row soft input information, a row received word read as soft determination information from a non-volatile memory and to calculate row extrinsic information and a column decoder to perform column decoding by using column soft input information, which is a result of adding of the row extrinsic information to a column received word read as soft determination information from the non-volatile memory, and to calculate column extrinsic information are included. The row decoder includes a first decoder for first decoding, a second decoder for second decoding a decoding method of which is different from that of the first decoding, and a selection unit to select a decoded result based on accuracy of a decoded result of the first decoding and that of a decoded result of the second decoding and to calculate the row extrinsic information.

Abstract: An operating method of a memory controller includes performing a soft read operation to read data stored in a semiconductor memory device using a soft read voltage, performing a soft decision ECC decoding operation to the read data based on a first log likelihood ratio (LLR) value, and performing the soft decision ECC decoding operation to the read data based on a second LLR value when the soft decision ECC decoding operation based on the first LLR value fails. The first and second LLR values are selected between a default LLR value and an updated LLR value. The updated LLR value is generated on a basis of numbers of error bits and non-error bits of the read data, which are obtained through the soft decision ECC decoding operation to the read data.

Abstract: According to one embodiment, a memory controller of a memory system includes a command issuing unit, a decoder, a counter, and a statistical processor. The command issuing unit issues a first command for single read of first data from a nonvolatile memory. The decoder performs first error correction on the read first data. The counter counts a number of times of multiple reads. The statistical processor performs statistical processing of results of the multiple reads, and outputs second data obtained by the statistical processing. When the decoder is unable to perform the first error correction on the read first data, the command issuing unit issues a second command for multiple reads of the first data.

Abstract: According to an embodiment, a memory system includes a nonvolatile memory, a correction unit, a storage unit, and an update unit. The correction unit performs error correction on code words forming a product code that is read from the nonvolatile memory. The storage unit stores a first code word, the first code words being the code word on which the error correction is not yet performed by the correction unit. The update unit updates, in case where a condition is satisfied, first data to second data, the first data being included in a second code word, the second code word being the code word on which the error correction is performed, the first data being corrected by the error correction, the second data being included in the first code word, the second data corresponding to the first data.

Abstract: An embodiment includes: a first decoder configured to calculate first distance information indicating a squared Euclidean distance between a first decoded word obtained by decoding a first received word read from a nonvolatile memory and the first received word, calculate a decoding success rate based on the first distance information, and calculate a first extrinsic value vector based on the first decoding success rate; and a second decoder configured to decode a result obtained by adding a second received word read from the nonvolatile memory to the rearranged set of the first extrinsic values corresponding to the second codeword, calculate second distance information based on a second decoded word obtained by the decoding, calculate a decoding success rate based on the second distance information, and calculate a second extrinsic value based on the second decoding success rate.

Abstract: According to one embodiment, a semiconductor memory device includes an encoder configured to generate an error correction code with respect to data, a processor configured to perform interleaving with respect to the data output from the encoder after the generation of the error correction code by the encoder, and a memory configured to store a process result from the processor.

Abstract: According to one embodiment, a memory controller includes a bank controller including a queuing part queuing commands associated with a bank and having a first flag associated with each of the commands, the bank controller executing the commands in order, a data controller transferring write data to the bank when a particular command to be executed among the commands is a write command associated with one of physical addresses in the bank, and a parity controller generating parity data for restoring the write data based on a value of a first flag associated with the particular command, before execution of the particular command is completed.

Abstract: An embodiment includes a system, comprising: an Error Correcting Code (ECC) memory comprising a plurality of memory locations, each memory location corresponding to a device address of the ECC memory; a system management bus (SMB); a baseboard management controller (BMC) coupled to the ECC memory through the SMB; and an operating system comprising a driver module coupled to the BMC through the SMB, the driver module being configured to receive through the Memory device address information associated with the ECC memory and to convert the device address information into physical address information independent of an ECC memory controller.

Abstract: Data placement for loss protection in a storage system includes constructing multiple logical compartments. Each logical compartment includes a placement policy including a set of storage placement rules for determining permitted placement of storage symbols, and a balancing policy for balancing placement of the storage symbols for each volume among physical storage containers. A first logical compartment of the multiple logical compartments is data loss independent with respect to a second logical compartment.

Abstract: An information processing system includes a storage unit storing application identification information of an application for executing a first process in association with information relating to the first process; a receiving unit that receives a request including the application identification information and information relating to electronic data from a device; a process execution unit that executes the first process on electronic data based on the information relating to the first process stored in association with the application identification information included in the request and the information relating to the electronic data included in the request; and a process generation unit that generates information relating to a second process for rolling back a processing result of the first process executed by the process execution unit. The process execution unit executes the second process based on the generated information relating to the second process when an error occurs in the first process.

Abstract: A method is described that includes providing a snapshot counter for a storage system implemented with multiple distributed consistent database instances. The method further includes recognizing the taking of a snapshot of the storage system by incrementing the snapshot counter from a first snapshot counter value to a second snapshot counter value. The method further includes, in response to a first change for one of the distributed consistent databases subsequent to the taking of the snapshot, performing the following: saving state information of the distributed consistent database as the state information existed prior to the change and associating the first snapshot counter value to the state information. Associating the second snapshot counter's value with the distributed consistent database having the first change. Another method for the taking of a snapshot of a distributed consistent database is also described.

Abstract: A method of backing up data from an electronic system is disclosed. The method may include detecting an operating mode of the battery subsystem that is a maintenance discharge cycle operating mode and in response, calculating, using a first algorithm, the available battery capacity relative to a minimum battery capacity. The method may also include detecting an operating mode of the battery subsystem that is a normal operating mode and in response, calculating, using a second algorithm, the available battery capacity relative to a maximum battery capacity. The method may also include comparing the available battery capacity to a battery capacity sufficient to complete a backup operation, detecting a backup trigger condition and in response to the backup trigger condition and the available battery capacity being sufficient to complete a backup operation, backing up, data from the electronic system.

Abstract: A storage system according to certain embodiments includes a client-side signature repository that includes information representative of a set of data blocks stored in primary storage. During restore operations, the system can use the client-side signature repository to identify data blocks located in primary storage. The system can also use the client-side signature repository to identify multiple locations within primary storage where instances of some of the data blocks to be restored are located.

Abstract: A data storage system including a virtual server on a network managing a plurality of user accounts, each user account including one or more files; the virtual server adapted to verify user access information for a particular user account; the virtual server transferring over the network information relating to files stored on the virtual server in the particular user account to a verified user on a user computer; the virtual server further adapted to transfer files associated with the particular user account to and from the user computer.

Abstract: An information processing system, computer readable storage medium, and method for supporting resilient execution of computer programs. A method provides a resilient store wherein information in the resilient store can be accessed in the event of a failure. The method periodically checkpoints application state in the resilient store. A resilient executor comprises software which executes applications by catching failures. The method uses the resilient executor to execute at least one application. In response to the resilient executor detecting a failure, restoring application state information to the at least one application from a checkpoint stored in the resilient store, the resilient executor resuming execution of the at least one application with the restored application state information.

Abstract: An information processing system, computer readable storage medium, and method for supporting resilient execution of computer programs. A method provides a resilient store wherein information in the resilient store can be accessed in the event of a failure. The method periodically checkpoints application state in the resilient store. A resilient executor comprises software which executes applications by catching failures. The method uses the resilient executor to execute at least one application. In response to the resilient executor detecting a failure, restoring application state information to the at least one application from a checkpoint stored in the resilient store, the resilient executor resuming execution of the at least one application with the restored application state information.

Abstract: A method for processing a data object access request in a storage system having storage devices can include receiving an access request for accessing a first data object, the request being received by a controller that stores at least two consecutive data objects received by the storage system in different storage devices. The method may then include detecting that the first data object is corrupted, and determining, in response to the detecting, that a second data object has identical data as the first data object. Determining that the second data object has identical information as the first data object can include determining that a first metadata tag corresponding with the first data object and a second metadata tag corresponding with the second data object are identical. The second data object can then be provided in a response to the access request.

Abstract: A method includes: causing at least three processors to perform a same process; extracting, when one of the at least three processors outputs different operational information generated by performing the same process, majority processors with which outputted operational information are the same and a minority processor with which different operational information is outputted; and controlling one of the two redundant processors to output a result of the same process.

Abstract: Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring a pipeline of a processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.

Abstract: In a server system, a hardware configuration comparison is made with respect to each combination of a current server and a backup server, and, by referring to hardware configuration matching policy information, the presence or absence of hardware configuration concealment and the possibility of a take-over are determined with respect to each combination of the current server and the backup server. In addition, with respect to each combination of the current server and the backup server, a configuration matching rate indicating the ratio of hardware configuration matching is calculated. Based on information about the presence or absence of hardware configuration concealment, information about the possibility of a take-over, and information about the configuration matching rate with respect to each combination of the current server and the backup server, the backup server as a take-over destination of the current server is allocated.

Abstract: A data processing method, a device, and a system for a storage unit in order to avoid performing repeated data read operations on the storage unit where the method includes recording, by a first server for at least one storage unit used to store data, information about a storage unit in which a repairable fault occurs but repairing fails, querying, by the first server each time a request for reading data is received, whether the storage unit corresponding to the recorded information about the storage unit stores a part or all of the data, and when the storage unit corresponding to the recorded information stores the data, returning, to a requesting party that sends the request, a message indicating that reading the data fails, or otherwise, reading the data from a storage unit that stores the data, and feeding back the data to the requesting party that sends the request.

Abstract: One or more techniques and/or systems are provided for interconnect failover between a primary storage controller and a secondary storage controller. The secondary storage controller may be configured as a backup or failover storage controller for the primary storage controller in the event the primary storage controller fails. Data and/or metadata describing the data (e.g., data and/or metadata stored within a write cache) may be mirrored from the primary storage controller to the secondary storage controller over one or more interconnect paths. Responsive to identifying a failover trigger for a failed interconnect path, the secondary storage controller is instructed to fence (e.g., block) I/O operations from the failed interconnect path. Streams of data and/or metadata that were affected by the failure may be instructed to transmit such data and/or metadata over one or more non-failed interconnect paths to the secondary storage controller during failover of the failed interconnect path.

Abstract: Exemplary embodiments for optimizing disaster recovery systems during takeover operations are provided. In one embodiment, by way of example only, a flag is set in a replication grid manager to identify replication grid members to consult in a reconciliation process for resolving intersecting and non-intersecting data amongst the disaster recovery systems for a takeover operation, including indicating those of the replication grid members that acquired ownership over cartridges belonging to source systems.

Abstract: Methods, systems, and computer program products for preventing non-detectable data loss during site switchover are disclosed. A computer-implemented method may include receiving a request to perform a switchover from a first node to a second node, determining whether to place a storage volume involved in the switchover in a suspended state, setting the storage volume in the suspended state based on determining that the storage volume is to be placed in the suspended state, and maintaining the storage volume in the suspended state after completing the switchover. In an example, the storage volume may be placed in a suspended state based on examining a volume-specific attribute indicating whether the storage volume is to be suspended when involved in a switchover. In one example, each storage volume involved in a switchover may be placed in a suspended state when indicated as part of a switchover request.

Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.

Abstract: In one or more aspects, a determination is made as to whether a connector is securely fastened, whether the connector connected within a socket structure is the expected connector for that socket structure, and/or whether connectors coupled to one another via one or more cables are properly positioned for communication between them. Information on selected physical connection elements of a connector is used to determine one or more structural characteristics of the cable(s) connected to the connector and to determine whether the connector is the expected connector for a particular socket structure.

Abstract: An information processing system, computer readable storage medium, and method with an integrated development environment to guide development of applications to implement a programming design objective. A method includes analyzing a selected portion of source code according to meeting each programming design objective from a set of programming design objectives; selecting, based on the analyzing, at least one programming design objective from the programming design objectives, the selected at least one programming design objective being determined suitable for the selected portion of source code based on one of conforming with constraints of the objective, or failing to conform and determining a quick fix can be applied by update to the source code to make it conform. The method outputs a message corresponding to the selected portion of source code and indicative of the selected programming design objective suitable for the portion of source code.

Abstract: A pre-initialized value of contents of a memory location is identified. A load value of contents loaded from the memory location by execution of a first instruction that loads from the memory location is also identified. A comparison is made between the load value and the pre-initialized value. Based on the comparison, a determination is made that the load value and the pre-initialized value are the same. In response to this determination, it is indicated that the first instruction contains an uninitialized memory reference.

Abstract: A debugging module determines by analysis of code build information of a system with an identified error, where to set a debug entry point at which to start execution of the system during a program subset debug session. Debug entry point metadata for the program subset debug session is captured in association with a subsequent execution of the system. The captured debug entry point metadata includes an initial file state of at least one file accessed by the system, any file inputs and file outputs (I/Os) detected as being performed by the system during the subsequent execution of the system up to the debug entry point, and an image of all instantiated objects at the debug entry point.

Abstract: In some aspects, a debugging application can obtain log data from a target device. The log data can be generated from the execution of object code by the target device. The object code can be generated from assembly code for the target device. For each of multiple program counter entries in the log data, the debugging application can identify a correspondence between the program counter entry and a respective portion of the assembly code and simulate a respective operation performed by the execution of the object code. The simulated operation corresponds to the program counter entry. Simulating the execution can include configuring a display device to display a visual indicator for the portion of the assembly code that caused a given operation. The visual indicator is displayed based on the identified correspondence between a portion of the assembly code and a program counter entry from the log data.