Abstract: Error logs, bug reports, and other databases identifying problems with a tracer system may be mined to determine how a tracer may interact with a given function, module, or other group of functions. Based on such reports, a tracer may be configured to avoid certain functions or to trace such functions in a specific manner. In some cases, tracer may be configured to limit tracing to certain parameters or with other limitations to avoid any known conditions under which errors occur.

Abstract: A method, computer program product, and computer system for receiving, by a computing device, a selection of one or more files for which to have one or more automated unit tests generated for an application under test. An action in the application under test is received while the application under test is used. Behavior data of how the application under test responds to the action is tracked, wherein tracking is performed by inserting observer code using aspect oriented programming method, which tracks each method's interaction with its own objects and objects that are passed to it. An automated unit test of the one or more automated unit tests is generated for underlying code of the application under test invoked when receiving the action based upon, at least in part, the behavior data of how the application under test responds to the action.

Abstract: Approaches for more efficiently executing calls to native code from within a managed execution environment are described. The techniques involve attempting to execute a native call, such as a call to a C function from within Java code, using a single hardware transaction. Not only is the native code executed in a hardware transaction, but also various transitional operations needed for transitioning between managed execution mode and native execution mode. If the hardware transaction is successful, at least some of the operations that would normally be performed during transitions between modes may be omitted or simplified. If the hardware transaction is unsuccessful, the native calls may be performed as they normally would, outside of hardware transactions.

Abstract: When a monitoring device for ladder program receives designation of a ladder program which is a confirmation object from a user, the monitoring device detects a branch circuit which is arranged above the ladder circuit which is the confirmation object in a ladder program and is closest to the ladder circuit and extracts a branch circuit which is to be a display object from the ladder program based on a type of the branch circuit which is detected. The monitoring device executes such processing up to a head of the ladder program so as to extract and display branch circuits up to the ladder circuit which is the confirmation object.

Abstract: According to one embodiment, a storage system includes a first storage and a controller which controls the first storage. The first storage includes a first group which includes a plurality of pages which are data write units and include first nonvolatile memories, and a first counter which counts the number of data writes to the first group. The controller determines whether all the pages in the first group has been written to or not.

Abstract: According to one embodiment, a method for controlling a nonvolatile memory includes allocating a first system block to a physical block included in one of the first and second parallel operation elements. The first system block is used by a first CPU controlling the nonvolatile memory but is not used by a second CPU controlling the nonvolatile memory. The method includes allocating a second system block to a physical block included in the other of the first and second parallel operation elements. The second system block is used by the second CPU but is not used by the first CPU.

Abstract: A storage device is provided as follows. A nonvolatile memory device includes blocks, each block having sub-blocks erased independently. A memory controller performs a garbage collection operation on the nonvolatile memory device by selecting a garbage collection victim sub-block among the sub-blocks and erasing the selected garbage collection victim sub-block to generate a free sub-block. The memory controller selects the garbage collection victim sub-block using valid page information of each sub-block and valid page information of memory cells adjacent to each sub-block.

Abstract: Various embodiments include methods for reclaiming memory in a computing device that may include storing a first pointer pointing to a first memory location storing the beginning of a data structure in which a plurality of threads executing on the computing device may concurrently access the data structure and storing a second pointer pointing to the current beginning of the data structure. In response to performing an operation on the data structure that changes the location of the beginning of the data structure from the first memory location to a second memory location, the second pointer may be updated to point to the second memory location. In response to determining that memory allocated to the data structure may be reclaimed, memory allocated to the data structure, including memory located at the first memory location pointed to by the first pointer, may be reclaimed.

Abstract: In one embodiment, a method comprising organizing access request by a processor to elements of textures, wherein a storage representation of a plurality of all the textures has a much larger size than a capacity of processor memory, wherein the plurality of all the textures is stored only out-of-core, wherein the processor requests access to incoherent data locations randomly distributed across the plurality of all the textures.

Abstract: A computing system includes: an adaptive back-up controller configured to calculate an adaptive back-up time based on a reserve power source for backing up a volatile memory to a nonvolatile memory; and a processor core, coupled to the adaptive back-up controller, configured to back up at least a portion of the volatile memory to the nonvolatile memory within the adaptive back-up time based on a back-up priority.

Abstract: A memory system has a first cache memory comprising a volatile memory, a second cache memory comprising a non-volatile memory with access speed slower than access speed of the volatile memory, and a reconfiguration control circuitry to switch between a first mode that uses the second cache memory as a cache memory in a lower layer than the first cache memory and a second mode that uses the first cache memory and the second cache memory as cache memories in an identical memory layer.

Abstract: A processor and method are described for alias detection. For example, one embodiment of an apparatus comprises: reordering logic to receive a set of read and write operations in a program order and to responsively reorder the read and write operations; adjustment information attachment logic to associate adjustment information with one or more of the set of read and write operations, wherein for a read operation the adjustment information is to indicate a number of write operations which the read operation has bypassed and for a write operation the adjustment information is to indicate a number of read operations which have bypassed the write operation; and out-of-order processing logic to determine whether execution of the reordered read and write operations will result in a conflict based, at least in part, on the adjustment information associated with the one or more reads and writes.

Abstract: A memory access control device of an embodiment includes a data memory configured to record information of an access request relating to reading and writing of data to a main memory, and a controller configured to receive notification of the access request and select an access destination with reference to recording content of the data memory. When history of a request for write access and history of a request for read access to an address designated by the access request are recorded in the data memory, the controller selects a cache memory as the access destination, and otherwise, selects the main memory as the access destination.

Abstract: A Solid State Drive (SSD) is disclosed. The SSD can include a host interface logic, a data input buffer, a data output buffer, and a buffer manager to manage the data input buffer and data output buffer. A re-order logic can advise the buffer manager about which data should be returned to the host computer from the data output buffer.

Abstract: According to one embodiment, a storage device includes a storage portion storing a first entry, the first entry includes a first translation table corresponding between a first logical address and a first physical address on a nonvolatile memory, and a first state showing that data at the first physical address is a valid as data at the first logical address, and a controller adding a second entry in the storage portion and changing the first state to a second state when receiving a command from a host, the second entry includes a second translation table corresponding between a second logical address and the first physical address, and a third state showing that the first physical address of the second translation table is referring to the first physical address of the first translation table, the second state showing that the first physical address of the first translation table is shared with the first physical address of the second translation table.

Abstract: Techniques to prelink software to improve memory de-duplication in a virtual system are described. An apparatus may comprise a processor circuit, a memory unit coupled to the processor circuit to store private memory pages for multiple virtual machines, and a dynamic linker application operative on the processor circuit to link a binary version of a software program with associated program modules at run-time of the binary version on a virtual machine. The dynamic linker application may comprise a master prelink component operative on the processor circuit to relocate a first set of program modules for a first binary version of the software program for a first virtual machine using a first set of virtual memory addresses from a first private memory page allocated to the first virtual machine, and store relocation information for the first set of program modules in a global prelink layout map for use by a second virtual machine. Other embodiments are described and claimed.

Abstract: A storage apparatus includes a physical memory including a plurality of first memory lines a part of which are assigned consecutive addresses and the rest of which are put into an unassigned state where no address is assigned and a second memory line assigned one of the consecutive addresses. The storage apparatus determines based on an address whether a write access to the physical memory is a write access to a first memory line or the second memory line, counts the numbers of times the first memory lines are written and the number of times the second memory line is written, and uses, when the total sum of the counted numbers of times exceeds a threshold, a first memory line in the unassigned state for swapping the address assigned to the second memory line with one of the addresses assigned to the part of the first memory lines.

Abstract: A method for mapping virtual memory pages to physical memory pages is described. The method includes receiving a mapping of a virtual memory page to multiple physical memory pages, detecting a request for a transaction to be performed on data contained in the multiple physical memory pages, in which the transaction includes a number of data updates, determining which of the number of multiple physical memory pages contains a latest version of the data to be updated by the transaction, updating a physical memory page by performing the transaction within a physical memory page among the multiple physical memory pages that does not contain the latest version of the data, and updating an indication of which of the physical memory pages contains the latest version of the data pertaining to the transaction.

Abstract: A host system includes a host device, a host buffer memory, and storage device. The host device includes a plurality of cores. The host buffer memory is configured to store a first command queue and a first map table, wherein each of the first command queue and the first map table corresponds to a first core of the cores. The storage device is configured to perform an input/output virtualization operation using the first core as a virtual core. The storage device uses the first command queue and the first map table during the input/output virtualization operation using the first core.

Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being emulated. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field or the fetch protection field is not enabled.

Abstract: A processing device includes a processing unit that executes a memory access instruction, a cache memory, and a cache control unit. The cache control unit includes a cache hit determining unit that determines a cache hit or not, based on the memory access instruction, a read counting unit that increments a count value of read instructions, a write counting unit that increments a count value of write instructions, a replacement criteria generating unit that, based on the count value of read instructions and the count value of write instructions, generates a target read area capacity and a target write area capacity which minimize an average memory access time needed to access the main memory device, and a replacement control unit that controls replacement of an area in the cache memory, based on the target read area capacity and the target write area capacity.

Abstract: Various embodiments for grouping tracks for destaging by a processor device in a computing environment are provided. Tracks are selected for destaging from a least recently used (LRU) list and the selected tracks are moved to a destaging wait list. One of the selected tracks is selected from the destaging wait list and the selected tracks are grouped for destaging. A first track and a last track are located from the group of selected tracks of the destaging wait list. The destaging is commenced from the first track in the group of selected tracks. A track is added to the group of selected tracks if the track is one of modified and located in a cache, otherwise, a next one of the selected tracks in the group of selected tracks is moved to.

Abstract: Computer-readable storage media, computing devices and methods associated with file cache management are discussed herein. In embodiments, a computing device may include a file cache and a file cache manager coupled with the file cache. The file cache manager may be configured to implement a context-aware eviction policy to identify a candidate file for deletion from the file cache, from a plurality of individual files contained within the file cache, based at least in part on file-level context information associated with the individual files. In embodiments, the file-level context information may include an indication of access recency and access frequency associated with the individual files. In such embodiments, identifying the candidate file for deletion from the file cache may be based, at least in part, on both the access recency and the access frequency of the individual files. Other embodiments may be described and/or claimed.

Abstract: A mechanism for managing storage block of a data volume is disclosed. A method includes determining, by a processing device, whether a current data is to be written into an entirety of a storage block of a data volume of an operating system. The method also includes deleting, by the processing device, all of previously written data on the storage block before writing the current data into the storage block in response to determining that the current data is not to be written into the entirety of the storage block. The current data is different from the previously written data.

Abstract: According to one embodiment, a system includes one or more memory units and one or more processors. The processors are configured to receive a plurality of data elements. The processors are also configured to, for a first data element of the plurality of data elements, generate a first token for the first data element, and transmit the first token to a device. The processors are further configured to individually encrypt the first data element, and break the first encrypted data element into a plurality of encrypted data portions including a first encrypted data portion and a second encrypted data portion. The processors are further configured to transmit the first encrypted data portion of the first encrypted data element for storage in a first data storage device, and transmit the second encrypted data portion of the first encrypted data element for storage in a second data storage device.

Abstract: A data management method includes receiving, by a terminal device, data stored in a first storage provided in an information processing device and storing the received data in a second storage provided in the terminal device, transmitting, to the information processing device, differential data between the data stored in the second storage and first updated data obtained by updating the data stored in the second storage, creating first encrypted data by encrypting the first updated data, deleting part of the created first encrypted data from the second storage, creating, by the information processing device, second encrypted data by encrypting second updated data obtained by updating the differential data transmitted from the terminal device, transmitting, to the terminal device, part of the second encrypted data which is identical in contents to the part of the first encrypted data deleted by the terminal device.

Abstract: A method and system for protecting the integrity of a memory system. An age counter and an opportunity counter are provided for each of multiple memory blocks. An epoch counter is provided for the memory system. Data is written in a selected memory block which increases the local sequence number of the selected memory block. The opportunity counter for the selected memory block is updated if the local sequence number of the selected memory block rolls over. A message authentication code (MAC) is generated in the selected memory block based on a global sequence number and the local sequence number. The age counter and the opportunity counter are updated for memory blocks when the opportunity counter for the memory blocks matches the LSB of the epoch counter. A new MAC is generator for any memory block for which the updating is performed.

Abstract: A method for privilege based memory pinning is provided. The method includes receiving a request to pin an amount of address space memory from a process executing on an operating system. The operating system includes a configurable mode of operation. In mandatory mode, the operating system executes the request to pin address space memory based on the role hierarchy-based privilege level of the requestor process. When the requested amount is greater than the operating system's amount of memory that can be used to pin memory, the operating system fails the request. However, when the operating can satisfy the request from processes having a lower privilege level relative to the requestor process, memory is unpinned from one or more of these processes.

Abstract: A method and an apparatus for accessing physical resources, is used to restrict access to physical resources of other light system kernel Light OSs by a first Light OS in a multi-kernel operating system and ensure security of accessing physical resources among the Light OSs. A method, executed by secure firmware, includes: receiving a physical address corresponding to a physical resource to be accessed by the first Light OS; determining whether the physical address corresponding to the physical resource is out of bounds; and if the physical address corresponding to the physical resource is within bounds, sending an access continuity signal to the first Light OS; or if the physical address corresponding to the physical resource is out of bounds, sending an access error signal to the first Light OS.

Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.

Abstract: A method is provided for use in a host module, for identifying at least one accessory module on a bus, wherein the bus is configured to allow multiple accessory modules to be connected to the host module. The method includes sending a query to any accessory module connected to the bus, the query concerning whether the or each accessory module meets a specified criterion; and receiving synchronised responses from any accessory module that meets the specified criterion connected to the bus where said responses are specific to the query but non-specific to an effectively uniquely distinguishing feature of the individual module. It is then possible to determine from redundant information contained in an aggregate of the synchronised responses whether there is (a) no accessory module meeting the specified criterion, or (b) at least one accessory module meeting the specified criterion.

Abstract: According to one aspect, a module 11_1 includes a communication circuit 111 that performs data communication with an externally-provided control device 12 through a communication bus 13, and an interrupt signal generation circuit 113 that, when an interrupt instruction signal I1 output from the communication circuit 111 becomes an active state, generates an interrupt signal and outputs the generated interrupt signal to the communication bus 13, the interrupt signal being defined by using a bus potential undefined in a data communication standard.

Abstract: An integrated-circuit radio communication device (1) comprises a processor (7) having a hardware-interrupt input line; memory (13); radio communication logic (17); and interrupt-interface logic (8). The memory (13) contains a firmware module (23) comprising (i) instructions (31) for controlling the radio communication logic (17) according to a predetermined radio protocol, and (ii) an interrupt routine comprising instructions for receiving an identification of a radio communication function in the firmware module (23) and for invoking the identified radio communication function. The interrupt-interface logic (8) comprises input logic for receiving a signal generated by software (27) executing on the device (1), and output logic arranged to assert the hardware-interrupt input line of the processor (7) in response to receiving a software-generated signal at the input logic.

Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

Abstract: In some aspects, a quantum computing system includes a control system and a quantum processor cell. The control system generates quantum processor control information for a group of devices housed in the quantum processor cell, and each device in the group has a distinct operating frequency. In some cases, a waveform generator generates a multiplexed control signal based on the quantum processor control information, and the multiplexed control signal is communicated an input signal processing system. In some cases, the input signal processing system includes an input channel configured to receive the multiplexed control signal, a de-multiplexer configured to separate device control signals from the multiplexed control signal, and output channels configured to communicate the respective device control signals into the quantum processor cell.

Abstract: In an embedded system, there are a plurality of data requesting devices, a plurality of data sources and a bus fabric interconnecting the data requesting devices and the data sources, wherein the bus fabric comprises a plurality of bus components. Some or all of the data sources and arbitration devices associated with the bus components resolve contentions between data bursts by selecting a first one of the contending data bursts; determining a length of a critical section of the first selected data burst; and processing the critical section of the selected data burst. Then, a second one of the contending data bursts is selected, a length of a critical section of the second selected data burst is determined, and the critical section of the second selected data burst is processed before a non-critical section of the selected data burst.

Abstract: A controller includes a pseudo device circuit connected to a target device with a bus and a reset line, the pseudo device circuit acquiring from the bus an instruction input to the target device and a response to the instruction input, predicting a response of the target device to the instruction acquired, and outputting a fault report when a difference is detected between a predicted response and an acquired response, and outputting a reset signal to the reset line; and a master circuit connected to the target device with the bus, the master circuit transmitting the instruction to the target device through the bus, and performing initial setting of the target device based on the fault report from the pseudo device circuit.

Abstract: Methods and apparatus for augmenting routing resources. In one exemplary embodiment, a Thunderbolt™ transceiver incorporates a Peripheral Component Interconnect Express (PCIe) bus that supports hot-plugging and hot-unplugging of peripheral devices. Unfortunately, for various backward compatibility reasons, existing PCIe bus enumeration protocols can quickly exhaust the PCIe routing resources (for example, PCIe bus numbers) resulting in undesirable consequences (for example, crashes, dead connections, etc.) The present disclosure describes schemes for augmenting the pool of PCIe bus numbers and dynamically re-assigning PCIe bus numbers, so as to eliminate the aforementioned concerns.

Abstract: An information processing system according to the present invention includes: a plurality of processing units; a plurality of input/output units controlled by any one of the processing units; a plurality of first connection units connecting one of the processing units to a first communication channel; a second connection unit connecting the input/output units to a second communication channel; a first mediating unit mediating the second communication channel and a communication network, and transmits identifiers of the input/output units via the communication network; and a plurality of second mediating units mediating a connection between the communication network and the first communication channel, receiving the identifier, and, when an identifier of its own is included in the received identifiers, establishing a connection between the input/output unit with the own identifier and the processing unit and detaches connections between the input/output unit with different identifier and the processing unit.

Abstract: The present disclosure provides a method for managing buffers of a device for Universal Serial Bus (USB) communication in a wireless environment. The method includes determining respective current data storage levels of transmit buffers that store different types of data for USB communication; comparing the respective current data storage levels of the transmit buffers with corresponding respective predetermined threshold levels; and controlling an input rate or output rate of a first transmit buffer if it is determined based on the comparison that the first transmit buffer has a current data storage level that exceeds a predetermined threshold level.

Abstract: Peripherals (18, 20, 22, 24, 26) are connected to a processor (6) and a programmable peripheral interconnect (10) is connected to each peripheral. One of the peripherals (18) is configured to signal an event to the interconnect, and one of the peripherals (20) is configured to respond to a task signal from the interconnect by performing a task. The task-receiving peripheral (20) has a task register (40), addressable by the processor (6), and performs the task in response to a change in the contents of the register (40). The interconnect (10) accesses a memory (14) in which a mapping is stored between an event of a first peripheral (18) and a task of a second peripheral (20), the mapping comprising (i) an identification of the event, and (ii) the address of a task register (40). The mapping causes the interconnect (10) to provide a channel by sending a task signal to the second peripheral (20) in response to a signal of the event from the first peripheral (18).

Abstract: According to one embodiment, a storage device includes a memory, a controller, an interface unit, a switch, and a switch control unit. The memory stores data. The controller is configured to control writing of data to the memory and reading of data from the memory. The interface unit includes a first terminal, a second terminal, and a third terminal. The first terminal has an electrical status different between a case where the storage device and a first device are connected, and a case where the storage device and a second device are connected. Through the second terminal, voltage is applied by the first device to the storage device in the case where the storage device and the first device are connected, and a control signal is input from the second device to the storage device in the case where the storage device and the second device are connected. Through the third terminal, power is supplied to the storage device. The switch switches a connection status and a disconnection status.

Abstract: Methods, computing systems and computer program products implement embodiments of the present invention that include configuring distributed storage system resources for a distributed storage system. Examples of the storage system resources include a plurality of network segments, one or more network devices coupled to the network, and multiple nodes coupled to the network, the nodes including both frontend and backend nodes. Upon receiving, by a given frontend node in the distributed storage system, an input/output (I/O) request, one or more of the distributed storage system resources required to process the I/O request are identified, and a respective load that the I/O request will generate on each of the identified distributed storage system resources is calculated. The distributed storage system processes the I/O request upon detecting that the respective loads are less than respective available capacities of the identified distributed storage system resources.

Abstract: In accordance with methods of the present disclosure, a system may include a switch and a management controller communicatively coupled to the switch. The switch may be configured to route input/output communications between a processor and a device. The management controller may be configured to, based on a measured bandwidth of communications of a communication link between the switch and the device, dynamically control at least one of a link width and a per-lane link speed of the communication link.

Abstract: An input/output device for an electric or electronic cabinet grouping together a plurality of devices such as computers. The input/output device includes input/output channels, conversion units and at least one computing unit. The conversion unit is connected to the input/output channels and to the computing unit. A digital network link protocol management unit is connected to the computing unit and to at least one transceiver. The computing unit executes software to provide a digital transmission of data representative of the input/output values between the network and the computers via the transceiver. An electric cabinet grouping together computers, each computer provided with a transceiver. The electric cabinet includes the input/output device.

Abstract: The present invention provides a system comprising a neurosynaptic processing device including multiple neurosynaptic core circuits for parallel processing, and a serial processing device including at least one processor core for serial processing. Each neurosynaptic core circuit comprises multiple electronic neurons interconnected with multiple electronic axons via a plurality of synapse devices. The system further comprises an interconnect circuit for coupling the neurosynaptic processing device with the serial processing device. The interconnect circuit enables the exchange of data packets between the neurosynaptic processing device and the serial processing device.

Abstract: Methods and apparatus for equalization of a high speed serial bus. Various aspects of the present disclosure are directed to a well-tuned passive equalization circuit for use with high frequency differential signals that suffer from e.g., impedance mismatches, impedance discontinuities (e.g., connectors, etc.). In one embodiment, a shunting circuit is inserted between the differential terminals of a Universal Serial Bus (USB) cable, connector, etc. The shunting circuit is configured to “open” at low frequencies to enable Full Speed (FS) enumeration, while also providing sufficiently high impedance at high frequencies to enable High Speed (HS) operation. In one such implementation, the shunting circuit includes a tuned resistor, capacitor, inductor, and switch element arranged in series.

Abstract: A semiconductor storage device according to one embodiment includes a memory cell. A first latch is selectively coupled to the memory cell. A first bus coupled to the first latch and a second latch. A first charger charges the first bus. A second bus transmits a signal of the same value both when first data is output and when second data is output from the first or second latch A second charger raises a voltage of the second bus from a first value to a second value. A controller whose input is coupled to the second bus controls the first charger to stop charging of the first bus based on the voltage of the second bus having reached the second value.

Abstract: A microcontroller device has a housing with a plurality of external pins having a plurality of input/output pins, a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, and a pad ownership multiplexer unit being controllable to assign control of the input/output pins to either the first microcontroller or the second microcontroller, wherein the number of external pins is less than the sum of a data buswidth of the first and second microcontroller.

Abstract: A microcontroller device has a housing with a plurality of external pins a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, and a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, wherein first and second microcontroller communicate only via a dedicated interface.