Abstract: FinFET and fabrication method thereof. The FinFET fabrication method includes providing a semiconductor substrate; forming a plurality of trenches in the semiconductor substrate, forming a buffer layer on the semiconductor substrate by filling the trenches and covering the semiconductor substrate, and forming a fin body by etching the buffer layer. The FinFET fabrication method may further includes forming a insulation layer on the buffer layer around the fin body; forming a channel layer on the surface of the fin body; forming a gate structure across the fin body; forming source/drain regions in the channel layer on two sides of the gate structure; and forming an electrode layer on the source/drain regions.

Abstract: A semiconductor device includes a fin structure on a substrate and extending in a first direction, a gate electrode crossing over the fin structure, source/drain regions on the fin structure at opposite sides of the gate electrode, and a barrier layer between the fin structure and each of the source/drain regions. The fin structure includes a material having a lattice constant different from that of the substrate, the fin structure, the source/drain regions, and the barrier layer include germanium, and a germanium concentration in the barrier layer is greater than that in the fin structure and less than a maximum germanium concentration in each of the source/drain regions.

Abstract: A non-planar transistor is provided. It includes a substrate, a fin structure, a gate structure, a spacer structure and a source/drain region. The fin structure is disposed on the substrate, the gate structure is disposed on the fin structure. The spacer structure is disposed on a sidewall of the gate structure. The spacer structure includes a first spacer with a first height and a second spacer with a second height, wherein the first spacer is disposed between the second spacer, and the first height is different from the second height. The source/drain region is disposed in a semiconductor layer at two sides of the spacer structure. The present invention further provides a method of forming the same.

Abstract: The present invention provides a thin film transistor and a method of fabricating the same, an array substrate and a display device. The thin film transistor comprises a gate, an active layer, a source and a drain formed on a substrate, the active layer comprises an oxide having doped ions, the doped ions have a p-orbital electron arrangement structure, and an energy level of p-orbital of the doped ions is higher than that of 2p-orbital of oxygen ions in the oxide, so that top of valence band of the active layer is higher than the energy level of oxygen vacancies formed in the oxide. The active layer of the thin film transistor is made of the oxide having the doped ions, which may improve a stability of the thin film transistor, and there is no need to add a light blocking structure in the display device.

Abstract: An array substrate provided according to the present disclosure may include: a base substrate; a gate electrode and a gate insulating layer sequentially formed on the base substrate; a semiconductor layer formed on the base substrate on which the gate insulating layer has been formed; and a source electrode and a drain electrode formed on the base substrate on which the semiconductor layer has been formed. The semiconductor layer may be connected to the source electrode and the drain electrode respectively. A first connection region in which a first connection point is located may be arranged between the semiconductor layer and the source electrode. And a second connection region in which a second connection point is located may be arranged between the semiconductor layer and the drain electrode.

Abstract: A miniaturized transistor with less variation and highly stable electrical characteristics is provided. Further, high performance and high reliability of a semiconductor device including the transistor are achieved. A semiconductor and a conductor are formed over a substrate, a sacrificial layer is formed over the conductor, and an insulator is formed to cover the sacrificial layer. After that, a top surface of the insulator is removed to expose a top surface of the sacrificial layer. The sacrificial layer and a region of the conductor overlapping with the sacrificial layer are removed, whereby a source region, a drain region, and an opening are formed. Next, a gate insulator and a gate electrode are formed in the opening.

Abstract: A modulation circuit includes a load and a transistor serving as a switch. The transistor has an oxide semiconductor layer in which hydrogen concentration is 5×1019/cm3 or less. The off-state current of the transistor is 1×10?13 A or less. A modulation circuit includes a load, a transistor serving as a switch, and a diode. The load, the transistor, and the diode are connected in series between the terminals of an antenna. The transistor has an oxide semiconductor layer in which hydrogen concentration is 5×1019/cm3 or less. An off-state current of the transistor is 1×10?13 A or less. On/off of the transistor is controlled in accordance with a signal inputted to a gate of the transistor. The load is a resistor, a capacitor, or a combination of a resistor and a capacitor.

Abstract: In a channel protected thin film transistor in which a channel formation region is formed using an oxide semiconductor, an oxide semiconductor layer which is dehydrated or dehydrogenated by a heat treatment is used as an active layer, a crystal region including nanocrystals is included in a superficial portion in the channel formation region, and the rest portion is amorphous or is formed of a mixture of amorphousness/non-crystals and microcrystals, where an amorphous region is dotted with microcrystals. By using an oxide semiconductor layer having such a structure, a change to an n-type caused by entry of moisture or elimination of oxygen to or from the superficial portion and generation of a parasitic channel can be prevented and a contact resistance with a source and drain electrodes can be reduced.

Abstract: To give favorable electrical characteristics to a semiconductor device. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a pair of electrodes over the semiconductor layer and each electrically connected to the semiconductor layer, a gate electrode over the semiconductor layer, and a gate insulating layer between the semiconductor layer and the gate electrode. The insulating layer includes an island-shaped projecting portion. A top surface of the projecting portion of the insulating layer is in contact with a bottom surface of the semiconductor layer, and is positioned on an inner side of the semiconductor layer when seen from above. The pair of electrodes covers part of a top surface and part of side surfaces of the semiconductor layer. Furthermore, the gate electrode and the gate insulating layer cover side surfaces of the projecting portion of the insulating layer.

Abstract: A thin film transistor, a method of fabricating the same, an array substrate and a display device are disclosed. The method of fabricating the thin film transistor comprises: forming a semiconductor layer; forming a conductive film that does not react with acid solution on the semiconductor layer to be employed as a protective layer; forming a source electrode and a drain electrode on the protective layer; and removing a portion of the protective layer between the source electrode and the drain electrode to expose a portion of the semiconductor layer between the source electrode and the drain electrode.

Abstract: An object is to provide a method for manufacturing a semiconductor device without exposing a specific layer to moisture or the like at all. A thin film element is manufactured in such a manner that a first film, a second film, and a third film are stacked in this order; a resist mask is formed over the third film; a mask layer is formed by etching the third film with the use of the resist mask; the resist mask is removed; a second layer and a first layer are formed by performing dry etching on the second film and the first film with the use of the mask layer; a fourth film is formed to cover at least the second layer and the first layer; and sidewall layers are formed to cover at least the entire side surfaces of the first layer by performing etch back on the fourth film.

Abstract: A thin-film transistor includes a substrate, a semiconductor channel region, a gate insulating layer, a source region, a drain region, a source electrode, a drain electrode and a gate electrode. The thin-film transistor also includes a carrier injection terminal, and the carrier injection terminal can provide the semiconductor channel region with a carrier of which the polarity is opposite to that of a channel carrier when the thin-film transistor is conducting. The thin-film transistor can significantly reduce device degradation and threshold voltage shift caused by a dynamic hot carrier effect, thereby improving the reliability of a thin-film transistor device and a circuit and simplifying the complexity of the design of a threshold voltage compensation circuit. In addition, the thin-film transistor has low processing difficulty and has no influence on the normal operation of a device.

Abstract: The present disclosure provides a TFT, an array substrate and a fabricating method thereof and a display device. The TFT includes a gate, an active layer, a first electrode and a second electrode, the first electrode is arranged at one side of the active layer, the second electrode is arranged at the other side of the active layer, the first electrode, the active layer and the second electrode forms a stacked structure, the gate is arranged to surround the stacked structure, and the gate and the stacked structure are insulated and separated from each other. Under fixed occupation area, the conductive channel of the TFT of the present disclosure has increased width, so drain current in saturation region is increased without impacting aperture ratio of a display panel, which further optimizes performance of the TFT and the array substrate, and improves display effect of the display device.

Abstract: A photoelectric conversion device including a photoelectric converter, a transparent cover, an insulating material layer and a photonic crystal layer is provided. The photoelectric converter is adapted to receive a light. The transparent cover is disposed on a side of the photoelectric converter. The insulating material layer is disposed between the photoelectric converter and the transparent cover. The photonic crystal layer is disposed between the insulating material layer and the transparent cover, wherein the material of the photonic crystal layer is different from the material of the insulating material layer.

Abstract: A solar cell includes: a semiconductor substrate having a light receiving surface and a back surface; a first semiconductor layer of the first conductivity type on the back surface; a second semiconductor layer of the second conductivity type on the back surface; a first electrode electrically connected to the first semiconductor layer; and an insulating layer for electrically insulating the first semiconductor layer and the second semiconductor layer from each other in a region in which an edge of the first semiconductor layer and an edge of second semiconductor layer overlap. The first electrode includes a first transparent electrode layer and a first collection electrode layer on the first transparent electrode layer. The first transparent electrode layer is separated into a primary electrode layer that is on the first semiconductor layer and a separated electrode layer that is on the second semiconductor layer in the region.

Abstract: A solar cell includes: a semiconductor substrate having a light-receiving surface and a back surface; a first-conductivity-type first semiconductor layer on the back surface; a second-conductivity-type second semiconductor layer on the back surface; a first electrode electrically connected to the first semiconductor layer; a second electrode electrically connected to the second semiconductor layer; and an insulating layer in a boundary region between a first-conductivity-type region of the first semiconductor layer and a second-conductivity-type region of the second semiconductor layer. The insulating layer has an inclined side surface adjacent the second-conductivity-type region inclined such that the thickness of the insulating layer decreases with decreasing distance from the second-conductivity-type region.

Abstract: Back contact back junction solar cell and methods for manufacturing are provided. The back contact back junction solar cell comprises a substrate having a light capturing frontside surface with a passivation layer, a doped base region, and a doped backside emitter region with a polarity opposite the doped base region. A backside passivation layer and patterned reflective layer on the emitter form a light trapping backside mirror. An interdigitated metallization pattern is positioned on the backside of the solar cell and a permanent reinforcement provides support to the cell.

Abstract: The present invention provides materials with high bulk photovoltaic effect response. The present invention also provides for products comprising the high bulk photovoltaic effect materials of the present invention.

Abstract: A new-generation photovoltaic flexible film offering high efficiency results from the combination of an ultra-thin and very flexible photovoltaic film with a very thin, antireflection, prismatic film absorbing energy from solar radiation and righting the angle of the solar rays is provided. The process of the invention allows encasement of the photovoltaic modules and the prismatic film by an assembly of flexible polymer thermoplastic thin films and resinless thermofusion in vacuo.

Abstract: Disclosed is a solar cell including a semiconductor substrate, a conductive area including a first conductive area and a second conductive area formed on one surface of the semiconductor substrate, a passivation film formed on the conductive area, the passivation film having a contact hole, a protective film formed on the conductive area inside the contact hole, the protective film being formed on at least one of at least a portion of an inner side surface of the contact hole and the passivation film, and an electrode electrically connected to the conductive area through the contact hole with the protective film interposed therebetween.

Abstract: The present application relates to an encapsulant for a PV module, a method of manufacturing the same and a PV module. The encapsulant according to an embodiment of the present application has excellent heat resistance or the like and improved creep physical properties, and thus even when the encapsulant is used under conditions of a high temperature and/or high humidity for a long time, deformation is small and the encapsulant can exhibit excellent adhesive strength. Accordingly, when the encapsulant is applied to a PV module, durability or the like may be improved.

Abstract: This solar cell module is provided with: solar cells; a first protective member winch is provided over a light-receiving-surface side of the solar ceils; a second protective member which is provided over a rear-surface side of the solar cells; and a sealing layer which is provided between the protective members, and which seals the solar cells. A light receiving surface-side area of the sealing layer, said area being positioned further towards the first protective member side than the solar cells, includes: a wavelength conversion material which absorbs light of a specific wavelength, and converts said wavelength: and an ultraviolet-ray absorption material which selectively absorbs ultraviolet rays.

Abstract: A photovoltaic interconnect wire includes a conductive base strip with grooves provided thereon, and the grooves are linear and/or curved strip-shaped grooves (3) arranged obliquely to a longitudinal direction of the conductive base strip. An inclination angle of 15° to 75° is present between each linear strip-shaped groove and the longitudinal direction of the conductive base strip, and between a tangent line of any point on the curve of a curved-shaped groove and the longitudinal direction of the conductive base strip. The photovoltaic soldering strip increases an output power of a solar cell assembly by increasing the total reflection proportion. It also ensures soldering fastness by adjusting flat regions of the base strip. Effective cross section loss of the conductive base strip is reduced by adjusting the angle of each groove, so as to minimize the confluence efficiency loss of the soldering strip.

Abstract: To provide a solar cell having improved photoelectric conversion efficiency and a solar cell module. A solar cell (10) is provided with a photoelectric conversion portion (20), a light receiving surface electrode (21a) and a back surface electrode (21b). The light receiving surface electrode (21a) is arranged on the light receiving surface (20a) of the photoelectric conversion portion (20). The back surface electrode (21b) is arranged on the back surface (20b) of the photoelectric conversion portion (20). The back surface electrode (21b) includes metal film (21b1) and an electrical connection electrode (21b2). The metal film (21b1) at least partially covers the back surface (20b). The electrical connection electrode (21b2) is arranged on the metal film (21b1).

Abstract: Annealing solutions providing damage-free laser patterning utilizing auxiliary heating to anneal laser damaged ablation regions are provided herein. Ablation spots on an underlying semiconductor substrate are annealed during or after pulsed laser ablation patterning of overlying transparent passivation layers.

Abstract: Methods of forming colloidal nanocrystal (NC)-based thin film devicesare disclosed. The methods include the steps of depositing a dispersion of NCs on a substrate to form a NC thin-film, wherein at least a portion of the NCs is capped with chalcogenocyanate (xCN)-based ligands; and doping the NC thin-film with a metal.

Abstract: A method of manufacturing a photovoltaic structure includes forming a p-type semiconductor absorber layer containing a copper indium gallium selenide based material over a first electrode, forming a n-type cadmium sulfide layer over the p-type semiconductor absorber layer by sputtering in an ambient including hydrogen gas and oxygen gas, and forming a second electrode over the cadmium sulfide layer.

Abstract: Barrier infrared detectors configured to operate in the long-wave (LW) infrared regime are provided. The barrier infrared detector systems may be configured as pin, pbp, barrier and double heterostructrure infrared detectors incorporating optimized p-doped absorbers capable of taking advantage of high mobility (electron) minority carriers. The absorber may be a p-doped Ga-free InAs/InAsSb material. The p-doping may be accomplished by optimizing the Be doping levels used in the absorber material. The barrier infrared detectors may incorporate individual superlattice layers having narrower periodicity and optimization of Sb composition to achieve cutoff wavelengths of ˜10 ?m.

Abstract: The size-dependent band-gap tunability and solution processability of nanocrystals (NCs) make them attractive candidates for optoelectronic applications. One factor that presently limits the device performance of NC thin films is sub-bandgap states, also referred to as trap states. Trap states can be controlled by surface treatment of the nanocrystals.

Abstract: This application is related to a method of manufacturing a solar cell device comprising providing a substrate comprising Ge or GaAs; forming a first tunnel junction on the substrate, wherein the first tunnel junction comprises a first n-type layer comprising InGaP:Te, and a first alloy layer comprising AlxGa(1?x)As and having a lattice constant; adding a material into the first alloy layer to change the lattice constant; and forming a first p-n junction on the first tunnel junction.

Abstract: A semiconductor light-emitting device comprises an optical semiconductor multilayer disposed above a support substrate, which has a structure in which a first semiconductor layer having a first conductivity type, an active layer having light emitting properties, and a second semiconductor layer having a second conductivity type different from the first conductivity type are sequentially stacked from the support substrate side, in which a groove, which has a height exceeding at least the active layer from the support substrate side, is formed along an outer edge of the optical semiconductor multilayer, and which includes an external region being a region further outside than the groove, an inner region being a region further inside than the groove, and a connection region corresponding to a region where the groove is provided, in plan view.

Abstract: A semiconductor light-emitting element includes: a lower clad layer 12 that is provided on a substrate 10; an active layer 20 that is provided on the lower clad layer 12 and includes a quantum well layer 24 and a plurality of quantum dots 28 sandwiching a second barrier layer 22b together with the quantum well layer 24; and an upper clad layer 14 that is provided on the active layer 20, wherein a distance D between the quantum well layer 24 and the plurality of quantum dots 28 is smaller than an average of distances X between centers of the plurality of quantum dots 28.

Abstract: A light emitting device includes a p-side heterostructure having a short period superlattice (SPSL) formed of alternating layers of AlxhighGa1-xhighN doped with a p-type dopant and AlxlowGa1-xlowN doped with the p-type dopant, where xlow?xhigh?0.9. Each layer of the SPSL has a thickness of less than or equal to about six bi-layers of AlGaN.

Abstract: An object of the present invention is to provide a light-emitting device comprising: a substrate, a first light-emitting semiconductor stack having a first transverse width, the first light-emitting semiconductor stack comprising a first active layer emitting a first radiation of a first dominant wavelength during operation; a second light-emitting semiconductor stack having a second transverse width less than the first transverse width and comprising a second active layer emitting a second radiation of a second dominant wavelength shorter than the first dominant wavelength during operation; and a first conductive connecting structure between the first light-emitting semiconductor stack and the second light-emitting semiconductor stack, wherein the first conductive connecting structure is lattice-mismatched to the first active layer and to the second active layer, the first light-emitting semiconductor stack is between the substrate and the second light-emitting semiconductor stack.

Abstract: A semiconductor layer including a plurality of inhomogeneous regions is provided. Each inhomogeneous region has one or more attributes that differ from a material forming the semiconductor layer. The inhomogeneous regions can include one or more regions configured based on radiation having a target wavelength. These regions can include transparent and/or reflective regions. The inhomogeneous regions also can include one or more regions having a higher conductivity than a conductivity of the radiation-based regions, e.g., at least ten percent higher. In one embodiment, the semiconductor layer is used to form an optoelectronic device.

Abstract: Methods and structures for forming arrays of LED devices are disclosed. The LED devices in accordance with embodiments of the invention may include an internally confined current injection area to reduce non-radiative recombination due to edge effects. Several manners for confining current may include etch removal of a current distribution layer, etch removal of a current distribution layer and active layer followed by mesa re-growth, isolation by ion implant or diffusion, quantum well intermixing, and oxide isolation.

Abstract: Embodiments of the invention include a semiconductor light emitting device. The device includes a substrate having first surface and a second surface opposite the first surface. The device further includes a semiconductor structure disposed on the first surface of the substrate. A cavity is disposed within the substrate. The cavity extends from the second surface of the substrate. The cavity has a sloped side wall.

Abstract: A micro-light-emitting diode (micro-LED) device includes a first semiconductor layer, an active layer, and a second semiconductor layer. The first semiconductor layer includes a first bottom surface. The active layer is disposed on the first semiconductor layer. The second semiconductor layer disposed on the active layer includes a second bottom surface. A surface of the second semiconductor layer opposite to the active layer is a light-exiting surface of the micro-LED device. The second semiconductor layer has different thicknesses, in which a minimum thickness of the second semiconductor layer is located at an edge or at least one side of the second semiconductor layer. Vertical-projection zones of the first semiconductor layer, the active layer, and the second semiconductor layer on the first bottom surface are substantially the same.

Abstract: A method of making a semiconductor device comprising: providing a semiconductor wafer having a semiconductor layer (210); forming a first mask layer (220) over the semiconductor layer; forming a first metal layer (225) over the first mask layer; forming a second metal layer (230) over the first metal layer, the first metal layer having a lower melting point than the second metal layer; annealing the second metal layer to form islands (231); and etching through the first mask layer and the semiconductor layer using the islands as a mask to form an array of pillars.

Abstract: The present invention provides structures and methods that enable the construction of micro-LED chiplets formed on a sapphire substrate that can be micro-transfer printed. Such printed structures enable low-cost, high-performance arrays of electrically connected micro-LEDs useful, for example, in display systems. Furthermore, in an embodiment, the electrical contacts for printed LEDs are electrically interconnected in a single set of process steps. In certain embodiments, formation of the printable micro devices begins while the semiconductor structure remains on a substrate. After partially forming the printable micro devices, a handle substrate is attached to the system opposite the substrate such that the system is secured to the handle substrate. The substrate may then be removed and formation of the semiconductor structures is completed. Upon completion, the printable micro devices may be micro transfer printed to a destination substrate.

Abstract: A semiconductor light-emitting device includes a substrate, an LED chip, a control element, a conductive layer and an insulating layer. The substrate, made of a semiconductor material, has an obverse surface and a reverse surface spaced apart from each other in the thickness direction of the substrate. The control element controls light emission of the LED chip. The conductive layer is electrically connected to the LED chip and the control element. The insulating layer is arranged between at least apart of the conductive layer and the substrate. The substrate has a recess formed in the obverse surface, and the LED chip is housed in the recess. The control element is arranged between the LED chip and the reverse surface in the thickness direction of the substrate.

Abstract: A method of fabricating a semiconductor structure comprises forming a quantum dot. An insulator layer of silica is then formed encapsulating the quantum dot to create a coated quantum dot, using a reverse micelle sol-gel reaction. In one embodiment, the reverse micelle sol-gel reaction includes dissolving the quantum dot in a first non-polar solvent to form a first solution, adding the first solution to a second solution having a surfactant dissolved in a second non-polar solvent; and adding sodium silicate, potassium silicate, or lithium silicate to the second solution.

Abstract: A method for producing a ceramic conversion element and a light-emitting device are disclosed. In an embodiment the method includes providing at least four functional layers, each being a green body or a ceramic, wherein first functional layer is formed as a first luminous layer comprising an oxide and configured to at least partially convert light of a first wavelength range into light of a second wavelength range, wherein a second functional layer is formed as a second luminous layer comprising a nitride and configured to at least partially convert light of the first wavelength range into light of a third wavelength range, wherein a third functional layer is formed as a first intermediate layer, wherein the first intermediate layer comprises an oxide, wherein a fourth functional layer is formed as a second intermediate layer, and wherein the second intermediate layer comprises a nitride or an oxynitride.

Abstract: In one aspect a light emitting device includes a light emitting diode (LED) chip, and an encapsulant covering the LED chip. The encapsulant is embedded with a downconverter. The downconverter includes a quasi-two dimensional quantum nanoplatelet structure.

Abstract: A method for producing a semiconductor light-emitting device having a substrate, an element and an encapsulating material as constituent members, includes: a first step of providing the substrate with the element; a second step of potting un uncured encapsulating material onto the substrate to cover the element; and a third step of curing the potted encapsulating material in such a manner that all of the following formulae (1), (2) and (3) are satisfied when the absorbances which a cured encapsulating material having a thickness of t [nm] has at wavelengths of 380 nm, 316 nm and 260 nm are represented by AbsA(t), AbsB(t) and AbsC(t), respectively, and the light transmittance thereof at 380 nm is represented by T(t): (1) T(1.7)?90%; (2) AbsB(t)?AbsA(t)<0.011t; and (3) AbsC(t)?AbsA(t)<0.125t.

Abstract: A light emitting device includes a substrate having a first main surface that serves as the light extraction surface, a second main surface that is opposite the first main surface, and a mounting surface that is adjacent to at least the second main surface, and that is provided an insulating base material, a pair of connection terminals disposed on the second main surface, and a heat dissipation terminal disposed on the second main surface and between the pair of connection terminals; a light emitting element that is mounted on the first main surface of the substrate and; a sealing member that seals the light emitting element and is formed substantially in the same plane as the substrate on the mounting surface.

Abstract: The invention relates to an optoelectronic semiconductor component comprising an optoelectronic semiconductor chip. In particular, the optoelectronic semiconductor component is a radiation-emitting semiconductor component which is designed as a side emitter. The invention also relates to a method for producing an optoelectronic semiconductor component of said type.

Abstract: A light-emitting element includes: a light transmissive substrate having a first main surface, a second main surfaces, a first lateral surface, a second lateral surface, a third lateral surface, and a fourth lateral surface; a semiconductor layered body; a first light reflection member; and a second light reflection member. A cross-sectional plane of the light transmissive substrate perpendicular to the first main surface and intersecting with the third lateral surface and the fourth lateral surface has a first concave figure having a first recess. The deepest portion of the first recess is arranged on an inner side of an outer periphery of the semiconductor layered body. The third lateral surface includes one or more surfaces defining the first recess.

Abstract: A light emitting device having an enhanced surface property and an electrical property is provided. The light emitting device includes a light emitting structure including a first semiconductor layer, an active layer, and a second semiconductor layer, a first electrode disposed on one side of the light emitting structure and electrically connected to the first semiconductor layer, a second electrode disposed on one side of the light emitting structure and electrically connected to the second semiconductor layer, and an ohmic contact including a first layer disposed between the second electrode and the second semiconductor layer and having aluminum (Al), a second layer including at least one MxAly alloy formed by a reaction with Al included in the first layer, and a third layer disposed on the second layer and having gold (Au) is provided.

Abstract: An LED package structure includes a base, an LED chip disposed on the base, at least one metal wire, a phosphor sheet, and an encapsulation resin disposed in the base and encapsulating the LED chip, the metal wire, and the phosphor sheet. The LED chip has at least one electrode thereon. The metal wire has an apex and a loop height being defined by the apex. The metal wire is electrically connected to the electrode and the base. The phosphor sheet includes a B-stage resin and a plurality of phosphor powders mixed therewith. The phosphor sheet is adhered to the LED chip by the B-stage resin capable of viscosity and covers the top surface, the side surface, and the electrode of the LED chip. A thickness of the phosphor sheet is smaller than the loop height, and the apex of the metal wire is exposed from the phosphor sheet.