Abstract: The present invention provides a thin film transistor, a fabricating method thereof, an array substrate and a display device. The fabricating method of the thin film transistor of the present invention comprises: forming an inducing layer film and an oxide active layer film in contact therewith on a substrate, the oxide active layer film being provided above or below the inducing layer film; and heating the substrate subjected to the above step, crystallizing the oxide active layer film through inducement of the inducing layer film to form a crystalline oxide active layer.

Abstract: A circuit-on-wire (CoW) is provided that is made from a flexible metal wire with an outer surface, and a plurality of discrete electrical control devices formed in series along the metal wire outer surface. Each control device may have an electrical contact accessible through the metal wire. In one aspect, the control device may have a via through the metal wire from the top surface to the bottom surface with a second electrical contact accessible through the via. In addition, the control devices may have a top surface with an accessible third electrical contact. For example, the control device may be a first thin-film transistor (TFT), with a gate electrode accessible through the metal wire, wherein the second electrical contact is a first source/drain (S/D) electrode, and wherein the third electrical contact is a second S/D electrode. Using the above-described CoW, a woven active matrix array can be fabricated.

Abstract: A pixel structure, an array substrate and a display device. The pixel substrate comprises a first pixel electrode and a second pixel electrode arranged in a first direction, and a thin film transistor (TFT) disposed between the first pixel electrode and the second pixel electrode. The TFT includes a comb-shaped source, a comb-shaped first drain and a comb-shaped second drain; and a channel region of the TFT is defined by the comb-shaped source respectively and the comb-shaped first drain and the comb-shaped second drain. The channel region has a greater ratio of width to length, thus improving the driving capability of the TFT for driving the first pixel electrode and the second pixel electrode.

Abstract: To provide a semiconductor device including a planar transistor having an oxide semiconductor and a capacitor. In a semiconductor device, a transistor includes an oxide semiconductor film, a gate insulating film over the oxide semiconductor film, a gate electrode over the gate insulating film, a second insulating film over the gate electrode, a third insulating film over the second insulating film, and a source and a drain electrodes over the third insulating film; the source and the drain electrodes are electrically connected to the oxide semiconductor film; a capacitor includes a first and a second conductive films and the second insulating film; the first conductive film and the gate electrode are provided over the same surface; the second conductive film and the source and the drain electrodes are provided over the same surface; and the second insulating film is provided between the first and the second conductive films.

Abstract: An insulating film provided between adjacent pixels is referred to as a bank, a partition, a barrier, an embankment or the like, and is provided above a source wiring or a drain wiring for a thin film transistor, or a power supply line. In particular, at an intersection portion of these wirings provided in different layers, a larger step is formed there than in other portions. Even when the insulating film provided between adjacent pixels is formed by a coating method, thin portions are problematically partially formed due to this step and the withstand pressure is reduced. In the present invention, a dummy material is arranged near the large step portion, particularly, around the intersection portion of wirings, so as to alleviate unevenness formed thereover. The upper wiring and the lower wiring are arranged in a misaligned manner so as not to align the end portions.

Abstract: A display panel includes an active device array substrate, an opposite substrate, a display medium and a sealant. The active device array substrate includes a substrate, an active device array, a passivation layer and an enhancement layer. A material of the enhancement layer is different from a material of the passivation layer. The opposite substrate is disposed opposite to the active device array substrate. The display medium is disposed between the active device array substrate and the opposite substrate. The sealant is disposed between the active device array substrate and the opposite substrate and surrounds the display medium. An end of the sealant directly contacts the enhancement layer, and a material of the enhancement layer is the same as a material of the sealant.

Abstract: To provide a semiconductor device including a capacitor whose charge capacity is increased without reducing the aperture ratio. The semiconductor device includes a transistor including a light-transmitting semiconductor film, a capacitor where a dielectric film is provided between a pair of electrodes, an insulating film provided over the light-transmitting semiconductor film, and a light-transmitting conductive film provided over the insulating film. In the capacitor, a metal oxide film containing at least indium (In) or zinc (Zn) and formed on the same surface as the light-transmitting semiconductor film in the transistor serves as one electrode, the light-transmitting conductive film serves as the other electrode, and the insulating film provided over the light-transmitting semiconductor film serves as the dielectric film.

Abstract: The present disclosure provides a display substrate, a method for manufacturing the display substrate, and a display device. An intermediate layer is formed on an organic base plate, a thermal expansion coefficient of the intermediate layer is smaller than that of the organic base plate and greater than that of an inorganic thin film, and the inorganic thin film is formed on the intermediate layer.

Abstract: Provided is a manufacturing method for an active matrix substrate, capable of providing a hole for alignment at an interlayer dielectric film without possible etching of a substrate surface and abnormal electric discharge and of allowing the position of a formed film to be easily corrected to be aligned with the position of the film of the lowest layer, with high overlaying precision. Also provided are the active matrix substrate and a display apparatus comprising the active matrix substrate. An interlayer dielectric film 14 of the active matrix substrate is formed using an SOG material with photosensitivity, and an adjustment hole 14b for adjustment of the patterns of a gate insulation film 15, a first semiconductor film 16, a second semiconductor film 17 and a source metal that are formed on the upper side of a substrate 10 and the interlayer dielectric film 14 is formed. The position of each film is adjusted while viewing an edge of the gate wiring 11 through the adjustment hole 14b.

Abstract: A manufacturing method and apparatus of low temperature polycrystalline silicon, and a polycrystalline silicon are provided. The manufacturing method of low temperature polycrystalline silicon includes forming an amorphous silicon layer on a substrate; scanning the amorphous silicon layer by using a laser to emit a strip-shaped laser beam to go through a mask which includes transmissive stripes and partially-transmissive stripes arranged alternately, to form low temperature fusion regions and high temperature fusion regions which are arranged alternately on the amorphous silicon layer; recrystallizing the amorphous silicon layer from the low temperature fusion regions to the high temperature fusion regions.

Abstract: Various embodiments provide a thin film transistor (TFT) device, a manufacturing method of the TFT device, and a display apparatus including the TFT device. An etch stop layer (ESL) material is formed on an active layer on a substrate. An electrical conductive layer material is formed on the ESL material for forming a source electrode and a drain electrode. The electrical conductive layer material is patterned to form a first portion of the source electrode containing a first via-hole through the source electrode, and to form a first portion of the drain electrode containing a second via-hole through the drain electrode. The ESL material is patterned to form an etch stop layer (ESL) pattern including a first ESL via-hole connecting to the first via-hole through the source electrode and including a second ESL via-hole connecting to the second via-hole through the drain electrode.

Abstract: A method of manufacturing an array substrate is disclosed. A first conductive pattern, a first insulating layer, a second conductive pattern, and a second insulating layer on a base substrate is successively formed. The second insulating layer and the first insulating layer are patterned with a double-tone mask. At least a half lap joint via hole in the second insulating layer, and at least a full lap joint via hole in both the first insulating layer and the second insulating layer is formed. The second conductive pattern corresponds to a part of the half lap joint via hole, and the first conductive pattern corresponds to the whole of the full lap joint via hole. A third conductivity pattern is formed on the surface of the second conductivity pattern and the first insulating layer and a fourth conductive pattern is formed on the surface of the first conductive pattern.

Abstract: There is provided a photodetector, comprising a semiconductor heterostructure having in sequence: a first collection layer having substantially uniform doping of a first doping type; a radiation-absorbing layer having substantially uniform doping of the first doping type and having a band gap less than or equal to that of the first collection layer; and a barrier layer having a band gap greater than that of the radiation-absorbing layer, the top of the valence band of the barrier layer being substantially equal in energy to that of the radiation-absorbing layer where the first doping type is n-type or the bottom of the conduction band of the barrier layer being substantially equal in energy to that of the radiation-absorbing layer where the first doping type is p-type; wherein a first portion of the barrier layer is of the first doping type and a second portion of the barrier layer is of a second doping type, the first portion of the barrier layer being adjacent to the radiation-absorbing layer, forming a het

Abstract: An image sensor includes: a first inter-layer dielectric layer formed over a front side of a substrate including photoelectric conversion regions; isolation structures each of which penetrates through the first inter-layer dielectric layer and has a portion buried in the substrate; first metal lines formed over the first inter-layer dielectric layer to correspond to the photoelectric conversion regions; and an optical filter and a light condenser formed over a back side of the substrate.

Abstract: A photoelectric conversion element includes a first electrode, a second electrode, a first layer, and a second layer. The first layer is provided between the first electrode and the second electrode. The second layer is provided between the first layer and the second electrode. The first layer contains selenium. The second layer contains In, Ga, Zn, and O. The second layer may contain an In—Ga—Zn oxide. The selenium may be crystalline selenium. The first layer functions as a photoelectric conversion layer. The second layer functions as a hole injection blocking layer. The In—Ga—Zn oxide may have a c-axis aligned crystal.

Abstract: A solid-state imaging device includes a layout in which one sharing unit includes an array of photodiodes of 2 pixels by 4×n pixels (where, n is a positive integer), respectively, in horizontal and vertical directions.

Abstract: A semiconductor device includes a carrier substrate, a first color filter, a first photodetector, and a light enhancement structure. The first photodetector is disposed between the carrier substrate and the first color filter. The light enhancement structure is disposed between the first color filter and the carrier substrate and adjacent to the first photodetector for enhancing intensity of light incident the first photodetector.

Abstract: A light-receiving device which has high reliability and high sensitivity is provided with low cost. The device has a laminate type device structure in which a photoelectric converter and a scanning circuit unit are connected by microbumps, and a structure in which a transparent conductive film is formed on a photodiode of a photoelectric converter. A rewiring is formed so as to have a function of an OB region, and an electrode for supplying a voltage to a scanning circuit and the photodiode on the transparent conductive film, and the rewiring is electrically connected to an external electrode by a wire.

Abstract: A back side image sensor and method of manufacture are provided. In an embodiment a bottom anti-reflective coating is formed over a substrate, and a metal shield layer is formed over the bottom anti-reflective coating. The metal shield layer is patterned to form a grid pattern over a sensor array region of the substrate, and a first dielectric layer and a second dielectric layer are formed to at least partially fill in openings within the grid pattern.

Abstract: There is provided a receiver optical module including a photodetector having a plurality of channels, a capacitor disposing block formed on an upper portion of the photodetector, a plurality of capacitors formed on the capacitor disposing block, and an electrical wiring configured to connect the plurality of capacitors to electrodes of a plurality of channels of the photodetector, wherein the plurality of capacitors are formed on the capacitor disposing block such that distance between the capacitors and the electrodes of the corresponding channels are the same. Distortion and loss of signal characteristics of high frequency can be reduced and quality of a signal can be enhanced.

Abstract: A solid-state imaging device has a first area in which a plurality of pixels are provided, a second area provided on an outer side with respect to the first area, and a third area provided on the outer side with respect to the second area. An inner-lens layer provided over the first to third areas has an opening. An insulating film provided below the inner-lens layer also has an opening.

Abstract: A package assembly includes a package body and a focal plane array (FPA) within the package body. The FPA includes a read out integrated circuit (ROIC) having a circuit side. A photodiode array (PDA) defines an optical axis and has a backside electrically connected to the circuit side of the ROIC. A plurality of conductive through-vias extend from the circuit side of the ROIC through to input/output (I/O) bondpads on the backside of the ROIC. A window is operatively connected between the FPA and the package body.

Abstract: The present disclosure relates to a solid-state imaging device that can reduce crosstalk interference, and to an electronic apparatus. In the upper chip, VSLs, VSLs, and control lines are stacked in this order from the bottom. That is, in the stacked solid-state imaging device, the control lines are laid out in the uppermost layer of the upper chip. In this structure, the influence of a lower chip on the two sets of VSLs can be shielded by the control lines. The present disclosure can be applied to CMOS solid-state imaging devices to be used in electronic apparatuses, such as a camera apparatus.

Abstract: The present technology relates to a solid-state imaging device, manufacturing method of a solid-state imaging device, and an electronic device, which can provide a solid-state imaging device having further improved features such as reduced optical color mixing and the like. Also, an electronic device using the solid-state imaging device thereof is provided. According to a solid-state imaging device having a substrate and multiple photoelectric converters that are formed on the substrate, an insulating film forms an embedded element separating unit. The element separating unit is configured of an insulating film having a fixed charge that is formed so as to coat the inner wall face of a groove portion, within the groove portion which is formed in the depth direction from the light input side of the substrate.

Abstract: The present disclosure provides an X-ray flat panel detector including: a base substrate; thin film transistors (TFTs), a pixel electrode layer, photodiodes, a transparent electrode layer, and an X-ray conversion layer which are arranged on the base substrate; and an electric field application portion configured to generate an electric field, wherein the photodiodes are arranged in the electric field, and a moving direction of negative charges when visible light rays are converted to electrical signals by the photodiodes is substantially same as a direction of the electric field. In this detector, it is applied a direction of the electric field which is substantially same as the moving direction of negative charges in the photodiode, so that movement of holes and electrons of the photodiode may be accelerated under an influence of the electric field, and thus the electrical signal may promptly arrive at the pixel electrode.

Abstract: The present disclosure provides a display substrate, its manufacturing method, and a display device. The method includes a step of forming a plurality of TFTs. The method further includes steps of: forming a lattice matching layer on a substrate so as to deposit AlN thereon; depositing an AlN layer on the lattice matching layer by low-temperature pulse magnetron sputtering; and forming on the AlN layer GaN LEDs each including an n-type GaN layer, a multilayered quantum well structure and a p-type GaN layer and corresponding to one of the TFTs.

Abstract: Embodiments of the technology implement DIOMEJ cells. In one embodiment, a DIOMEJ cell includes: an MEJ that includes, a ferromagnetic fixed layer, a ferromagnetic free layer, and a dielectric layer interposed between said fixed and free layers, where the fixed layer is magnetically polarized in a first direction, where the free layer has a first easy axis that is aligned with the first direction, and where the MEJ is configured such that when a potential difference is applied across it, the magnetic anisotropy of the free layer is altered such that the relative strength of the magnetic anisotropy along a second easy axis that is orthogonal to the first easy axis, as compared to the strength of the magnetic anisotropy along the first easy axis, is magnified for the duration of the application of the potential difference; and a diode, where the diode and the MEJ are arranged in series.

Abstract: A semiconductor integrated circuit device having a vertical channel and a method of manufacturing the same are provided. A plurality of active lines are formed in a semiconductor substrate. A gate electrode having a lower height than each active line is formed on a sidewall of the active line. A first insulating layer having a height lower than that of the active line and higher than that of the gate electrode is buried between active lines, and a silicide layer is formed on an exposed upper surface and a lateral surface of the active line.

Abstract: A method for producing a semiconductor device includes forming a fin-shaped semiconductor layer on a semiconductor substrate and a first pillar-shaped semiconductor layer, a first dummy gate layer and a second pillar-shaped semiconductor layer, and a second dummy gate layer. Third and fourth dummy gate layers are formed on sidewalls of the first dummy layer gate, the first pillar-shaped semiconductor layer, the second dummy gate layer and the second pillar-shaped semiconductor layer. An interlayer insulating film is deposited, the dummy gate layers are removed, and a gate insulator is formed film around the first and second pillar-shaped semiconductor layers. A first metal is deposited and a gate electrode and a gate line are formed around the first pillar-shaped semiconductor layer. Second and third metals are deposited and a first contact and a pillar-shaped resistance-changing layer, a lower electrode, and a reset gate are formed.

Abstract: A switch device includes: a first electrode; a second electrode disposed to oppose the first electrode; a switch layer provided between the first electrode and the second electrode, and including at least one or more kinds of chalcogen elements and one or more kinds of first elements out of the one or more kinds of chalcogen elements, the one or more kinds of first elements, and a second element including one or both of oxygen (O) and nitrogen (N), the one or more kinds of chalcogen elements being selected from tellurium (Te), selenium (Se), and sulfur (S), and the one or more kinds of first elements being selected from boron (B), carbon (C), and silicon (Si).

Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes an OLED comprising a plurality of pixels configured to emit different colors of light and an encapsulation layer formed over the OLED. The OLED display also includes a color filter layer formed over the encapsulation layer, wherein the color filter layer comprises a plurality of color filters formed on regions corresponding to the pixels and a plurality of light block units respectively formed at least between the color filters. The OLED display further includes an edge lens unit formed over a lower surface of the color filter layer and formed between a lower surface of each of the color filters and a lower surface of each of the light block units.

Abstract: The thickness of a display device including a touch sensor is reduced. Alternatively, the thickness of a display device having high display quality is reduced. Alternatively, a method for manufacturing a display device with high mass productivity is provided. Alternatively, a display device having high reliability is provided. Stacked substrates in each of which a sufficiently thin substrate and a relatively thick support substrate are stacked are used as substrates. One surface of the thin substrate of one of the stacked substrates is provided with a layer including a touch sensor, and one surface of the thin substrate of the other stacked substrate is provided with a layer including a display element. After the two stacked substrates are attached to each other so that the touch sensor and the display element face each other, the support substrate and the thin substrate of each stacked substrate are separated from each other.

Abstract: An organic light emitting diode display includes: a first organic light emitting element configured to emit light having a first wavelength; and a second organic light emitting element configured to emit light having a second wavelength substantially shorter than the first wavelength. The first organic light emitting element includes a first electrode, and the second organic light emitting element includes a second electrode having substantially higher reflectance for the light having the second wavelength than the first electrode.

Abstract: An organic light emitting display panel and associated methods, the panel including a substrate; an organic light emitting diode (OLED) on the substrate; and an encapsulation member to separate the OLED from an external environment, wherein the OLED includes a first electrode on the substrate; a pixel defining layer exposing the first electrode and including a flat planar surface and an inclined planar surface extending from the flat planar surface such that the inclined planar surface overlaps an edge of the first electrode; an organic layer, the organic layer including a first region on the first electrode and a second region on the inclined planar surface; and a second electrode on the organic layer, and wherein, in the second region, a thickness of the organic layer is decreased along a direction extending away from the first region.

Abstract: A display apparatus manufacturing method, including: forming a first electrode layer over a substrate; forming a planarization film over the first electrode layer; forming a contact hole in the planarization film; forming a second electrode layer over the planarization film and the contact hole; forming a light-emitting layer over the second electrode layer; forming an upper electrode layer over the light-emitting layer; and irradiating a part of the first electrode layer in a pixel with laser light from a substrate side, so as to connect the part of the first electrode layer to the second electrode layer, the pixel being a pixel having the first electrode and the second electrode which are not in contact with each other in the contact hole, the part being at a position other than in the contact hole.

Abstract: An organic light emitting diode (OLED) display includes a light-emitting region including an organic emission layer and a non-light-emitting region neighboring the light-emitting region. The OLED display includes a first electrode positioned at the light-emitting region and including a plurality of division regions divided according to a virtual cutting line crossing the light-emitting region, an organic emission layer positioned on the first electrode, a second electrode positioned on the organic emission layer, a driving thin film transistor connected to the first electrode, and a plurality of input terminals positioned at the non-light-emitting region and respectively connecting between each of division regions and the driving thin film transistor.

Abstract: The present invention provides an AMOLED backplane structure and a manufacturing method thereof. In each sub-pixel, a TFT substrate (TS) includes a corrugation structure (4) formed in an area corresponding to an opening (71) of a pixel definition layer (7). The corrugation structure (4) includes a plurality of raised sections (41) and a recessed section (42) formed between every two adjacent ones of the raised sections (41). An upper surface of a portion of the planarization layer (5) and a portion of a pixel electrode (6) that correspond to and are located above the corrugation structure (4) include curved surfaces corresponding to the corrugation structure (4). The AMOLED backplane structure helps ensure the planarization layer (5) is smooth and free of abrupt change sites and also makes the pixel electrode (6) in a form of a curved surface to increase an effective displaying surface, extend the lifespan of the OLED, reduce difficulty of manufacturing, and improve resolution.

Abstract: A TFT substrate has a thin-film transistor including an oxide semiconductor layer, a source electrode, and a drain electrode, and includes: a first wiring line formed in a positionally-higher layer than that of the source electrode and the drain electrode, and connected to at least the source electrode or the drain electrode; and a terminal formed in a higher layer than that of the first wiring line, and connected to the first wiring line. The source electrode or the drain electrode connected to the first wiring line contains copper. The first wiring line is a multilayer film having a first film (transparent conductive film), a second film (copper film), and a third film (copper-manganese alloy film) laminated in this order from the bottom. The terminal comprises an aluminum alloy.

Abstract: An on-chip magnetic structure structure includes a magnetic material comprising cobalt in a range from about 80 to about 90 atomic % (at. %) based on the total number of atoms of the magnetic material, tungsten in a range from about 4 to about 9 at. % based on the total number of atoms of the magnetic material, phosphorous in a range from about 7 to about 15 at. % based on the total number of atoms of the magnetic material, and palladium substantially dispersed throughout the magnetic material.

Abstract: A semiconductor device is improved in reliability and productivity. In the formation of its Ti/TiN stacked film, about a mixed gas of Ar gas and N2 gas that is used to form a TiN film by a sputtering method, the supply of the N2 gas is turned off (i.e., is stopped) before that of the Ar gas.

Abstract: A device includes a source region, a drain region, and a wurtzite semiconductor between the source region and the drain region. A source-drain direction is parallel to a [01-10] direction or a [?2110] direction of the wurtzite semiconductor. The device further includes a gate dielectric over the wurtzite semiconductor, and a gate electrode over the gate dielectric.

Abstract: An IGBT includes an emitter electrode, base regions, an emitter region, a collector region, a collector electrode, a gate insulating film provided in contact with the silicon carbide semiconductor region, the emitter region, and the base region, and a gate electrode that faces the gate insulating film. A FWD includes a base contact region provided adjacent to the emitter region and electrically connected to the emitter electrode, and a cathode region disposed in the upper layer part on the other main surface side of the silicon carbide semiconductor region, provided adjacent to the collector region, and electrically connected to the collector electrode. The IGBT further includes a reduced carrier-trap region disposed in a principal current-carrying region of the silicon carbide semiconductor region located above the collector region and having a smaller number of carrier traps than the silicon carbide semiconductor region located above the cathode region.

Abstract: A silicon carbide semiconductor device includes: a drift layer of a first conductivity type made of silicon carbide; a well region of a second conductivity type formed on the drift layer; a source region of a first conductivity type formed on the well region; a gate insulating film formed on an inner wall of a trench extending from a front surface of the source region through the well region, at least a part of a side surface of the gate insulating film being in contact with the drift layer; a gate electrode formed in the trench with the gate insulating film therebetween; a protective layer of the second conductivity type formed in the drift layer; and a depletion suppressing layer of the first conductivity type formed in the drift layer so as to be in contact with a side surface of the protective layer.

Abstract: A silicon carbide semiconductor device capable of achieving a decrease in ON resistance and an increase in breakdown voltage and a method for manufacturing a silicon carbide semiconductor device. A silicon carbide semiconductor device includes a silicon carbide substrate and a drift layer. The drift layer includes a breakdown voltage holding layer extending from a point where a doping concentration has a predetermined value to a surface of the drift layer. The doping concentration in the breakdown voltage holding layer continuously decreases from the point where the doping concentration has the predetermined value to a modulation point located further toward the surface of the drift layer than a midpoint in a film thickness direction of the breakdown voltage holding layer. The doping concentration in the breakdown voltage holding layer continuously increases from the modulation point to the surface of the drift layer.

Abstract: The present examples relate to a power semiconductor device. The present examples also relate to a power semiconductor device that maintains a breakdown voltage and reduces a gate capacitance through improving the structure of an Injection Enhanced Gate Transistor (IEGT), and thereby reduces strength of an electric field compared to alternative technologies. Accordingly, the present examples provide a power semiconductor device with a small energy consumption and with an improved switching functionality.

Abstract: A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor substrate and a p-doped layer formed on the substrate having a dislocation density exceeding 108 cm?2. An n-type layer is formed on or in the p-doped layer. The n-type layer includes a II-VI material configured to tolerate the dislocation density to form an electronic device with reduced leakage current over a device with a III-V n-type layer.

Abstract: A semiconductor wafer processing system for processing a semiconductor wafer is presented.

Abstract: A method for forming a non-volatile memory cell is provided. The method comprises: forming a field region with a first impurity type in a semiconductor substrate, the field region having a first impurity concentration; forming a plurality of spaced apart higher concentration regions with the first impurity type within the field region, the higher concentration regions each having a higher concentration than the first impurity concentration; and forming a plurality of floating gate transistors in the field region between the higher concentration regions.

Abstract: An apparatus comprises a first semiconductor fin, a second semiconductor fin and a third semiconductor fin over a substrate, wherein the first semiconductor fin and the second semiconductor fin are separated by a first isolation region and the second semiconductor fin and the third semiconductor fin are separated by a second isolation region, and wherein a width of the first isolation region is greater than a width of the second isolation region.