Abstract: A tuning fork type piezoelectric vibration piece 2 includes a base portion 25 in which a piezoelectric vibration substrate has a connection area with an external element, and a pair of leg portions 21, 22 projecting from a first end face of the base portion. The pair of leg portions has vibrating portions 212, 222 equipped with drive electrodes, wide weight portions 211, 221 formed at tip ends of the vibrating portions, and connecting portions 213, 223 between the vibrating portions and the weight portions. The connecting portions have widening sections whose width increases exponentially from the vibrating portions to the weight portions. The length of the widening sections is greater than their width. The weight portions have constant-width parts whose width is fixed from their connecting positions with the connecting portions. The weight portions are free of drive electrodes.

Abstract: A resonant member of a MEMS resonator oscillates in a mechanical resonance mode that produces non-uniform regional stresses such that a first level of mechanical stress in a first region of the resonant member is higher than a second level of mechanical stress in a second region of the resonant member. A plurality of openings within a surface of the resonant member are disposed more densely within the first region than the second region and at least partly filled with a compensating material that reduces temperature dependence of the resonant frequency corresponding to the mechanical resonance mode.

Abstract: The floating immittance emulator is presented in four embodiments in which four new topologies for emulating floating immittance functions are detailed. Each circuit uses three current-feedback operational-amplifiers (CFOAs) and three passive elements. The present topologies can emulate lossless and lossy floating inductances; capacitance, resistance, and inductance multipliers; and frequency-dependent positive and negative resistances.

Abstract: Apparatus and methods for reducing glitches in digital step attenuators are disclosed. By configuring a multi-bit DSA such that an attenuation control block changes a plurality of control signals in a manner sequencing individual switches of the DSA, glitches can be reduced and RF signal behavior can be enhanced. The sequence, based upon a unit time delay, causes the transient attenuation value to be bounded between a minimum and maximum and can improve settling time.

Abstract: One or more resistors or resistances are integrated in a 7-bit DVR or PVCOM integrated circuit. A 7-bit DVR or PVCOM integrated circuit includes a 7-bit DAC. The integrated resistors or resistances (R1, R2, or RSET, or any combination) reduces the number of external components, reduces the number of pins, and increases the accuracy of the DVR or PVCOM circuit. The least significant bit (LSB) of the DAC depends only on ratios of internal resistors, which can be made very accurate and independent of temperature.

Abstract: A clock generation device generates a clock signal which has a predetermined number of clocks for each predetermined time in such a way that a clock signal (32.768 kHz+? (? is zero or a positive number)) is input and some clocks of the clock signal are masked.

Abstract: Systems and methods for frequency specific closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a frequency specific predetermined value of a dynamic operating indicator of the integrated circuit at the desired specific operating frequency. The predetermined value is stored in a data structure within a computer usable media. The data structure comprises a plurality of frequency specific predetermined values for a variety of operating frequencies. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the measured behavior of the integrated circuit.

Abstract: A driver integrated circuit (IC) device. The driver device can include a front-end module, a pre-driver module, and a driver module coupled to a transmission line path. The pre-driver module can be coupled to the front-end module and can include one or more delay adjust capacitor modules, and one or more pull-down control modules. The driver module can be coupled to the pre-driver module, the driver module including one or more pull-down control logic modules. This driver device can configured in several implementations to provide control and programmability of a driver slew rate to maximize a signal integrity eye opening.

Abstract: An oscillator circuit includes: a plurality of delay elements, a first delay element configured to receive a first oscillator signal outputted from a second delay element in one stage before the first delay element and a second oscillator signal outputted from a third delay element in two or more stages before the first delay element, the plurality of delay terminals being connected in a ring by at least three or more delay elements, and the first oscillator signal and the second oscillator signal having phases different from one another; and a bias voltage generator configured to change a ratio of a first input bias current for the first oscillator signal to a second input bias current for the second oscillator signal, in accordance with a first bias voltage and a second bias voltage supplied to the plurality of delay elements.

Abstract: A time signal generating circuit and a time signal generating method are provided. The time signal generating method includes following steps: receiving a feedback voltage and a reference voltage to provide a first control signal, wherein the feedback voltage is related to an output voltage of a power converter; receiving an input voltage and a default voltage to provide a second control signal; and adjusting an on-time of a pulse width modulation signal according to the first control signal and the second control signal.

Abstract: A switching circuit includes a driver circuit DRV2 that outputs voltage for turning on and off a first transistor switch M2, positioned at a low potential side with respect to a load, among a plurality of transistor switches disposed in series between an input voltage and a ground; and a control circuit that causes the driver circuit DRV2 to output a first voltage that turns the first transistor switch M2 on upon an output voltage of the driver circuit DRV2 rising while the first transistor switch M2 is off and to cause the driver circuit DRV2 to suspend output of the first voltage upon the output voltage of the driver circuit DRV2 dropping after the driver circuit DRV2 outputs the first voltage.

Abstract: In order to increase the switching speed of an RF FET in an RF shunt circuit, a second, smaller, FET, with respect to the size of the RF FET, is connected directly to the gate of the RF FET to shunt the gate to ground quickly when switched from the off-state to the on-state. The smaller FET switches faster, due to being smaller than the larger RF FET, but it is effectively open-circuited in terms of RF performance when off because it is so small.

Abstract: A HEMT cell includes two or more gallium nitride (“GaN”) high-electron-mobility transistor (“HEMT”) devices electrically connected in series with each other. The HEMT cell includes a HEMT cell drain, a HEMT cell source, and a HEMT cell gate. The HEMT cell drain connects with the drain of a first GaN HEMT device in the series. The HEMT cell source connects with the source of a last GaN HEMT device in the series. The HEMT cell gate connects to a first two-dimensional electron gas (“2DEG”) gate bias resistor that connects with the gate of the first GaN HEMT device. The HEMT cell gate connects to a second 2DEG gate bias resistor that connects with the gate of the second GaN HEMT device. The first and second 2DEG gate bias resistors are located in a 2DEG layer of the HEMT cell. A multi-throw RF switch is also disclosed.

Abstract: A self-powered gate drive circuit comprising a first capacitor electrically coupled to a power semiconductor collector node of the circuit; a first switch arranged between the first capacitor and a second capacitor, the first switch electrically coupling the first and second capacitors when switched on; the second capacitor; a first diode, the first diode anode electrically coupled to the first capacitor and the first diode cathode electrically coupled to the first switch; a second diode, the second diode cathode electrically coupled to the first capacitor and the second diode anode electrically coupled with a ground node of the circuit; and a second switch, wherein the second switch electrically couples the second capacitor with a power semiconductor gate node when switched on.

Abstract: A proximity switch assembly and method for detecting activation of a proximity switch assembly is provided. The assembly includes a plurality of proximity switches each having a proximity sensor providing a sense activation field. A first proximity sensor generates a first activation field and comprises first and second electrodes having first fingers interdigitated with second fingers. A second proximity sensor generates a second activation field and comprises third and fourth electrode fingers having third fingers interdigitated with fourth fingers. The first and second electrodes are interleaved with the third and fourth electrodes.

Abstract: Embodiments are generally directed to smart impedance matching for high-speed I/O. In some embodiments, a circuit includes an impedance sensing block; a finite state machine to provide impedance tuning for a driver; and a control block, the control block to provide a feedback loop to check and tune impedance of the driver. The impedance sensing block is to sample an output voltage of the driver to determine whether the impedance of the driver is greater than or less than an impedance of the channel; and the finite state machine is to produce a signal to decrease or increase the impedance of the driver based on the determination whether the impedance of the driver is greater than or less than the impedance of the channel.

Abstract: Various embodiments of the invention allow to effectively reduce device and system power consumption in both active and inactive modes without compromising performance, without large area overhead, and at low cost. In certain embodiments, the reduction of power consumption is accomplished by combining circuit control techniques with power gating methods to reduce power loss due to leakage current.

Abstract: Technology is described for a relative timed clock gated cell. In one example, the relative timed clock gated cell includes a trigger latch and a data clock latch. The trigger latch includes a clock input coupled to a trigger line for transmitting a trigger signal. The trigger latch is configured to generate a data clock signal on an output. The trigger signal is based on a clock signal. The data clock latch includes a clock input coupled to the output of the trigger latch that latches a data input of the data clock latch based on the data clock signal. Various other computing circuitries and methods are also disclosed.

Abstract: A method for manufacturing a digital circuit is described including forming a plurality of field effect transistor pairs, connecting the field effect transistors of the field effect transistor pairs such that in response to a first transition from a first state of two nodes of the digital circuit and in response to a second transition from a second state of the nodes of the digital circuit the nodes each have an undefined logic state when, for each field effect transistor pair, the threshold voltages of the field effect transistors of the field effect transistor pair are equal and setting the threshold voltages of the field effect transistors of the field effect transistor pairs such that the nodes each have a predetermined defined logic state in response to the first transition and in response to the second transition.

Abstract: In accordance with some embodiments, an electrostatic discharge (ESD) protection circuit for high-voltage power rails includes an RC-triggered clamp having an RC-circuit having a resistor coupled between a first node and a second node, and a capacitor coupled between the second node and a third node. The RC-triggered clamp also has a transistor with a first source/drain, a gate, and a second source/drain, wherein the first source/drain is coupled to the first node, and the second source/drain is coupled to the third node. The RC-triggered clamp also has an inverter, wherein an input of the inverter is coupled to the second node, and an output of the inverter is coupled to the gate of the transistor. The ESD protection circuit also includes one or more forward-biased diodes coupled in series between a supply node and the first node.

Abstract: Disclosed is a cascode configuration that moves the gate of the cascode substantially without delay relative to an output node by capacitively coupling the latter onto the cascode gates. The passive coupling eliminates the need for actively driving the gates of the cascode. In some embodiments, the only circuitry needed on the cascode gate may be a biasing circuit that limits the swing on the cascode gate between Vmax and 2×Vmax, where Vmax is a transistor device rating.

Abstract: A method of configuring an integrated circuit device to perform a function includes storing a plurality of configurations for performing the function, each of the configurations being designed for a different characteristic of a particular input to the function. Inputs are received for the function, including the particular input. The characteristic of the particular input as received is examined, and one of the plurality of configurations is instantiated based on that characteristic of the particular input as received. A machine-readable data storage medium may be encoded with instructions to perform the method. A programmable device may be configured according to the method, and also may be incorporated into a heterogeneous system.

Abstract: A device that includes a memristive Akers logic array, wherein the memristive Akers logic array comprises multiple primitive logic cells that are coupled to each other; wherein each primitive logic cell comprises at least one memristive device.

Abstract: An on-chip Josephson parametric converter is provided. The on-chip Josephson parametric converter includes a Josephson ring modulator. The on-chip Josephson parametric converter further includes a lossless power divider, coupled to the Josephson ring modulator, having a single input port and two output ports for receiving a pump drive signal via the single input port, splitting the pump drive signal symmetrically into two signals that are equal in amplitude and phase, and outputting each of the two signals from a respective one of the two output ports. The pump drive signal excites a common mode of the on-chip Josephson parametric converter.

Abstract: An IC that performs integer and fractional divisions is disclosed. The IC comprises a plurality of shift registers that forms a shift register ring. Consecutive shift registers are coupled to each other through a multiplexer. The IC also includes a multiplexer controller that determines the shift registers to be activated within the shift register ring. The multiplexer controller determines the activation based upon a divisional factor. The IC also includes a pattern controller that generates the control signal to program the shift register.

Abstract: In some examples, compensating for hysteretic characteristics of a crystal oscillator in a timing circuit includes obtaining a plurality of successive temperature measurements. From the plurality of successive temperature measurements, a temperature gradient having a sign and a magnitude can be determined. A frequency compensation parameter can then be determined based on any combination of two or more factors chosen from a set of factors including a temperature measurement, the sign of the temperature gradient, and the magnitude of the temperature gradient. A frequency error of the timing circuit can then be compensated based on the frequency compensation parameter.

Abstract: A phase-detector circuit is disclosed. The phase-detector circuit comprises a plurality of phase comparators which detects a phase difference between receipt data and a clock signal of a plurality of clock signals having the same frequency and phase difference of a predetermined angle with each other, and generates and outputs signals for up/down signals for synchronizing a phase. The phase comparator generates and outputs a signal for the up/down signals having a pulse width including a detected phase-time difference and a predetermined delay time.

Abstract: A phase locked loop system comprises a phase locked loop and an oscillator that is coarse tuned and fine tuned according to coarse tuning operations and fine tuning operations. The system operates to calibrate the coarse tuning of the oscillator based on one or more characteristics related to the oscillator and determined by a characterization component, an interpolation function and one or more final measurements. An adjustment component is configured to adjust the coarse tuning value based on at least one final frequency measurement to generate a final coarse tuning value and set the coarse tuning of the oscillator based on the final coarse tuning value.

Abstract: A glitch-free digitally controlled oscillator (DCO) code update may be achieved by synchronizing the transfer of the DCO code update to a logic state transition of a pulse in the DCO clock output signal such that the code update may be achieved while the DCO delay chain remains in the same logic state. A state machine may provide the DCO code update and a pulsed update signal to a timing circuit. The DCO code update may be aligned with a pulse in the pulsed update signal. The timing circuit may generate a DCO code update enabled signal upon alignment of the pulse in the pulsed update signal with a state transition of a pulse in the pulsed DCO clock output. The DCO code update enabled signal may be aligned with a state transition in the pulsed DCO clock output to permit a glitch-free DCO code update.

Abstract: A PLL control system is provided that implements a phase tracer module to reduce lock time and output clock jitter. A second clock signal is generated by dividing a frequency of a reference clock signal. A feedback clock signal is generated based on a high-frequency clock signal from a digitally controlled oscillator (DCO) and a PLL feedback divide number. Lead/lag determination circuitry generates a lead/lag detection result that indicates whether the feedback clock signal leads or lags the second clock signal. A skew digitizer digitizes a skew between a falling edge of the second clock signal and a rising edge of the feedback clock signal to generate a skew signal. The phase tracer module processes the lead/lag detection result and the skew signal to generate a digital control signal that controls cycle time of the DCO to change frequency of the high-frequency clock signal.

Abstract: An operating parameter method and circuitry are provided that generate operating parameter signals that are compensated for noise. Such operating parameter circuitry includes control loop circuitry that operates from a first power supply to provide an operating parameter signal to functional circuitry operating from a second power supply separate from the first power supply. The control loop circuitry comprises generator circuitry to generate the operating parameter signal based on an input signal. Replica generator circuitry operates from the second power supply to generate a further operating parameter signal based on the input signal. Adjustment circuitry performs a comparison on the operating parameter signal and the further operating parameter signal and causes an adjusted input signal to be produced in dependence on a result of the comparison. The adjusted input signal is received by the generator circuitry.

Abstract: A circuit according to an example includes a controllable oscillator configured to generate an output signal based on a control signal, an input signal processing circuit configured to receive a reference signal and configured to generate a sequence of digital values indicative of a phase relation between the reference signal and the output signal or a signal derived from the output signal, and a digital data processing circuit configured to generate a sequence of processed values at a lower frequency than a frequency of the sequence of the digital values, each processed value being based on a plurality of the digital values of the sequence of digital values, wherein the control signal is based on the sequence of processed values.

Abstract: An RF circuit for providing phase coherent signals, an RF heating apparatus comprising the RF circuit and a method for providing phase coherent signals in an RF circuit. The RF circuit has a first frequency synthesiser including a fractional-N phase locked loop and a second frequency synthesiser including an integer-N phase locked loop. An output of the first frequency synthesiser is connected to a phase frequency detector of the integer-N phase locked loop of the second frequency synthesiser via a synchronization signal divider for distributing a synchronization signal from the first frequency synthesiser to the second frequency synthesiser. The integer-N phase locked loop of the second frequency synthesiser comprises a frequency divider of the same modulus as the synchronization signal divider.

Abstract: The disclosure provides a current steering digital to analog converter (DAC) that includes a plurality of DAC elements. At least one DAC element of the plurality of DAC elements is coupled to a calibration circuit. The calibration circuit includes a fixed current source coupled to a primary node of the DAC element through a first estimation switch. A digital code generator is coupled to the primary node, and generates a first digital code corresponding to a primary voltage generated at the primary node. The digital code generator generates a second digital code. A correction DAC is coupled to the digital code generator and generates a bias voltage based on the second digital code. The bias voltage is provided to the DAC element such that a current flowing through each DAC element of the plurality of DAC elements is equal.

Abstract: The embodiments described herein provide calibration systems and methods for mixed-signal devices. Specifically, the embodiments provide systems and methods for calibrating mixed-signal devices that can facilitate effective calibration of such mixed-signal devices, including mixed-signal devices with poorly characterized nonlinearities that cannot be effectively calibrated with traditional calibration techniques. In general, the embodiments described herein calibrate by measuring output values from a mixed-signal device with a known calibration input values being applied. The measured output values are used to determine localized polynomial interpolants. Each of the determined localized polynomial interpolants is then evaluated at an uncorrected output value, and the evaluated localized polynomial interpolants are then used to generate correction values.

Abstract: The present invention is directed integrated circuits and methods thereof. More specifically, an embodiment of the present invention provides a comparator calibration loop where a digital integrator stores a running sum based on the output of a comparator. A DAC converts the running sum and generates an offset calibration voltage, which is filtered by a low-pass filter module, and the filtered offset calibration voltage is used to cancel out the intrinsic offset voltage and low frequency noise of the comparator. There are other embodiments as well.

Abstract: Methods and systems for analog-to-digital conversion applicable to an image sensor, such as a CMOS image sensor, in which an ADC comprises built-in redundancy such that the ADC can start its conversion cycle before the ADC input settles to a desired resolution and the ADC can yet accurately convert the ADC input to a digital value with the desired resolution. In a CMOS image sensor, such an ADC configuration enables the pixel readout time to overlap with the ADC conversion time, reducing the total time needed to convert the pixel signal value to a digital value with the desired resolution.

Abstract: A signal generator includes: a dual-port RAM for digitally storing multiple waveforms in a predefined temporal resolution; multiple channels for modeling in each case one signal pattern from at least one of the waveforms; and multiple digital-analog converters for analog output of the signal patterns in the temporal resolution.

Abstract: A digital to analog converter including a current source for providing a master current, a first sub digital to analog converter coupled to the current source which generates a plurality of currents, and a second sub digital to analog converter coupled to at least one of the plurality of currents from the first sub digital to analog converter which generates a second plurality of currents. The digital to analog converter also includes an overlap adjustment circuit coupled with the second sub digital to analog converter which adds current. The digital to analog converter is configured to operate in a first mode for generating a sine wave with a first bit level accuracy and, when in the first mode, the overlap adjustment circuit adds no current.

Abstract: In one aspect, a compressive sampling encoder comprises matrix determination circuitry configured to determine a particular sampling matrix selected from a codebook comprising a plurality of sampling matrices. The compressive sampling encoder further comprises sampling circuitry coupled to the matrix determination circuitry and configured to apply the particular sampling matrix to a first signal to generate a second signal, and encryption circuitry configured to receive an identifier of the particular sampling matrix and to encrypt the identifier of the particular sampling matrix. The compressive sampling encoder provides at one or more outputs thereof the second signal and the encrypted identifier of the particular sampling matrix. Other aspects include a compressive sampling decoder, compressive sampling encoding and decoding methods, and associated computer program products.

Abstract: Systems and methods are provided for decoding low density parity check (LDPC) codes with different circulant sizes using common decoding circuitry. The systems and methods include receiving a plurality of codewords corresponding to an LDPC code and determining a circulant size associated with the plurality of received codewords. In response to determining the circulant size associated with the plurality of received codewords, the systems and methods partition processing resources of the common decoding circuitry into a plurality of cells based on the determined circulant size and processing the plurality of received codewords simultaneously using the plurality of cells.

Abstract: In one embodiment, a computer program product for providing header protection in magnetic tape recording includes a computer readable storage medium having program instructions embodied therewith, the program instructions readable by a processor to cause the processor to: calculate or obtain, by the processor, codeword interleave designation (CWID) parity for all CWIDs in a codeword interleave (CWI) set header, the CWID parity including error correction coding (ECC) parity, and store, by the processor, the CWID parity to a magnetic tape in one or more fields which are repeated for each CWI header in the CWI set header without using reserved bits in the CWI set header to store the CWID parity. Other systems and methods for providing header protection in magnetic tape recording are described in more embodiments.

Abstract: A coding method intended to increase the error correction performance without greatly increasing the size of an error correction circuit, the method, as illustrated in FIG. 1A, includes the steps of dividing data constituting one page and yet to be coded into data blocks including a first data block located on one end of the one page to a fourth data block located on the other end of the one page; generating a first error correcting code by coding the first data block; generating a second error correcting code by coding a second data block and a part of the first data block in combination; generating a third error correcting code by coding a third data block and a part of the second data block in combination; and generating a fourth error correcting code by coding a fourth data block and a part of the third data block in combination.

Abstract: An adaptation technique for decoding low-density parity-check (LDPC) codes for hard disk drive (HDDs) systems is disclosed. The method includes tuning the normalization factor for LDPC decoding for each data zone and read head during the test stage of manufacturing. The LDPC decoder can be either a sum-product algorithm (SPA) decoder or a Min-Sum decoder. The channel detector can be any soft-output detector, such as a soft-output Viterbit detector (SOVA), a BCJR detector, a pattern-dependent noise-predictive (PDNP) detector, or a bi-directional pattern-dependent noise-predictive (BiPDNP) detector. The adaptation technique can optimize the LDPC decoding performance for each data zone and read head, thereby relaxing the acceptance criteria for hard disk drive read/write heads and disk media, enabling acceptance and use of a much broader range of head and media for hard disk drives.

Abstract: A method and electronic device for encoding data are provided. The method includes acquiring sets xj (j=1 . . . k) and yi (i=1 . . . p) in generating a Generator Cauchy Matrix, wherein k denotes a number of information symbols, and p denotes a number of parity symbols, generating a matrix A1 using the sets xj and yi, wherein elements of the matrix A1 are obtained by 1 x j + y i and have weight of Galois field, and the matrix A1 has a size of P×K, generating a set K, wherein all elements of the set K are not included in the sets xj and yi, updating the set xj by changing at least one element of the set xj for an element of the set K, updating the set yi by changing at least one element of the set yi for the set K element, generating the Generator Cauchy Matrix using the updated sets xj and yi, and encoding data including the information symbols and parity symbols using the Generator Cauchy Matrix.

Abstract: A decoder including a compression module configured to select one or more nodes from a plurality of nodes associated with data being decoded by the decoder, where each node includes one or more bits, and to compress the one or more bits associated with the selected nodes. A memory is configured to store the compressed one or more bits associated with the selected nodes.

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: a frame generator configured to generate a first frame provided for a fixed terminal and a second frame provided for a mobile terminal, the second frame including common service data commonly provided for the fixed terminal and the mobile terminal; an information inserting unit configured to insert access information on the common service data into a signaling area of the first frame; and a transmitter configured to transmit the first and second frames.

Abstract: An apparatus for testing for the susceptibility of an aircraft system to radio frequencies comprises a wireless module for generating radio signals that sweep each of the 2.4 GHz frequency band and the 5 GHz frequency band. A first amplifier is configured for amplifying signals in the 2.4 GHz band, and a second amplifier is configured for amplifying signals in the 5 GHz band. The apparatus comprises at least one dual band antenna for transmitting the signals in each of the 2.4 GHz and the 5 GHz bands.

Abstract: A multi-band amplifier may operate in a first frequency band and a second frequency band. The multi-band amplifier may include a first amplifier, a second amplifier, and a coupler. The coupler may couple a signal, such as a communication signal, to a selected amplifier. In some embodiments, the coupler may include one or more inductive elements to couple the signal to the first or the second amplifier. In some embodiments, the inductive elements may include a balun.

Abstract: Radio frequency (RF) front end circuitry includes first RF multiplexer circuitry and second RF multiplexer circuitry. The first RF multiplexer circuitry is a quadplexer, while the second RF multiplexer is a triplexer. The RF front end circuitry is configured to support the transmission and reception of signals within a first operating band, a second operating band, and a third operating band. Further, the RF front end circuitry is configured to support carrier aggregation configurations between the first operating band and the third operating band and the second operating band and the third operating band.