Abstract: Non-limiting examples of the present disclosure describe decoupling task state tracking that is managed by a shared task completion platform from execution of tasks by a task resource owner. Task registration data is received at a shared task state platform for a task that is executable by a task owner resource. Task registration data comprises parameters to be collected for execution of the task and ancillary information, such as the name of the task and whether to confirm the values of the parameters after collection. During interaction with a user, the shared task completion platform receives an input and determines the task is associated with the received input. During the interaction, parameters of the received task registration data are utilized to collect data for execution of the task. The collected data is transmitted to the task owner resource for execution of the task.

Abstract: A system is provided in which a scheduler of each environment acquires task information associated with its own identification information from a database to control execution of a task. With respect to task information that is not executed by a scheduler in any environment in operation, a scheduler in a production environment controls execution of the task.

Abstract: The following relates generally to computer system efficiency improvements. Broadly, systems and methods are disclosed that improve efficiency in a cluster of nodes by efficient processing of tasks among nodes in the cluster of nodes. Assignment of tasks to compute nodes may be based on learned CPU capabilities and I/O bandwidth capabilities of the compute nodes in the cluster.

Abstract: According to embodiments illustrated herein there is provided a method for assigning one or more resources to a task. The method includes determining one or more workflows, comprising one or more sub-tasks in a sequence, utilizable to process the task. The method further includes determining a set of scores for each sub-task associated with each workflow based on at least a set of performance attributes of a set of resources who are available for processing each sub-task. The disclosed method further includes assigning at least a resource from the set of resources, available for processing each sub-task, based on at least one of the determined set of scores and one or more predefined requisites associated with each sub-task.

Abstract: A system for allocating field-programmable gate array (FPGA) resources comprises a plurality of FPGAs operable to implement one or more pipeline circuits, the plurality of FPGAs comprising FPGAs of different processing capacities, and one or more processors operable to access a set of data comprising a plurality of work items to be processed according to a pipeline circuit associated with each of the plurality of work items, determine processing requirements for each of the plurality of work items based at least in part on the pipeline circuit associated with each of the plurality of work items, sort the plurality of work items according to the determined processing requirements, and allocate each of the plurality of work items to one of the plurality of FPGAs, such that no FPGA is allocated a work item with processing requirements that exceed the processing capacity of the FPGA.

Abstract: Methods, systems, and computer programs are presented for allocating CPU cycles in a storage system. One method includes operations for receiving requests to be processed, and for associating each request to one task. A foreground task is for processing input/output requests, and the foreground task includes one or more flows. Each flow is associated with a queue and a flow counter value, where each queue is configured to hold requests. The method further includes an operation for selecting one task for processing by the CPU based on an examination of the number of cycles processed by the CPU for each task. When the selected task is the foreground task, the flow having the lowest flow counter is selected. The CPU processes a request from the queue of the selected flow, and the flow counter of the selected flow is increased based on the data consumption of the processed task.

Abstract: A method for scheduling the execution of a computer instruction, receive an entitlement processor resource percentage for a logical partition on a computer system. The logical partition is associated with a hardware thread of a processor of the computer system. The entitlement processor resource percentage for the logical partition is stored in a register of the hardware thread associated with the logical partition. An instruction is received from the logical partition of the computer system and the processor dispatches the instruction based on the entitlement processor resource percentage stored in the register of the hardware thread associated with the logical partition.

Abstract: The present invention provides an information processing device to efficiently execute a plurality of analysis engines on a plurality of analysis processing devices. The information processing device includes an arrangement control means that determines an arrangement pattern indicating connection between a plurality of data distribution devices and a plurality of controlled information processing devices based on cost information indicating price values of operation of a load control executing means regarding data processing and a dynamic load control means that connects the data distribution device to the controlled information processing device based on the arrangement pattern and controls start and stop of operation of the load control executing means based on the cost information and a load status of the controlled information processing device.

Abstract: A distributed work processing system for processing computational tasks is scalable and fault-tolerant without requiring centralized control. Worker processes running on worker hosts are organized into a logical group and worker coordinators running on worker coordinator hosts coordinate tasks assigned to worker processes. A task store might hold a collection of tasks to be performed by the logical group. A lock database can be used for locking the logical group for coordination by one worker coordinator process at a time. A membership store contains mappings of worker processes to logical groups, and an assignment store indicates which tasks are assigned to which workers. The worker coordinator process has a scanner process to deal with unassigned tasks and deduplicating duplicate assignments. If a worker coordinator does not see enough worker processes, it can instantiate more. If a worker process does not see a worker coordinator, it can instantiate one.

Abstract: Implementations are disclosed herein for enhancing swizzling technology. In at least one implementation, functions are hooked by modifying their machine code implementations to jump to a central callback function. The central callback function may then route to other target functions that serve to replace the hooked functions. In another implementation, the machine code implementations are modified to jump to intermediate functions. The intermediate functions invoke dispatch functions that can call into a central callback function. The central callback function may return to the hooked functions.

Abstract: Methods, systems, and computer program products for applying actions during server system processing. Functional processing blocks where actions may be applied to a service request are identified. actions are dynamically associated with functional processing blocks. During execution of a functional processing block, a check is performed to determine whether an action is associated with the functional processing block. If an action is associated with a functional processing block, the action is applied during the functional processing block's execution. An evaluation may be performed to determine if an action should be applied before or after the functional processing block. The server system may comprise an XML data repository, providing access to XML data, based on identity information which is received with a client system request. A portion of the server system may be described in accordance with an XML schema.

Abstract: Differing implementations associated with components of dissimilar execution environments are mediated to facilitate component integration. A host is provided to facilitate native interaction with foreign components by translating between native and foreign communications. Policies can be specified by either or both of a native and foreign component that control interaction.

Abstract: An electronic device includes a memory configured to store at least one application and a processor configured to connect to the memory. The processor is configured to provide a list of external devices, having the same attributes as at least part of operation attributes of the at least one application, based on a state where the at least one application is registered in a device manager, in which at least one external device is registered, to operate as a device.

Abstract: A system and method for providing a message bus component or version thereof (referred to herein as an implementation), and a messaging application program interface, for use in an enterprise data center, middleware machine system, or similar environment that includes a plurality of processor nodes together with a high-performance communication fabric (or communication mechanism) such as InfiniBand. In accordance with an embodiment, the messaging application program interface enables features such as asynchronous messaging, low latency, and high data throughput, and supports the use of in-memory data grid, application server, and other middleware components.

Abstract: A method for binding a first and second devices is disclosed. The method is implemented using the architectural principles of REST, which allows a binding initiator to directly contact the first device and instruct the device of actions to be taken. Specifically, the binding initiator may contact the first device by providing a first REST request to the device, the request specifying that the first device is to monitor a state of a particular REST resource identified by the request and is to trigger the second device to perform a specified action when the state of that REST resource satisfies a particular condition. Using REST further allows the first device to directly contact the second device and instruct the second device to perform the specified action. Since the first device is now able to directly contact the second device, these two devices may be considered to be bound.

Abstract: The present invention relates to a method and apparatus which corrects antenna noise temperature in antenna back lobes, for earth-observing microwave instruments on satellites in orbit, to counter signal contamination from celestial bodies. The antenna back lobe signal correction is computer-program-modeled with only a few static and only a few dynamic inputs, and for a given set of parameters (i.e., orbital altitude, pointing characteristics (e.g., nadir or cross-scanning or conical-scanning), frequency selectivity of the receiver/detector) produces a few output files which are then combined by the program to predict the back lobe signal correction which is to be applied.

Abstract: Technology is disclosed for determining high availability readiness of a distributed computing system (“system”). A confidence measure (CM) can be computed for a particular controller in the system to determine whether a takeover by the particular controller from a first controller would be successful. The CM can be a percentage value. A CM of 0% indicates that a takeover would be a failure, which results in loss of access to data managed by the first controller. A CM of 100% indicates a successful takeover with no performance impact on the system. A CM between 0% and 100% indicates a successful takeover but with a performance impact. The CM can be computed based on events occurring in the system, e.g., veto and non-veto events. The CM is computed as a function of various weights and/or indices associated with the veto events and/or non-veto events.

Abstract: An approach for two stage log normalization is provided. The approach retrieves a message format and a plurality of parameters from one or more log files. The approach determines a classification for one or more first sequence files, wherein the one or more first sequence files includes the message format from the one or more log files. The approach determines a classification of error for the one or more first sequence files. The approach determines whether there is a high confidence in the classification of error for the one or more first sequence files. The approach determines whether there is an improvement in confidence in the classification of error from one or more second sequence files, wherein the one or more second sequence files includes the message format and the plurality of parameters from the one or more log files.

Abstract: Embodiments of the innovation relate to a host device having a memory and a processor, the host device configured to determine an anomaly associated with an attribute of a computer environment resource of the computer infrastructure. The host device is configured to correlate an object associated with the attribute of the detected anomaly with a related object of the computer infrastructure. The host device is configured to determine a root cause probability for each object of the correlated objects, the root cause probability identifying a probability of the correlated object functioning as a cause of the detected anomaly. The host device is configured to output an identification of a root object associated with the anomaly based upon the identified root cause probability.

Abstract: A method of providing troubleshooting for an in vitro diagnostics instrument includes receiving, via a computing device, identification of one of a plurality of issues of the instrument, each of the plurality of issues associated with a portion of the instrument. An ordered list of one or more corrective actions to resolve the issue is provided via a user interface in communication with the computing device. The ordered list is stored in a database in communication with the computing device. The computing device receives an indication via the user interface of the one or more corrective actions determined to successfully resolve the issue.

Abstract: A system for allocating field programmable gate array (FPGA) resources, comprises a plurality of FPGAs operable to implement one or more pipeline circuits; and one or more processors operable to determine the size of a set of data to be processed, determine an amount of time available to process the data set, determine an operational clock speed for the plurality of FPGAs, determine, based at least in part on the determined size of the set of data, the determined amount of time, and the determined operational clock speed, a number of FPGAs to allocate to process the set of data within the determined amount of time, and allocate at least the determined number of the plurality of FPGAs to process the set of data.

Abstract: The present invention makes it possible to process a plurality of commands included in a series of communication processes in a shared manner by a plurality of circuit parts, thereby improving reliability and processing performance. A semiconductor integrated circuit for communication (212) includes: a plurality of first circuit parts (2121) that are responsible for communicating with a higher-level apparatus (4); a plurality of second circuit parts (2122), which analyze a command included in a series of communication processes, and which share the processing of a plurality of commands included in the series of processes with another second circuit part; a common connector (2123) for connecting the first circuit parts to the second circuit parts; and a failure management part (2124), which, when a failure has occurred in any circuit part, causes the stoppage of processing by a stop-target circuit part that must stop processing.

Abstract: A two part process is used for modifying records to be written and retrieved from tape devices. A record is appended with a cyclic redundancy check and a string of zeros. Submitting the entire record to tape drives which are logical block protection enabled will result in no change. For drives that are not LBP enabled, the string of zeros at the end of the record is removed. In addition to determining whether a drive is LBP compliant, a determination may be made as to whether a drive is a linear tape open drive from a particular manufacturer. Linear tape open drives may behave similarly as drives which may not be enabled with logical block protection.

Abstract: A storage module is configured to store data segments, such as error-correcting code (ECC) codewords, within an array comprising two or more solid-state storage elements. The data segments may be arranged in a horizontal arrangement, a vertical arrangement, a hybrid channel arrangement, and/or vertical stripe arrangement within the array. The data arrangement may determine input/output performance characteristics. An optimal adaptive data storage configuration may be based on read and/or write patterns of storage clients, read time, stream time, and so on. Data of failed storage elements may be reconstructed by use of parity data and/or other ECC codewords stored within the array.

Abstract: Provided is a non-volatile semiconductor storage device which can be downsized with a simple circuit without impairing the function of an error correcting section, and a method of testing the non-volatile semiconductor storage device. An error correction circuit is configured to perform error detection and correction of merely the same number of bits as data bits, and a circuit for performing error detection and correction of check bits is omitted to downsize the circuit. A multiplexer for, in a testing state, replacing a part of the data bits read out from a storage element array with the check bits, and inputting the check bits to the error correction circuit is provided. Thus, error detection and correction of the check bits are performed to enable shipment inspection concerning the check bits as well.

Abstract: Aspects of the disclosure relate to storage systems for providing low latency read access of a non-volatile memory. One such system includes a non-volatile memory (NVM) configured for read access via a primary data path, a syndrome checker disposed along the primary read data path and configured to check a codeword read from the NVM for errors, an error correction code circuitry disposed outside of the primary data path and, if the codeword is determined to contain an error, configured to determine a location of the error in the codeword, and a queue disposed along the primary read data path. The queue is configured to receive the codeword from the syndrome checker and output the codeword to a host. If the codeword is determined to contain the error, the queue corrects the error based on the determined location of the error from the error correction code circuitry.

Abstract: There is provided an error correction device with a simple configuration and a high correction capability. An error correction device which can perform c (c<n) error corrections on n-bit encoded data containing a parity bit includes an assumption data setting circuit for setting a plurality of assumption data, containing c error bits and (n?c) or fewer erasure bits, by assuming data of an erasure bit, and a decoding circuit which calculates a syndrome for each of the assumption data set by the assumption data setting circuit and performs decoding based on a calculation result and the parity bit.

Abstract: A memory, such as a non-volatile ferroelectric memory, including both error correction coding (ECC) capability and redundant memory cells. During the system operating life of the memory, upon ECC decoding determining that a symbol read from the memory array at an address cannot be corrected, the failed memory cells are identified, and redundancy enabled to replace those failed cells if available. Redundant columns may be partitioned by row address, to allow the same column of redundant cells to replace bits in different columns for different portions of the memory. Dynamic redundancy is provided by the disclosed embodiments, extending the reliability of the memory during its system operating life.

Abstract: A mechanism is provided in a data processing system for securing data integrity in de-duplicated storage environments in combination with software defined native redundant array of independent disks (RAID). The mechanism receives a data portion to write to storage, divides the data portion into a plurality of chunks, and identifies a given chunk within the plurality of chunks for de-duplication. The mechanism increment a de-duplication counter for the given chunk and determines a RAID level for the given chunk based on a value of the de-duplication counter. The mechanism stores the given chunk based on the determined RAID level.

Abstract: Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for multiple codeword processing in a data processing system.

Abstract: A node includes: an arithmetic processing device; and a first memory, wherein the arithmetic processing device includes: a processor core; a storing circuit to store a first failure node list in which first information indicating that a failure has occurred or second information indicating that no failure has occurred is set for each of nodes; a request issuing circuit to issue a first request to a second memory provided at a first node among the nodes; a setting circuit to set the first information for the first node in the first failure node list when the first request has timed out; and an issuance inhibition circuit to inhibit, based on a second request to the second memory from the processor core, the second request from being issued by the request issuing circuit when the first information is set for the first node in the first failure node list.

Abstract: A storage system according to the present invention comprises a controller and multiple storage devices, constitutes a RAID group from (n+m) number of storage devices, wherein the storage system stores write data from a host computer to n number of storage devices, and stores redundant data generated from the n number of data to m number of storage devices. When failure occurs to at least one storage device, the controller reads data in a compressed state and redundant data from each of the storage devices where failure has not occurred in the storage devices constituting the RAID group, and transmits the read data in the compressed state to the storage device which is a data recovery destination.

Abstract: A synchronization engine detects a notification of a change to a file. It determines whether an application associated with the file has indicated that the file is to be synchronized by the application. If so, the changes to the file are synchronized between a cloud-based storage system and a local disk by the application. Collaborative metadata, associated with the synchronized file, is updated to indicate a state of a copy of the file on the local disk and a copy of the file in the cloud-based storage system. The collaborative metadata is stored by the synchronization engine.

Abstract: An update information managing unit, when specific data is updated, adds update information to the specific data, prevents a predetermined program from deleting the update information, and deletes the update information added to the specific data when a predetermined condition of the specific data is satisfied. A utilization program executing unit, when the update information is added to the specific data, performs a predetermined process on the specific data.

Abstract: A computer-implemented method, system and computer program product, the method comprising: receiving a request for backing up data from a mainframe on a backup server implemented on an open system; issuing a call to data set services, the call associated with an exit function; receiving a callback to the exit function, the callback associated with a data set record; packing the data set record to obtain packed information; and transmitting the packed information over a network connection to the backup server for backing up the data, wherein no additional data is written to a persistent memory of the mainframe, and wherein no limitations exist on a number of mainframes connected to the mainframe, or on a number of mainframes simultaneously communicating with the backup server.

Abstract: Techniques are described herein which minimize the impact of virtual machine snapshots on the performance virtual machines and hypervisors. In the context of a volume snapshot which may involve (i) taking virtual machine snapshots of all virtual machines associated with the volume, (ii) taking the volume snapshot, and (iii) removing all the virtual machine snapshots, the virtual machine snapshots may be created in a first order and removed in a second order. Specifically, snapshots for busy virtual machines (i.e., virtual machines with higher disk write activity) may be created last and removed first. Consequently, snapshots of busy virtual machines are retained for shorter periods of time, thereby minimizing the effect of virtual machine snapshots on those virtual machines (and their associated hypervisors) that would be most negatively impacted by virtual machine snapshots.

Abstract: According to one embodiment, a memory system is connectable to a host. The memory system includes a first memory, a second memory, and a controller. The first memory stores translation information associating a logical address and a physical address. The second memory stores location information associating the logical address and a location of the translation information. The controller updates the translation information and the location information. After returning from a power supply interruption, the controller starts, at different timing, recovery of first location information and recovery of second location information. The first location information is a part of the location information. The second location information is a part of the location information different from the first location information. The controller executes processing different from recovery of the location information between the recovery of the first location information and the recovery of the second location information.

Abstract: A method for processing return entities associated with multiple requests in a single ISR (Interrupt Service Routine) thread, performed by one core of a processing unit of a host device, is introduced. Entities are removed from a queue, which are associated with commands issued to a storage device, and the removed entities are processed until a condition is satisfied.

Abstract: A storage controlling device including a memory and a processor configured to obtain information on each of a plurality of remaining lives of each of a plurality of storage devices included in a redundancy storage system, determine each of a plurality of timings for replacement of each of the plurality of storage devices so that a number of the timings for replacement included in a predetermined time range is less than a predetermined number, each of a plurality of timings for replacement being determined to be earlier than each of the plurality of timings that malfunctions occur in each of the plurality of storage devices corresponding to each of a plurality of timings for replacement, each of the plurality of timings that malfunctions occur being specified based on the obtained information, and output information that indicates at least one of the plurality of determined timings for replacement.

Abstract: A method and apparatus using a non-intrusive probe for testing double data rate interfaces is provided. The method begins with the generation of at least one component parameter model, which is then cascaded to form a full system parameter model of the double data rate interface being tested. Transfer functions are generated using the full system parameter model. A target transfer function is calculated between the test equipment and a decision point. The calculated target transfer function is applied and testing is completed. The apparatus includes a device to be tested, mounted on a circuit board. A probe card is attached to the backside of the circuit board and is in communication with a high-speed connector. At least one connector in communication with the high-speed connector and at least one small footprint RF connector on an accessible side of the circuit board are also part of the non-intrusive probing apparatus.

Abstract: A system and method are provided for managing internal-computer system communications in an SPI management system. The system includes a storage device, at least one serial bus interface to interface with a serial bus, and a processing unit that accesses via the at least one serial bus interface, master data propagating from a master device along the serial bus. The processing unit stores, in the storage device, at least one of timing and phase data related to clock pulses associated with the master data, and a phase relationship between the clock pulses and at least one of the master data and return data propagating from a slave device in response to the master data.

Abstract: A data collection apparatus includes a data collection section configured to receive sequential time-series output data pieces for each of data sources, a data shaping section configured to perform data shaping processing on the sequential time-series output data pieces based on a predetermined data shaping rule set for each of the data sources such that the resulting data pieces are reduced in number or in data amount as compared with the output data pieces output from the data source, a data transmission section configured to transmit the output data pieces to the monitor control apparatus, and a data shaping rule control section configured to receive the data shaping rule set for each of the data sources from the monitor control apparatus and to set the received data shaping rule in the data shaping section.

Abstract: Provided are a software detection method and device.

Abstract: Systems, methods, and computer-readable media for securing a mobile device application using an application wrapper while preserving and/or improving performance of the wrapped application are presented. In one or more embodiments, an application wrapper may detect, during execution of a wrapped application, at least one performance caused by the application wrapper. The application wrapper may modify execution of the wrapped application to address the at least one detected performance issue. In some instances, the at least one performance issue may be associated with a cache that stores one or more pages from a database, and the cache and the database may be maintained within the wrapped application.

Abstract: Testing computer software applications is performed by identifying first and second executable portions of the computer software application, where the portions are configured to access a data resource, and where at least one of the portions is configured to write to the data resource, instrumenting the computer software application by inserting one or more instrumentation instructions into one or both of the portions, where the instrumentation instruction is configured to cause execution of the portion being instrumented to be extended by a randomly-determined amount of time, and testing the computer software application in multiple iterations, where the computer software application is executed in multiple parallel execution threads, where the portions are independently executed at least partially in parallel in different threads, and where the computer software application is differently instrumented in each of the iterations.

Abstract: Embodiments of the present invention provide methods, systems, and computer program products for building an environment. Embodiments of the present invention can be used to allocate resources and build an environment such that the environment is built when a user is prepared to test one or more portions of code in the environment. Embodiments of the present invention can be used to reduce the “lag time” developers experience between waiting for the code to be built and for resources to be provisioned, and can also provide a less costly alternative to maintaining and operating dedicated environments.

Abstract: In order to perform system-capability testing, an application in an application layer may provide predefined system capabilities and/or requirements of or associated with the application to a communication plugin in a data-link layer, such as availability of communication via a network and/or a latency of the network less than a predefined value. In response, the communication plugin may determine feedback information that specifies whether the predefined system capabilities are available and whether the predefined requirements are satisfied. Then, the communication plugin may provide the feedback information to the application. When the feedback information indicates that a system capability is unavailable, remedial action may be performed. For example, the remedial action may include updating a version of the application, updating a version of the communication plugin, and/or updating a path to a location in a network.

Abstract: A method for testing an application running on an electronic device includes parsing, by a test processor, a state model of the application representing relationships among a plurality nodes, each node representing an application state. The method further includes parsing, by the test processor, a test implementation file including a plurality of commands for manipulating at least one of the application and the electronic device, each of the plurality of commands associated with respective ones of the plurality of nodes, traversing, by the test processor, the state model of the application by selecting for testing an application node in accordance with the node relationships in the state model. The method also includes selecting, by the test processor, one or more of the plurality of commands for testing the application based on at least one criteria, and executing, by the test processor, the one or more selected commands.

Abstract: A memory system for a network device is described. The memory system includes a main memory configured to store one or more data elements. Further, the memory system includes a link memory that is configured to maintain one or more pointers to interconnect the one or more data elements stored in the main memory. The memory system also includes a free-entry manager that is configured to generate an available bank set including one or more locations in the link memory. In addition, the memory system includes a context manager that is configured to maintain metadata for a list of the one or more data elements.

Abstract: A memory system for a network device is described. The memory system includes a main memory configured to store one or more data elements. Further, the memory system includes a link memory that is configured to maintain one or more pointers to interconnect the one or more data elements stored in the main memory. The memory system also includes a free-entry manager that is configured to generate an available bank set including one or more locations in the link memory. In addition, the memory system includes a context manager that is configured to maintain metadata for a list of the one or more data elements.