Abstract: Resource management in MapReduce architecture and architectural system. The present invention provides an apparatus for resource management in the MapReduce architecture including a memory, a processor communicatively coupled to the memory, and a module for resource management in the MapReduce architecture configured to carry out the steps of a method. The method includes the steps of: determining a ratio r of an input data amount of a Map task, an output data amount of the Map task, and an average size R of a record in Map output results; determining a memory size Memory_size that can be allocated to the Map task corresponding to a Map slot; determining an input split size appropriate for the Map task according to the determined r, R and Memory_size; and allocating an input split with the input split size in a MapReduce job to be processed to the Map task occupying the Map slot.

Abstract: A mapping table updating method for a rewritable non-volatile memory module is provided. The method includes: allocating a mapping table storage area for storing a physical address-logical address mapping table in a buffer memory. The method also includes: determining whether a remaining storage space of the mapping table storage area is less than a threshold. If the remaining storage space is less than the threshold, mapping information of the physical address-logical address mapping table stored in the mapping table storage area is updated into at least one logical address-physical address mapping table, and the mapping information of the physical address-logical address mapping table stored in the mapping table storage area is cleared. The method also includes: storing updated mapping information corresponding to a programmed active physical erasing unit into the mapping table storage area.

Abstract: A storage device for deduplicating data includes a memory that stores machine instructions and a controller coupled to the memory to execute the machine instructions in order to compare a data pattern associated with a write request to stored data. If the data pattern matches the stored data, the controller further executes the machine instructions to increment a counter associated with the data pattern and map a source storage address corresponding to the data pattern to a physical storage address associated with the storage device.

Abstract: An age compensation method and apparatus for an integrated circuit (IC). An IC may be configured to operate at an initial operating voltage at the beginning of its operational life. Various circuits may be used to detect aging of the IC, and indications of aging may be stored to determine the aging of the IC. The information indicative of the determined aging of the IC may be compared to an aging threshold. If the information indicates that the aging is greater than or equal to the determined aging threshold, the operating voltage of the IC may be increased. This process may be repeated over the life of the IC, increasing the operating voltage as the IC ages. Raising the operating voltage in response to aging may compensate for various age related degradation mechanisms that can occur over the operational life of the IC.

Abstract: A data access control apparatus of an embodiment includes an update region management apparatus including an update region management unit configured to record, in response to a writing request for data from an input apparatus, management information of a first address region in which the data is stored, a reading request management unit configured to record a second address specified in a reading request from a storage apparatus and a control unit configured to receive the writing request and the reading request, and control processing of the reading request and updating of the update region management unit and the reading request management unit.

Abstract: One embodiment of the present invention provides a system for efficiently warming up a cache. During operation, the system determines a cache prediction based on a user request. The cache prediction determines replication data from a database; the replication data is data that is to be replicated in the cache from the database for warming up the cache. The system generates a control signal comprising a replication proportion, which determines the volume of the replication data, for the replication model. The system then stores the replication data prior to receiving a request for the replication data, thereby warming up the cache with the replication data.

Abstract: A host device includes a controller configured to receive input/output (TO) access information associated with an IO workload, the IO access information identifying at least one of a read action and a write action associated with the IO workload over a period of time. Based upon the received IO access information associated with the storage element, the controller is configured to derive a predicted cache access ratio associated with the IO workload and relating a predicted number of cache accesses associated with the IO workload with at least one of a total number of read actions and a total number of write actions associated with the IO workload. When the predicted cache access ratio reaches a threshold cache access ratio value, the controller is configured to identify the IO workload as an IO workload candidate for caching by the host device.

Abstract: Aspects include computing devices, systems, and methods for implementing generating a cache memory configuration. A server may apply machine learning to context data. The server may determine a cache memory configuration relating to the context data for a cache memory of a computing device and predict execution of an application on the computing device. Aspects include computing devices, systems, and methods for implementing configuring a cache memory of the computing device. The computing device may classify a plurality of cache memory configurations, related to a predicted application execution, based on at least a hardware data threshold and a first hardware data. The computing device may select a first cache memory configuration from the plurality of cache memory configurations in response to the first cache memory configuration being classified for the first hardware data, and configuring the cache memory at runtime based on the first cache memory configuration.

Abstract: An instruction is provided to perform invalidation of an instruction specified range of segment table entries or region table entries. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.

Abstract: Systems and methods for generating random address mapping in non-volatile memories using local and global interleaving are provided. One such method for generating a random address mapping for a non-volatile memory (NVM) involves identifying a number of bits (N) in a physical address space of the NVM, selecting G bit(s) of the N bits to be used for global interleaving, where G is less than N, determining a number of bits (N-G) to be used for local interleaving, mapping the G bit(s) using a mapping function for global interleaving, interleaving (N-G) bits using an interleaving function for local interleaving, and generating a combined mapping comprising the mapped G bit(s) and the interleaved (N-G) bits.

Abstract: A system can translate an input/output (I/O) direct memory access (DMA) address to a physical system memory address in a data processing system. In response to receiving a DMA packet containing a requester identity (RID) associated with a partitionable endpoint (PE) number and an I/O DMA address, the system can retrieve an entry associated with the RID from a first translation validation table (TVT). Using that entry, the system can validate the number of TVT entries and extract from the I/O DMA address an offset. This offset can be validated and used to retrieve an entry in a second TVT. Data from this entry can be validated and the system can use this to access another table to retrieve the translation to the physical system memory address.

Abstract: An apparatus and method for implementing a heterogeneous memory subsystem is described. For example, one embodiment of a processor comprises: memory mapping logic to subdivide a system memory space into a plurality of memory chunks and to map the memory chunks across a first memory and a second memory, the first memory having a first set of memory access characteristics and the second memory having a second set of memory access characteristics different from the first set of memory access characteristics; and dynamic remapping logic to swap memory chunks between the first and second memories based, at least in part, on a detected frequency with which the memory chunks are accessed.

Abstract: Methods for distributed storage in accordance with embodiments of the invention enable secret sharing. One embodiment includes encoding source data using an encoding system to produce a plurality of sets of encoded data, where: the source data can be recovered from at least a portion of less than all of the plurality of sets of encoded data; and the source data cannot be recovered using less than a threshold number of the plurality of sets of encoded data; storing each of the plurality of sets of encoded data on a storage device from a set of storage devices on which encoded data is stored; determining a set of storage devices that are available using a decoding system, where the set of storage devices that are available does not include all of the storage devices in the set of storage devices on which encoded data is stored.

Abstract: In one embodiment, the data storage apparatus includes a control unit configured to decode at least one input command and configured to generate at least one of a read signal and a start signal in response to the input command. The start signal indicates to start an internal mode determination process. The data storage apparatus also includes a memory unit configured to output data in response to the read signal, and a coding unit configured to start and perform the internal mode determination process in response to the start signal. The internal mode determination process includes autonomously determining a coding mode, and the coding unit is configured to code the output data based on the determined coding mode to produce coded data.

Abstract: An asymmetric multiprocessor system (2) includes a plurality of processor cores (4, 6) supporting transactional memory via controllers (14, 16) as well as one or more processor cores 8 which do not support transactional memory via hardware. The controllers respond to receipt of a request for exclusive access to a lock address by determining whether or not their associated processing element is currently executing a memory transaction guarded by a lock value stored at that lock address and if their processing element is executing such a transaction, then delaying releasing the lock address for exclusive access until a predetermined condition is met. If the processing element is not executing such a guarded memory transaction, then the lock address may be unconditionally released for exclusive access. The predetermined condition may be that a threshold delay has been exceeded since the request was received and/or that the request has previously been received and refused a threshold number of times.

Abstract: A synchronous serial peripheral device has a transmission unit coupled with a data output line and a clock unit coupled with a clock line. The serial peripheral device transmits a minimum of a single transmission, wherein in a first operating mode the transmission unit and the clock unit are configurable to perform a data transmission with a data length that can be defined to be between one (1) and eight (8) bit.

Abstract: A cluster manager of a computer cluster determines an allocation of resources from the endpoints for running applications on the nodes of the computer cluster and configures the computer cluster to provide resources for the applications in accordance with the allocation. The cluster may include a Peripheral Component Interconnect express (PCIe) fabric. The cluster manager may configure PCIe multi-root input/output (I/O) virtualization topologies of the computer cluster. The allocations may satisfy Quality of Service requirements, including priority class and maximum latency requirements. The allocations may involve splitting I/O traffic.

Abstract: A memory buffering system is disclosed that arbitrates bus ownership through an arbitration scheme for memory elements in chain architecture. A unified host memory controller arbitrates bus ownership for transfer to a unified memory buffer and other buffers within the chain architecture. The system is used within a communication system with a bus in chain architectures and parallel architectures.

Abstract: Methods, apparatus, and system for use in adaptive communication interfaces are disclosed. An adaptive communication interface is provided, in which a high-speed clock provided in a high-speed mode of operation is suppressed in a low-power mode of operation. In the low-power mode of operation, a low-speed command dock is used for data transfers between a memory device and a system-on-chip, applications processor or other device. A method for operating the adaptive communication interface may include using a first clock signal to control transmissions of commands to a memory device over a command bus. In a first mode of operation, the first clock signal controls data transmissions over the adaptive communication interface. In a second mode of operation, the second clock signal controls data transmissions over the adaptive communication interface. The frequency of the second clock signal may be greater than the frequency of the first clock signal.

Abstract: A data storage device includes a controller coupled to multiple groups of data storage dies, such as a meta-meta-die. The controller is configured to write data to a first meta-block if a storage size associated with a first group of data storage dies associated with a first priority is greater than or equal to a threshold storage size. The first meta-block includes a respective block of each data storage die of the first group. The controller is further configured to write the data to a second meta-block if the storage size associated with the first group is less than the threshold storage size. The second meta-block includes a respective block of each data storage die of the first group and further includes a respective block of each data storage die of the second group. Each data storage die of the second group is associated with a second priority.

Abstract: Embodiments of input/output hub unit are disclosed for aggregating interrupts received from multiple endpoint devices. The input/output hub may include an interface unit and one or more communication units. Each communication unit may be configured to receive messages from a corresponding endpoint device. The interface unit may be configured to update a first pointer within a first data structure responsive to a request from a given one of the communication units. The interface unit may be further configured to stored data in a second data structure responsive to updating the first pointer, reading a second pointer and the first pointer, and sending an interrupt responsive to a determination that the first and second pointers are equal.

Abstract: A memory system includes a first plurality of nonvolatile memory devices of a first channel of the memory system, the first plurality of memory devices each being connected to a first communications bus; a second plurality of nonvolatile memory devices of a second channel of the memory system, the second plurality of memory devices each being connected to a second communications bus, and a first interconnection between a first memory device and a second memory device, the first memory device being a memory device from among the first plurality of nonvolatile memory devices, the second memory device being a memory device from among the second plurality of nonvolatile memory devices.

Abstract: A data processing system includes a plurality of data processing devices that perform in parallel data processing on the basis of initial setup data. The data processing devices each has a unique ID and includes a plurality of registers that store the initial setup data and a transfer circuit. The transfer circuit receives packets including a payload that is the initial setup data, shared information, a destination ID and a destination address and, when the shared information indicates that the payload is the initial setup data to be set commonly into the plurality of the data processing devices including its own data processing device, transfers the payload to the register that the destination address indicates irrespective of mismatching between the destination ID and its own ID.

Abstract: A transmission terminal includes at least one processor configured to transmit a terminal information request to request the number of transmission terminals under transmission to a transmission management apparatus connected via a network; and display image data received from one or more of the transmission terminals under transmission on a display device, and display the number of the transmission terminals under transmission received from the transmission management apparatus in response to the terminal information request on the display device.

Abstract: A multi-matrix bus system is disclosed that provides proactive quality of service (QoS) by propagating, as soon as possible through an arbitration node in a network transfer request path, a highest priority value coming from an upstream arbitration node or master that has a current bus request pending at the arbitration node. The bus system ensures that any last downstream arbitration node knows at any time which is the highest priority request pending in the network transfer request path from the masters that are competing to share the bus layer switches and arbitration nodes in the network transfer request path.

Abstract: This application is directed to a stacked semiconductor device assembly including first and second integrated circuit (IC) devices. Each of the first and second IC devices further includes a master interface, a channel master circuit configured to receive read/write data using the master interface, a slave interface, a channel slave circuit configured to receive read/write data using the slave interface, a memory core coupled to the channel salve circuit, and a modal pad. The first and second IC devices are configured such that in response to at least a modal selection signal received at one of the modal pads of the first and second IC devices, one of the first and second IC devices is configured to receive read/write data using its respective charnel master circuit, and the other of the first and second IC devices is configured to receive read/write data using its respective channel slave circuit.

Abstract: A computing device may include a universal serial bus (USB) port, a port controller, and a first port multiplexer. The port controller may determine that a connector of a cable has been connected to the port of the computing device and determine that the cable includes a second port multiplexer. The port controller may send a first instruction to the first port multiplexer to select a single-ended signaling configuration and send a second instruction to the second port multiplexer to select the single-ended signaling configuration. In the single-ended configuration, the first port multiplexer may receive a set of differential signals, convert the set of differential signals to a corresponding set of single-ended signals, and output the set of single-ended signals to the port.

Abstract: A firmware updating method in just a bunch of disks includes the following blocks. A motherboard is coupled to a first primary storage extension chip or to a second primary storage extension chip. The first primary storage extension chip and the second primary storage extension chip are coupled to each other. At least one secondary storage extension chip is coupled to the first primary storage extension chip. At least one secondary storage extension chip is coupled to the second primary storage extension chip. A signal sent to the first primary storage extension chip or to the second primary storage extension chip by the motherboard causes firmware of each storage extension chip to be updated.

Abstract: Methods and systems are disclosed which may provide MultiGig capability to a system where a physical layer device (PHY) or a network device does not have the capacity to support all available line speeds while operating in a single system-interface mode between MAC and PHY devices.

Abstract: A detection circuit of Universal Serial Bus (USB) is provided. A port of the USB has a first configuration channel pin and a second configuration channel pin, and the first and second configuration channel pins are disposed on opposite sides. The detection circuit includes a switch unit and a detection unit. The switch unit is coupled to the first and second configuration channel pins to sequentially provide a first voltage level of the first configuration channel pin and a second voltage level of the second configuration channel pin. The detection unit is coupled to the switch unit and correspondingly provides a state reference signal according to the first and second voltage levels.

Abstract: The disclosure relates to a method for communication in process automation between a sensor and a connecting element connectable to the sensor, wherein the sensor is configured for acquisition of a measured variable of the process automation and for transmission of a value that is dependent upon the measured variable value to the connecting element, wherein the connecting element for transmission of the value dependent upon the measured variable to a parent unit is configured via a first protocol. The method is characterized in that communication between the sensor and the connecting element takes place without the knowledge of the parent unit using a second protocol, the second protocol being independent of the first protocol.

Abstract: Various computer peripheral cards, devices, systems, methods, and software are provided herein. In one example, a storage card insertable into a host system includes a plurality of storage device connectors in a stacked arrangement, each configured to mate with associated storage devices and carry Peripheral Component Interconnect Express (PCIe) signaling for the associated storage devices. The storage card also includes a PCIe switch circuit configured to communicatively couple the PCIe signaling of the plurality of storage device connectors and PCIe signaling of a host connector of the storage card, where the PCIe switch circuit is configured to receive storage operations over the PCIe signaling of the host connector of the storage card and transfer the storage operations for delivery over the PCIe signaling of selected ones of the plurality of storage device connectors.

Abstract: A first port of a device is connected to a first switch port of a first virtual switch defined within a switch device and a second port of the device is connected to a second switch port of a second virtual switch defined within the switch device. A target world wide port name of a target port of a storage system connected to the second virtual switch is identified by the device. The first port of the device is registered, in a first registration procedure, with the first virtual switch based on the target world wide port name. Registration information relating to an initiator port of a server that is associated with the target port is received in a second registration procedure. An initiator world wide port name of the initiator port of the server is determined based on the registration information. A storage volume in the storage system that is associated with the initiator port is identified based on the initiator world wide port name of the initiator port.

Abstract: A method includes monitoring port login requests initiated by elements of a storage system, the storage system comprising interconnection cabling, constructing a connection graph corresponding to the port login requests, wherein each edge of the connection graph corresponds to a specific port login request and each vertex of the connection graph corresponds to a port within the storage system, and using the connection graph to evaluate the interconnection cabling of the storage system. A corresponding computer program product and computer system are also disclosed herein.

Abstract: An advanced extensible interface 4 (AXI4) topology is provided. The topology includes a main entity, parallel sub entities comprising a first sub entity having a first functionality and a second sub entity comprising parallel third sub entities having a second functionality, which is different from the first functionality, and a controllable element in series with the parallel third sub entities and an AXI4 interconnect element serially interposed between the main entity and the parallel sub entities. For a transaction issued by the main entity with an augmented address including first and second addresses, the first address is readable by the AXI4 interconnect element to select one of the first and second sub entities for transaction execution and the second address is readable by the controllable element to select one of the third sub entities for transaction execution.

Abstract: A protocol transparent retimer circuit monitors certain link layer control signals, detects far-end receiver parameters of the link partners, and detects attributes of the data signal on the link to determine the link status and operate the retimer in accordance with the determined link status. By combining and reducing host and device system states into a few retimer states, the retimer circuit is largely simplified and yet still serves its purpose. The retimer includes a controller that employs a state machine to interpret the monitored and detected signals to determine the link state and operate the retimer in an operating state corresponding to the determined link state. The approach enables the retimer to restore signal integrity and forward what ever it receives in both downstream and upstream directions of the link without frequency alteration.

Abstract: A system may include an interface circuit and a plurality of wire buses electrically coupled with one another. The interface circuit may include transmitters which change states of the plurality of wire buses to transmit a plurality of multilevel symbols. The transmitters may drive wire buses, coupled to each other, to a termination voltage level.

Abstract: An accessory controls power delivery from a host device to the accessory by receiving and rectifying a wireless signal into an electrical voltage that operates an electronic switch. The electronic switch sets a voltage state of an electrical connection to the host device that triggers the host device to begin providing power. The accessory may no longer receive power from the host device once the wireless signal stops. The host device may be the source of the wireless signal and may thereby control whether the accessory draws power by operation of the wireless signal. Alternatively, the accessory may include a controller that once powered on by the host device as a result of the rectification of the wireless signal, maintains the same or a different electronic switch in a closed state to maintain power delivery from the host device until the controller is triggered to allow the electronic switch to open.

Abstract: Embodiments of the present invention provide a data processing system and a data processing method. An MMIO address of a data request is obtained, where data stored in a PCIe storage device can be directly obtained from the MMIO address, and according to the MMIO address, a network adapter can directly read the data from the PCIe storage device of the data processing system, and transmit the data to a second data processing system, or directly write the data received from the second data processing system into the PCIe storage device. Therefore, the processing system can implement transmitting data directly from the PCIe storage device to the network adapter without using memory. During data transmission between the two data processing systems, a usage ratio of a resource, such as memory and a CPU, is reduced, and efficiency of data transmission is improved.

Abstract: A method and apparatus are for providing information to at least one other wireless communication device (WCD of a group of WCDs of which the WCD is a member, wherein the WCDs in the group have agreed to share computing resources. An assignment as one of a provider WCD and a recipient WCD is received in response to the information. At least one of two actions is taken. The first action is to operate, as a provider WCD, a power intensive portion of an application and providing the results to at least one recipient WCD of the group of WCDs. The second action is to operate, as a recipient WCD, to receive the results. Another method provides for a WCD to make a selection of the provider and recipient WCDs.

Abstract: Computing apparatus includes a central processing unit (CPU), which is configured to run concurrently multiple virtual machines, including at least first and second virtual machines. A peripheral component bus is connected to communicate with the CPU. Multiple peripheral devices are connected to communicate via the bus with the CPU and with others of the peripheral devices, including at least first and second peripheral devices that are each respectively partitioned into at least first and second functional entities, which are respectively assigned to serve the at least first and second virtual machines. Access control logic is configured to forward peer-to-peer communications initiated by the functional entities between the peripheral devices over the bus while inhibiting access in the peer-to-peer communications between the functional entities that are assigned to different ones of the virtual machines.

Abstract: A technology for controlling a reconfigurable processor is provided. A determination is made as to whether configuration information is provided from a configuration buffer in a preset process performed by the reconfigurable processor, based on address values of the configuration information that are stored in the configuration buffer. Therefore, access to a configuration memory is controlled to reduce power consumption.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for reducing processor latency through the use of dedicated cores. In one aspect, a method includes a multi-core processor having n cores, including, selecting k cores of the n cores of the multi-core processor to perform dedicated low-latency operations for the n-core processor, where k is less than n, m cores are unselected, and each core of the multi-core processor has a rated core capacity. The methods operate the selected k cores at less than the rated core capacity such that k cores are collectively underutilized by an underutilized capacity and operate one or more of the m cores at a capacity in excess of the rated core capacity such that the m cores operate at a collective capacity that exceeds a collective capacity of the rated core capacities of the m cores.

Abstract: A layout engine generates a visual layout tree for a visual description tree of a document whose content is to be rendered in one or more display areas. A visual description tree describes the content of a document along with formatting and logical arrangement the content. Visual description nodes of a visual description tree represent the organization of the constituent elements a document hierarchically. A visual layout tree defines the layout of a document within one or more display areas. Visual layout nodes of a visual layout tree represent the layout of the content of a document hierarchically. The layout engine receives as input a visual description tree and generates the corresponding visual layout tree. A rendering engine then inputs the visual layout tree and generates a graphics buffer containing the pixels representing the layout of the document as defined by the visual layout tree.

Abstract: A layout engine generates a visual layout tree for a visual description tree of a document whose content is to be rendered in one or more display areas. A visual description tree describes the content of a document along with formatting and logical arrangement the content. Visual description nodes of a visual description tree represent the organization of the constituent elements a document hierarchically. A visual layout tree defines the layout of a document within one or more display areas. Visual layout nodes of a visual layout tree represent the layout of the content of a document hierarchically. The layout engine receives as input a visual description tree and generates the corresponding visual layout tree. A rendering engine then inputs the visual layout tree and generates a graphics buffer containing the pixels representing the layout of the document as defined by the visual layout tree.

Abstract: A layout engine generates a visual layout tree for a visual description tree of a document whose content is to be rendered in one or more display areas. A visual description tree describes the content of a document along with formatting and logical arrangement the content. Visual description nodes of a visual description tree represent the organization of the constituent elements a document hierarchically. A visual layout tree defines the layout of a document within one or more display areas. Visual layout nodes of a visual layout tree represent the layout of the content of a document hierarchically. The layout engine receives as input a visual description tree and generates the corresponding visual layout tree. A rendering engine then inputs the visual layout tree and generates a graphics buffer containing the pixels representing the layout of the document as defined by the visual layout tree.

Abstract: Embodiments disclosed include a computer-automated system including a processing unit coupled to a memory element and having instructions encoded thereon, the instructions cause the system to: via a network, receive a document in a first format, and via an assessment engine, determine the first format of the received document. The assessment engine is also configured to determine if the determined first format can be converted to a second desired format for printing or display, and if the determined first format can be converted to the second desired format, a conversion engine is caused to convert the received document to the second desired format. If the determined first format cannot be converted to the second desired format, a network routing engine routes the document over the network to a cloud-based conversion engine.

Abstract: Some embodiments provide a method that displays, on a display screen, a document with several candidate cinemagraph presentations for display. The method selects, based on a set of at least two criteria, at least one candidate cinemagraph presentation for display. The method displays the selected cinemagraph presentation with the document.

Abstract: A management system displays a plurality of elements detected from an information system according to a horizontal relation view (HRV) format which is a multi-column display format, based on information of the plurality of detected elements. In the HRV format display, the plurality of columns correspond to a plurality of types, and include a key column which is a column serving as a key for aggregated display and an aggregation target column subjected to aggregated display according to the key column. The key column includes key objects which represent information on elements belonging to the corresponding type and which are arranged vertically. A lateral area of each of the key objects in the aggregation target column includes aggregation objects indicating aggregation information of elements related to an element represented by the key object, whereby the key objects and the related aggregation objects are arranged on the same row.

Abstract: A unified publishing platform (UPP) system is disclosed that may process electronic content to identify content data irrespective of the format of the electronic content. Content data may be separated from formatting to generate electronic content with different formats. The content data may be transformed to a format configured for display by one or more destinations. The UPP system may generate electronic content having a format using a template (e.g., a content workflow) selected by a user for displaying content. One or more attributes associated with the content data may be used to identify content data for placement in a layout using a template. The electronic content may be parsed to identify semantic data that identifies content data in the electronic content. The semantic data may be associated with one or more attributes. The attribute(s) may identify one or more content items in content data.