Abstract: A streams manager monitors data tuples processed by a streaming application represented by an operator graph. The streams manager includes a tuple breakpoint mechanism that allows defining a tuple breakpoint that fires when a tuple has been in the operator graph too long. What constitutes too long can be defined in a number of different ways, including a time limit, a processing limit for multiple operators, and a processing limit for an individual operator. When the tuple breakpoint fires, one or more operators in the operator graph are halted according to specified halt criteria. Information corresponding to the breakpoint that fired is then displayed. The tuple breakpoint mechanism thus provides a way to debug a streaming application that may have data tuples that stay in the operator graph too long.

Abstract: Systems and methods for debugging in a production environment are disclosed. An example method includes first receiving, by a processor, a user request from a development environment to execute a debugging program in a production environment, wherein the production environment is inaccessible by the development environment. The method then approves, by the processor, the execution of the debugging program in the production environment by seeking approval from at least one member from the production environment and the development environment. The method then in response to the approving, transmitting, by the processor, a communication to the production environment to cause the debugging program to be executed in the production environment.

Abstract: For generating an application program (15) from a plurality of application program modules (12), a computerized application platform (1) comprises an application configuration module (11) configured to receive from a user of a communication terminal instructions, for defining a selection of the application program modules (12), and to generate an application program (15) using the selected application program modules (12). The application platform (1) further comprises a plurality of device profiles (13) for different types of mobile communication devices. Each device profile (13) includes hardware characteristics of a different type of mobile communication device.

Abstract: Managing software performance debugging based on a distributed VM system is provided. In response to determining a debugging state of a software system running on a VM, a timing of a system clock of the VM is controlled. A data packet sent to the VM from another VM is intercepted, and an added system time and reference time that indicate when the packet was sent by the other VM is extracted from the packet. Based on the system and reference times, as well as a reference time of when the packet is intercepted, a timing at which the packet is expected to be received by the VM is calculated. The packet is forwarded to the VM as a function of a comparison of the timing at which the packet is expected to be received and a system time of the VM when the packet is intercepted.

Abstract: Mechanisms are provided for evaluating test cases for testing a software product based on a requirements change. The mechanisms analyze a test case corpus to identify a plurality of first relationships between elements of test cases in the test case corpus and generate a test case relationship model based on the identified plurality of first relationships. The mechanisms receive a proposed requirements change to change one or more requirements of the software product and then perform a search of the test case relationship model to identify test case relationships corresponding to the proposed requirements change. The mechanisms identify a subset of test cases affected by the proposed requirements change and generate an output specifying the identified subset of test cases.

Abstract: Mechanisms are provided for evaluating test cases for testing a software product based on a requirements change. The mechanisms analyze a test case corpus to identify a plurality of first relationships between elements of test cases in the test case corpus and generate a test case relationship model based on the identified plurality of first relationships. The mechanisms receive a proposed requirements change to change one or more requirements of the software product and then perform a search of the test case relationship model to identify test case relationships corresponding to the proposed requirements change. The mechanisms identify a subset of test cases affected by the proposed requirements change and generate an output specifying the identified subset of test cases.

Abstract: A system for automated testing of functionally complex systems, comprising a test manager, a test execution module, and a correlation engine, is disclosed. The test manager module causes tests to be executed by the test execution engine, and on detection of an anomalous test result, the test manager module at least causes additional testing to be performed and causes the correlation engine module to analyze the results of at least some of the additional testing in order to isolate at least one component exhibiting anomalous behavior.

Abstract: Methods, systems, and computer program products for parsing a binary, the parsing including identifying a section that includes a relocation entry; locating padding in a memory page of the section, the section including one or more memory pages; and inserting entropy into the padding.

Abstract: A storage device includes at least one nonvolatile memory device; and a memory controller configured to control the nonvolatile memory device, wherein the memory controller includes, at least one processor configured to control an overall operation of the memory controller; a buffer memory configured to store input/output data according to a control of the processor when an input/output request from an external device occurs; an error correction circuit configured to detect and correct an error of the input/output data; a garbage collector configured to selectively generate a first global garbage collection command in response to the input/output request and configured to perform a global garbage collection according to a second global garbage collection command received from the external device; and a storage interface configured to transmit the first global garbage collection command to another storage device.

Abstract: A log-structured data store may implement efficient garbage collection. Log records may be maintained in data blocks according to a log record sequence. Based, at least in part, on a log reclamation point, the log records may be evaluated to identify data blocks to reclaim that have log records in the log sequence prior to the log reclamation point. New versions of data pages updated by log records in the identified data blocks may be generated and stored in base page storage for the log structured data store. The identified data blocks may then be reclaimed for storing new data.

Abstract: Systems, methods, and computer programs are disclosed for scheduling tasks in a heterogeneous processor cluster architecture in a portable computing device. One embodiment is a system comprising a first processor cluster and a second processor cluster. The first processor cluster comprises a first shared cache, and the second processor cluster comprises a second shared cache. The system further comprises a controller in communication with the first and second processor clusters for performing task migration between the first and second processor clusters. The controller initiates execution of a task on a first processor in the first processor cluster. The controller monitors a processor workload for the first processor and a cache demand associated with the first shared cache while the task is running on the first processor in the first processor cluster. The controller migrates the task to the second processor cluster based on the processor workload and the cache demand.

Abstract: Embodiments of an invention for paging in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes evicting a first page from an enclave page cache.

Abstract: Execution of a transaction mode setting instruction causes a computer processor to be in an atomic write-only mode ignoring conflicts to certain read-sets of a transaction during transactional execution. Write-set conflicts may still cause a transactional abort. Absent any aborting, the transaction's execution may complete, by committing transactional stores to memory and updating architecture states.

Abstract: Performing efficient cache invalidation is disclosed, including: receiving an invalidation request to invalidate one or more invalidated cache entries at a cache storage: determining whether an invalidation pattern included in the invalidation request matches an invalidation pattern associated with an existing invalidation entry of an invalidation data structure; in the event that the invalidation pattern included in the invalidation request matches the invalidation pattern associated with the existing invalidation entry of the invalidation data structure, updating the existing invalidation entry with an invalidation timestamp included in the invalidation request, and in the event that the invalidation pattern included in the invalidation request does not match invalidation patterns associated with existing invalidation entries of the invalidation data structure, generating a new invalidation entry in the invalidation data structure with the invalidation pattern and the invalidation timestamp included in the

Abstract: A system and method are disclosed for multiple coherent caches supporting agents that use different, incompatible coherence models. Compatibility is implemented by translators that accept coherency requests and snoop responses from an agent and accept snoop requests and coherency responses from a coherence controller. The translators issue corresponding coherency requests and snoop responses to the coherence controller and issue corresponding coherency responses and snoop requests to the agent. Interaction between translators and the coherence controller accord with a generic coherence model, which may be a subset, superset, or partially inclusive of features of any native coherence model. A generic coherence protocol may include binary values for each of characteristics: valid or invalid, owned or non-owned, unique or shared, and clean or dirty.

Abstract: An operation processing apparatus includes: processor cores configured to perform an operation processing; cache memories each provided for the respective processor cores; and a controller configured to perform a coherency control between the cache memories, wherein, the controller, in the coherency control, in a case where one or more shared cache memories which share a target data block for a store request are present in the cache memories when the store request is received from a request cache memory included in the cache memories: controls one cache memory of the one or more shared cache memories such that the target data block is transferred to the request cache memory; receives an exclusive right acquisition response from another operation processing apparatus which manages a state of the target data block; and transmits the exclusive right acquisition response to the request cache memory.

Abstract: A cache management system and method allowing data stored in non-sequential storage blocks on a storage system to be retrieved to a cache memory in advance of a call for the data based on a defined event in a host. The system and method detects a defined event from the host. The defined event issues an event read sequence of read requests for data from non-sequential storage blocks of a storage system. The event data read sequence of read requests is recorded to create a pre-fetch list. The read requests in the event read sequence are then issued for the pre-fetch list associated with the defined event to store the requested data in the cache memory.

Abstract: An apparatus includes an operand cache for storing operands from a register file for use by execution circuitry. In some embodiments, eviction priority for the operand cache is based on the status of entries (e.g., whether dirty or clean) and the retention priority of entries. In some embodiments, flushes are handled differently based on their retention priority (e.g., low-priority entries may be pre-emptively flushed). In some embodiments, timing for cache clean operations is specified on a per-instruction basis.

Abstract: The present invention discloses a method for distributed transaction processing in a flash memory, including the following steps: S1. performing two-phase commit on a transaction, removing a state log record of a two-phase commit protocol, and internalizing as an operation on flash memory metadata in a transaction interface; S2. storing a temporary data object as a shadow version while performing the transaction, using a shadow mapping table to store the address of the shadow version or a state of a page, using page metadata to record transaction information, using a transaction metadata page to record a transaction state, and using a transaction state table to record an address of the transaction metadata page; and S3. when the coordinator or a participant fails, recovering the FTL mapping table, shadow mapping table, and transaction state table with the help of stored data and flash memory metadata.

Abstract: Embodiments of the present disclosure provide a method, a coalescing configuration engine, a coalescing configuration tool and a file system for a storage system, and comprises at least one initiator, each initiator accessing a corresponding storage space in the storage system via at least one virtual logic unit number LUN by executing in parallel a plurality of configuration operations, wherein each configuration operation is used to configure a mapping relationship between the at least one virtual LUN and the at least one initiator.

Abstract: A solid-state drive (“SSD”) containing a non-volatile memory (“NVM”), flash translation layer (“FTL”) table, cache node index table, and random access memory (“RAM”) configured to cache at least a portion of the FTL table is disclosed. The NVM is organized its memory space into memory blocks for data storage wherein each of the memory blocks is further divided into a set of physical pages addressable by corresponding physical page addresses (“PPAs”). The FTL table, also known as address mapping table, includes multiple entries used for NVM memory accessing. Each entry of the FTL table stores a PPA addressing a physical page in the NVM. The RAM caches or stores a portion of the FTL table based on a table caching mechanism. The cache node index table resided in the RAM or RAM cache contains indexing information associated with the FTL table.

Abstract: A cache memory and method of operating a cache memory are provided. The cache memory comprises cache storage that stores cache lines for a plurality of requesters and cache control circuitry that controls insertion of a cache line into the cache storage when a memory access request from one of the plurality of requesters misses in the cache memory. The cache memory further has cache occupancy estimation circuitry that holds a count of insertions of cache lines into the cache storage for each of the plurality of requesters over a defined period. The count of cache line insertions for each requester thus provides an estimation of the cache occupancy associated with each requester.

Abstract: An information processing apparatus including: a memory configured to store size information indicating each size of each data handled in a cache system, access frequency information indicating each access frequency of each data, and a memory space information indicating each size of each of a plurality of memory spaces, the plurality of memory space including one or more specified memory space including a first memory space that stores each data accessed at least twice in a specified period in the cache system, and a processor configured to: calculate one or more specified period in which each data remains in the one or more specified memory spaces respectively based on the size information, the access frequency information, and the memory space information, calculate a cache hit rate of each data in the cache system based on the one or more specified period, and output the cache hit rate.

Abstract: An arithmetic processing device includes clusters, each including cores and a last level cache shared by the cores; a home agent connected to the last level caches; and a memory controller connected to the home agent to control accesses to a memory. In response to a memory request from a first last level cache in a first cluster, the home agent issues a first replace request to the first last level cache to evict a first victim line in the first last level cache, the home agent issues a second replace request to a second last level cache in a second cluster in an idle state other than the first cluster to evict a second victim line in the second last level cache, and the second last level cache fills data of the first victim line to the second victim line.

Abstract: The present invention discloses a secure printed memory. It comprises a laser-programmable read-only memory (LP-ROM) which stores at least a key. The key is written during manufacturing and different LP-ROMs store different keys. The output of the secure printed memory is encrypted with the key stored in the LP-ROM and is different for different devices. Compromising a single device does not compromise other devices.

Abstract: A method of obfuscating a code is provided, wherein the method comprises performing a first level obfuscating technique on a code to generate a first obfuscated code, and performing a second level obfuscating technique on the first obfuscated code. In particular, the code may be a software code or a software module. Furthermore, the first level obfuscating technique and the second obfuscating may be different. In particular, the second level obfuscating technique may perform a deobfuscation.

Abstract: Memory systems may include a programmable bit control unit suitable for defining read-write properties to locations in a base address register (BAR) memory, a read-write switch suitable for receiving a memory access request, and identifying whether the memory access request is a read access or a write access, and an access control unit suitable for receiving the memory access request from the read-write switch when the memory access request is identified as a write access, determining a read-write property associated with the write access, and processing the write access to a location in the BAR memory with a defined read-write property that is the same as the determined read-write property associated with the write request.

Abstract: Memory systems may include a plurality of queues, a queue ready indicator suitable for grouping the plurality of queues into a predefined number of queue ranges, each queue range having associated with it a queue range ready signal, and setting a queue range ready signal to ready when each queue in the queue range associated with the queue range ready signal is ready for processing, and a queue process sequencer suitable for determining a queue range ready for processing based on the queue range ready signals, and processing a queue within the queue range determined to be ready for processing.

Abstract: A method and apparatus for accessing multiple storage devices from multiple hosts without use of remote direct memory access (RDMA) as disclosed herein include: providing a data store switch fabric enabling data communications between a data storage access system and a plurality of compute nodes, each compute node having integrated compute capabilities, data storage, and a network interface controller (Host NIC); providing a plurality of physical data storage devices; providing a host bus adapter (HBA) in data communication with the plurality of physical data storage devices and the plurality of compute nodes via the data store switch fabric, the HBA including at least one submission queue and a corresponding shadow queue; receiving an input/output (I/O) request from the plurality of compute nodes; including an element of the I/O request to the at least one submission queue; and including additional information related to the element of the at least one submission queue to the corresponding shadow queue.

Abstract: A switch includes a PCI bus. A line card processor is coupled to a line card memory system and includes a line card processor port connected to the PCI bus. A management processor is coupled to a management memory system and includes a management processor port connected to the PCI bus and associated with a register. The management processor retrieves an OS image and stores the OS image in the management memory system. The management processor then configures the register with a mapping between the management memory system and the line card memory system. The management processor then provides a write instruction to write the OS image to an address range included in the management memory system, and the management processor port converts the write instruction using the address mapping such that the OS image is written over the PCI bus to the line card memory system.

Abstract: This technology provides a method for fabricating an electronic device. A method for fabricating an electronic device including a variable resistance element, which includes a free layer having a variable magnetization direction; a pinned layer having a first non-variable magnetization direction, and including first ferromagnetic materials and a first spacer layer interposed between adjacent two first ferromagnetic materials among the first ferromagnetic materials; a tunnel barrier layer interposed between the free layer and the pinned layer; a magnetic correction layer having a second magnetization direction which is anti-parallel to the first magnetization direction; and a third spacer layer interposed between the magnetic correction layer and the pinned layer, and providing an anti-ferromagnetic exchange coupling between the magnetic correction layer and the pinned layer.

Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).

Abstract: A data processing system is disclosed that includes an in-line accelerator and a processor. The system can be extended to include an in-line accelerator and system of multi-level accelerators and a processor. The in-line accelerator receives the incoming data elements and begins processing. Upon premature termination of the execution, the in-line accelerator transfers the execution to a processor (or the next level accelerator in a multi-level acceleration system). Transfer of execution includes transferring of data and control. The processor (or the next accelerator) either continues the execution of the in-line accelerator from the bailout point or restarts the execution. The necessary data must be transferred to the processor (or the next accelerator) to complete the execution.

Abstract: A technology precluding attacks through peripheral devices thefts to a network of electronic appliances, by utilizing physical chip identification devices, is disclosed. The electronic appliances in the network are divided into the peripheral devices and the stem servers managing the registration information of the peripheral devices. The stem servers are under the central control with software, and the peripheral devices are controlled at device-level with the physical chip identification devices implemented in the chip. Thus, the security of the whole network is efficiently enhanced.

Abstract: An apparatus for initialization. The apparatus includes a management I/O device controller for managing initialization of a plurality of I/O devices coupled to a PCI-Express (PCIe) fabric. The management I/O device controller is configured for receiving a request to register a target interrupt register address of a first worker computing resource, wherein the target interrupt register address is associated with a first interrupt generated by a first I/O device coupled to the PCIe fabric. A mapping module of the management I/O device controller is configured for mapping the target interrupt register address to a mapped interrupt register address of a domain in which the first I/O device resides. A translating interrupt register table includes a plurality of mapped interrupt register addresses in the domain that is associated with a plurality of target interrupt register addresses of a plurality of worker computing resources.

Abstract: Latency reduction for direct memory access operations involving address translation is disclosed. Example methods disclosed herein to perform direct memory access (DMA) operations include initializing a ring of descriptors, the descriptors to index respective buffers for storing received data in a first memory. Such example methods also include causing prefetching of a first address translation associated with a second descriptor in the ring of descriptors to be performed after a first DMA operation is performed to store first received data in a first buffer indexed by a first descriptor in the ring of descriptors and before second received data to be stored in the first memory is received, the first address translation being associated with a second DMA operation for storing the second received data in the first memory.

Abstract: An interrupt management system for managing multiple interrupts includes a timer and an interrupt management sub-system. The interrupt management sub-system receives first and second interrupts, determines the first interrupt to be a real-time interrupt and the second interrupt to be a non-real-time interrupt, initializes the timer for a predetermined time period on reception of the first interrupt, and determines whether the second interrupt is either a maskable or non-maskable interrupt. The interrupt management sub-system transmits the first interrupt to an interrupt controller, en-queues the second interrupt during the predetermined time period, and transmits the second interrupt to the interrupt controller after the predetermined time period when the second interrupt is a maskable interrupt. The interrupt management sub-system transmits the second interrupt to the interrupt controller during the predetermined time period when the second interrupt is a non-maskable interrupt.

Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

Abstract: Systems and methods for reserving bandwidth in a USB hub are disclosed. The systems and methods may include receiving data from at least one downstream endpoint in a buffer, identifying a current capacity of the buffer, comparing the current capacity of the buffer to a buffer threshold, generating an output based at least on the comparison, based at least on the output, dynamically throttling at least one low-throughput endpoint, and allocating a predefined bandwidth to a USB device that has a predetermined bandwidth requirement by providing bandwidth to the USB device available from the throttle of the at least one low-throughput endpoints.

Abstract: A Micro-Electromechanical System (MEMS) recorder is provided. The MEMS recorder includes a scheduler, a serializer, a multiplexer, a transmit/receive switch, a master clock generator, a deserializer, a comparator array to determine whether to generate a signal to wake up a controller and/or a location module from a sleep mode, and a First-In-First-Out (FIFO) memory to output data to be stored and wake up the controller and/or the location module from the sleep mode if a signal to wake up the controller and/or the location module is received or if the FIFO memory is full, wherein the controller and/or the location module is awakened directly by the MEMS recorder or via the controller.

Abstract: An on-chip crossbar of a network switch comprising a central arbitration component configured to allocate packet data requests received from destination port groups to memory banks. The on-chip crossbar further comprises a Benes routing network comprising a forward network having a plurality of pipelined forward routing stages and a reverse network, wherein the Benes routing network retrieves the packet data from the memory banks coupled to input of the Benes routing network and route the packet data to the port groups coupled to output of the Benes routing network. The on-chip crossbar further comprises a plurality of stage routing control units each associated with one of the forward routing stages and configured to generate and provide a plurality of node control signals to control routing of the packet data through the forward routing stages to avoid contention between the packet data retrieved from different memory banks at the same time.

Abstract: The present invention relates to an electronic apparatus, which includes at least two node modules; a shared I/O module, having a first I/O interface connected with an external device and a second I/O interface electrically connected with the at least two node modules; and a switching module connecting the at least two node modules and the shared I/O module, used to cause the shared I/O module to communicate with one node module in the at least two node modules through the second I/O interface according to a selection signal when receiving the selection signal.

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

Abstract: The application provides a field programmable gate array (FPGA) and a communication method. At least one application specific integrated circuit based (ASIC-based) hard core is embedded in the FPGA. The ASIC-based hard core includes a high-speed exchange and interconnection unit and at least one station. Each station is connected to the high-speed exchange and interconnection unit. The station is configured to transmit data between each functional module in the FPGA and the ASIC-based hard core. The high-speed exchange and interconnection unit is configured to transmit data between the stations. In the FPGA provided by the application, an ASIC-based hard core is embedded, which can facilitate data exchange between each functional module and the ASIC-based hard core in proximity and reduce a time delay.

Abstract: A connection system includes a flippable cable connector (7) for connecting wires in a cable (5) to a complementary host connector located at a host device (4), the cable connector having a set of cable terminals and a set of duplicate cable terminals corresponding to the set of cable terminals, and configured to be located symmetrically to the set of cable terminals, so that the connector has 180° rotational symmetry. A particular cable terminal (9) is connected to a particular wire (11) in the cable but the corresponding duplicate cable terminal (12) is not connected to it. The cable connector is connectable to the host connector such that either the set of cable terminals or the set of duplicate cable terminals is connected to host terminals of the host connector. The system includes means (18) for determining an orientation of the cable connector relative to the host connector.

Abstract: A backboard applied in an electronic device includes a storage extended chip, a serial attached small computer system interface (SAS) hard disk drive (HDD) connector, a convertor, a first election unit, and a second election unit. An input pin of the convertor is coupled to a plurality of input pins of the SAS HDD, to receive the data signal from the SAS HDD connector. The first election unit is coupled to a first ground pin of the SAS HDD connector, enable pins of the convertor and the storage extended chip. The second election unit is coupled to the first ground pin of the SAS HDD connector and an enable pin of the storage extended chip. When the SAS HDD connector is coupled to a SATA HDD or a SAS HDD, the storage extended chip operates and receives a SAS signal from the SAS HDD connector.

Abstract: A data processing system is disclosed that includes machines having an in-line accelerator and a general purpose instruction-based general purpose instruction-based processor. In one example, a machine comprises storage to store data and an Input/output (I/O) processing unit coupled to the storage. The I/O processing unit includes an in-line accelerator that is configured for in-line stream processing of distributed multi stage dataflow based computations. For a first stage of operations, the in-line accelerator is configured to read data from the storage, to perform computations on the data, and to shuffle a result of the computations to generate a first set of shuffled data. The in-line accelerator performs the first stage of operations with buffer less computations.

Abstract: A system includes a management controller for managing a plurality of computing platforms. The management controller includes a processor, a physical network interface controller (NIC), a volatile memory, and a non-volatile memory storing computer executable code. The computer executable code, when executed at the processor, is configured to: provide a plurality of firmware instances, each corresponding to a respective one of the computing platforms; configure a plurality of virtual NICs (VNICs), each of the VNICs corresponding to a respective one of the firmware instances, wherein the VNICs share network resource provided by the physical NIC; and for each of the firmware instances, in response to a communication command to transmit data through the corresponding VNIC, transmit the data through the physical NIC.

Abstract: There is disclosed a single-wire Interface bus transceiver system comprising: an I2C master, a master transceiver, a signal wire, a slave transceiver and an I2C slave, wherein the master transceiver is adapted to encode master data SDA and master clock SCL received from I2C master using Manchester code, generate master single wire signal and transfer it to the slave transceiver through the signal wire, the master transceiver is also adapted to decode Manchester-encoded slave signal received from the signal wire and transfer the decoded slave data to I2C master; the slave transceiver is adapted to encode slave data received from I2C slave using Manchester code, generate slave single wire signal and transfer it to the master transceiver through the signal wire, the slave transceiver is also adapted to decode Manchester-encoded master signal received from the signal wire, generate the recovered master clock and transfer the decoded master data and recovered master clock to I2C slave.

Abstract: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.