Abstract: A resonation device includes a heat generation element as a heat generation portion which is disposed on a bottom plate of a package as a base substrate, a resonator element having connection portions and fixed to the heat generation element, and a protruding portion which overlaps a region different from the connection portions and of the resonator element when seen in plan view and is provided on the bottom plate. The area of the connection portions is larger than the area of the protruding portion when seen in plan view.

Abstract: A resonation device includes substrate, a resonation element that is attached to first main surface of substrate at first and second attachment portion, and heat-generating unit that is disposed on second main surface which is side opposite to first main surface so as to overlap with resonation element in a planar view. When an angle formed by line which connects center of resonation element and center of first attachment portion and virtual line which connects center of heat-generating unit and center of resonation element in a planar view is ?1 and an angle formed by a line which connects center of resonation element and center of second attachment portion and virtual line which connects center of heat-generating unit and center of resonation element in a planar view is ?2, conditions 0°<?1<90°, 0°<?2<90°, and 0°<|?1??2|<10° are satisfied.

Abstract: A method for producing an electronic component module prevents a space from collapsing. The method includes a step of preparing an electronic component including an element substrate, a drive device formed on a principal surface of the element substrate, and a protection device covering the drive device so as to form a space around the drive device; a step of fixing the electronic component on a common substrate such that a principal surface of the common substrate and another principal surface of the element substrate face each other; a step of fixing a reinforcing plate on the protection device of the electronic component; and a step of forming a resin layer on the principal surface of the common substrate such that the electronic component is contained therein.

Abstract: Apparatus and methods for control of the second order temperature dependence of the frequency of a mechanical resonating structure are described. The second order temperature dependence of frequency of the mechanical resonating structure may be non-linear. Control may be provided by doping of a semiconductor layer of the mechanical resonating structure.

Abstract: A pair of vibrating arm portions are disposed lined up in a second direction perpendicular to a first direction and are configured such that base end sides thereof in the first direction are fixed to a base portion. A pair of inclined surfaces are formed on both sides in the second direction on the base end side of the vibrating arm portion so that a width of the vibrating arm portion in the second direction is gradually widened from the distal end side to the base end side. A length of a region, having the pair of inclined surfaces formed therein, in the first direction is set to equal to or greater than 0.25 times and equal to or less than 0.5 times of a total length of the vibrating arm portion from the base end to the distal end.

Abstract: An electroacoustic transducer having an alternative finger structure is provided. The number of fingers of a cell of length A is divisible by four. The electrode fingers of the cell are divided into four groups. The distance (?2) between the second group and the third group is less than the distance (?1) between the first group and the second group and less than the distance (?3) between the third group and the fourth group.

Abstract: A dynamically tunable transconductor includes a voltage-to-current converter stage for generating a current signal based on a voltage signal; and a current scaling stage for scaling the current signal by a scaling factor to achieve a particular transconductance. Current scaling stage includes a coarse tune mechanism having an associated coarse tune step and a fine tune mechanism having an associated fine tune step, where the scaling factor is a ratio of the coarse tune step to the fine tune step. A delta-sigma modulator can implement the transconductor to generate loop filter coefficients by dynamically tuning the transconductance to achieve a particular resistance.

Abstract: Provided herein are high frequency signal attenuators. In certain configurations, an integrated circuit includes a signal conductor that carries a radio frequency (RF) signal, a shield conductor routed with the signal conductor and biased with a ground voltage, and an attenuation circuit that provides a controllable amount of attenuation to the RF signal. The attenuation circuit includes a shunt circuit electrically connected between a signal tapping position of the signal conductor and a shield tapping position of the shield conductor. Connecting the shunt circuit in this manner enhances high frequency performance by reducing a length of an effective loop from the signal conductor to an adjacent portion of the shield conductor.

Abstract: A fingerprint sensing circuit, system, and method is disclosed. The fingerprint sensor maybe include a plurality of inputs coupled to a plurality of fingerprint sensing electrodes and to an analog front end. The analog front end may be configured to generate at least one digital value in response to a capacitance of at least one of the plurality of fingerprint sensing electrodes. Additionally, the analog front end may include a quadrature demodulation circuit to generate at least one demodulated value for processing by a channel engine. The channel engine may generate a capacitance result value that is based, in part, on the demodulated value and is stored in a memory.

Abstract: A capacitor structure is described. The capacitor structure includes a substrate, a plurality of source/drain regions, a first plurality gates, and a second plurality of gates. The plurality of source/drain regions is formed in the substrate. The first and second plurality of gates is formed above the substrate. Each gate of the first and second plurality of gates has a gate width. The gate widths are configured to be less than an active area width and each gate of the first and second plurality of gates is formed between a pair of the source/drain regions of the plurality of source/drain regions. And, each gate of the first plurality of gates is configured to be in line with a corresponding gate of the second plurality of gates to form a head-to-head gate configuration.

Abstract: Leakage current in a standby mode of a level shifter capable of operating with low voltage is reduced. Provided is a level shifter circuit in which an n-channel silicon transistor and an oxide semiconductor transistor are provide in series between an output signal line and a low potential power supply line. The potential of a gate electrode of the oxide semiconductor transistor is raised to a potential higher than input signal voltage by capacitive coupling, so that on-state current of the oxide semiconductor transistor is increased.

Abstract: A driver circuit for receiving input data and generating an output signal to a termination element is provided, wherein the input data has a first bit and second bit, and the driver circuit includes: a pair of differential output terminals for outputting the output signal, wherein the pair of differential output terminals has a first output terminal and a second output terminal; at least one current mode drive unit, coupled to the pair of differential output terminals, for outputting a current from one of the first output terminal and the second output terminal, and receiving the current from the other of the first output terminal and the second output terminal according to the first bit; and at least one voltage mode drive unit, coupled to the pair of differential output terminals, for providing voltages to the first output terminal and the second output terminal according to the second bit.

Abstract: A receiving circuit may include a wide range receiving circuit and a parallelizing circuit. The wide range receiving circuit may amplify an input signal which swings within a first range and generate an intermediate output signal which swings within a second range wider than the first range. The parallelizing circuit may compare the intermediate output signal with a second reference voltage and amplify the intermediate output signal accordingly and generate output signals which swing within a third range wider than the second range.

Abstract: The invention relates to a multi-phase oscillator for generating multiple phase-shifted oscillator signals including: a ring oscillator having a number of concatenated oscillator delay cells which are interconnected to generate an oscillator signal, wherein phase-shifted oscillator signals are generated between the oscillator delay cells; a phase-blending unit configured to receive two phase-shifted oscillator signals and to generate a mid-phase oscillator signal whose phase shift is between the shifts of the two phase-shifted oscillator signals; and an interpolator delay line having a number of concatenated interpolator delay cells to generate further phase-shifted oscillator signals.

Abstract: A flip-flop (10) is disclosed comprising a slave latch (30) and a master latch (20). Each of the slave and master latch comprise a pair of cross-coupled logic gates (21, 22, 31, 32). A cross coupling connection of the slave or master latch (30, 20) comprises a resistive element (8, 9, 11, 12) arranged to reduce the sensitivity of the flip-flop (10) to a current injection.

Abstract: An apparatus is disclosed that includes a clock distribution circuit configured to shift a first clock signal in the first voltage domain to a second voltage domain to produce the second clock signal. The second voltage domain extends outside of the first voltage domain. A set of flip-flops operating in the first voltage domain, each including a master latch, a slave latch, and a clock node is coupled to receive the second clock signal. Each flip-flop includes a master pass transistor configured to pass a value from an input of the flip-flop to an input of the master latch when the second clock node is set to a first value. Each flip-flop also includes a master pass transistor configured to pass the value from an output of the master latch to an input of the slave latch when the second clock node is set to a second value.

Abstract: An optical flip-flop circuit that includes an optical thyristor configured to receive a digital optical signal input and produce a digital signal output based on the ON/OFF state of the digital optical signal input. The optical flip-flop circuit further includes control circuitry operably coupled to the terminals of the optical thyristor. The control circuitry is configured to control switching operation of the optical thyristor in response to the level of a digital electrical signal input.

Abstract: A magnetic waveform generator circuit includes a first switch coupled to a first rectifier element at a first node, a first capacitor coupled, at a second node to the first switch, and to a fourth node, a second capacitor coupled, at a third node to the first rectifier element, and to the fourth node, and an inductor coupled between the first and the fourth nodes. The first switch is operable to be in an ON state during a first time period and in an off state during a second time period. The first switch and the first rectifier element are configured to enable the inductor to generate, during the first and the second time periods, a magnetic field having a waveform resembling a positive half-cycle of a triangular waveform.

Abstract: According to an embodiment, a method of generating a clock pulse includes receiving a leading edge at a clock input at a time when an enable signal is active, generating an edge at a clock output based on the received leading edge at the clock input, latching a logic value corresponding to the edge at the clock output, preventing changes at the clock input from affecting the latched logic value after the logic value is latched, resetting the latched logic value after a first delay time, and maintaining the reset logic value until a second edge is received at the clock input. The second edge at the clock input matches the leading edge at the clock input.

Abstract: An adaptive UWB radar front-end that can a) automatically tune the pulse width for target type and depth; b) automatically sweep specific area by controlling the timing (delay); and, c) for each steering direction, it can automatically adjusts the power distribution for improving radiation pattern and thus improving signal quality for clutter free imaging.

Abstract: An apparatus includes a current-to-voltage converter configured to convert first and second currents into first and second input voltages and provide the first and second input voltages to first and second nodes, respectively, and a current difference determination circuit configured to determine a difference between the first and second currents based on a difference between the first and second input voltages. A method includes converting first and second currents into first and second input voltages to output the first and second input voltages to first and second nodes, respectively, and determining a difference between the first and second currents based on a difference between the first and second input voltages.

Abstract: A glitch filter circuit has a filter/delay part that always operates on rising or falling pulses for both rising edges and falling edges of the input signal. In this way, the filter delay can be made symmetrical and the circuit will have no duty cycle distortion. The rise and fall delays will track each other when there are PVT (Process, Voltage and Temperature) variations.

Abstract: Disclosed herein is a device includes a duty correction circuit adjusting a duty ratio of a first clock signal based on a duty control signal to generate a second clock signal; a delay line delaying the second clock signal to generate a third clock signal; and a duty cycle detector detecting the duty ratio of the second clock signal to generate the duty control signal in a first mode, and detecting the duty ratio of the third clock signal to generate the duty control signal in a second mode.

Abstract: An input buffer circuit comprising: a first current source; a first differential control circuit, configured to generate a first bias voltage at the first couple terminal according to the input signals, and configured to generate first control signals according to the input signals; a second current source; a second differential control circuit, configured to generate a second bias voltage at the second couple terminal according to the input signals, and configured to generate second control signals according to the input signals; a third current source, configured to provide a first current according to the second bias voltage; a first differential output circuit, configured to receive the first control signals to generate output signals; a fourth current source, configured to drain a second current according to the first bias voltage; and a second differential output circuit, configured to receive the second control signals to generate the output signal.

Abstract: A voltage converter having a bootstrap refresh control circuit and a method for controlling the voltage converter. The bootstrap refresh control circuit monitors a bootstrap voltage across a bootstrap capacitor and provides a high side driving signal to a high side switch of the voltage converter. The bootstrap refresh control circuit also controls the charging of the bootstrap capacitor through decreasing the output voltage of the voltage converter once the bootstrap voltage is dropped to be smaller than a bootstrap refresh threshold. When the output voltage of the voltage converter is decreased enough, the bootstrap refresh control circuit switches the high side switch and the low side switch on and off to refresh the bootstrap voltage.

Abstract: A gate-driver device for operating a field-effect-transistor (FET) includes a pull-down-block and a pull-up-block resistant to or protected from short circuits of the gate drive signal output by the device. The pull-down-block is operable to drive a gate of a FET to a low-voltage. The pull-up-block includes a resistive-pull-up operable to an ON-state and an OFF-state to switchably couple the gate to the high-voltage via an upper-resistive-element, and a current-pull-up arranged in parallel with the resistive-pull-up. The current-pull-up is operable to an ON-state and an OFF-state to control a current-source applied to the gate. When the pull-up-block drives the gate to the high-voltage, the resistive-pull-up and the current-pull-up operates from the OFF-state to the ON-state. A turn-on-interval after the resistive-pull-up operates from the OFF-state to the ON-state the resistive-pull-up operates to the OFF-state while the current-pull-up is maintained in the ON-state.

Abstract: A driver circuit for receiving input data and generating an output signal to a termination element is disclosed, wherein the input data has a first bit and second bit, and the driver circuit includes: a pair of differential output terminals, arranged for outputting the output signal, wherein the pair of differential output terminals has a first output terminal and a second output terminal; a current mode drive unit, coupled to the pair of differential output terminals, for outputting a current from one of the first output terminal and the second output terminal, and receiving the current from the other of the first output terminal and the second output terminal according to the first bit; and a voltage mode drive unit, coupled to the pair of differential output terminals, for providing voltages to the first output terminal and the second output terminal according to at least the second bit.

Abstract: Systems and methods for controlling current or mitigating electromagnetic or radiation interference effects using structures configured to cooperatively control a common semi-conductive channel region (SCR). One embodiment includes providing a metal oxide semiconductor field effect transistor (MOSFET) section formed with an exemplary SCR and two junction field effect transistor (JFET) gates on opposing sides of the MOSFET's SCR such that operation of the JFET modulates or controls current through the MOSFET's. With two JFET gate terminals to modulate various embodiments' signal(s), an improved mixer, demodulator, and gain control element in, e.g., analog circuits can be realized. Additionally, a direct current (DC)-biased terminal of one embodiment decreases cross-talk with other devices. A lens structure can also be incorporated into MOSFET structures to further adjust operation of the MOSFET.

Abstract: A drive circuit includes: a constant current circuit configured to supply a constant current to a gate of the voltage-controlled device, and to turn on the voltage-controlled device; a discharge circuit configured to supply a discharge current between the gate and an emitter of the voltage-controlled device, and to turn off the voltage-controlled device; a switch circuit configured to operate one of the constant current circuit or the discharge circuit depending on a drive signal, and to turn on or turn off the voltage-controlled device; a current instruction value generation circuit configured to generate and output at least a current instruction value that sets an output current from the constant current circuit; and a current control circuit configured to control the output current from the constant current circuit based on the current instruction value generated by the current instruction value generation circuit.

Abstract: A comparator sense input is disconnected from a current sense resistor for the duration of a switching transition in an adjacent channel(s). Instead, the sense input receives a signal of the magnitude and the slew rate sampled prior to the transition.

Abstract: Radio frequency (RF) switches and devices provide improved switching performance. An RF switch includes at least one field-effect transistor (FET) disposed between a first node and a second node, each of the at least one FET having a respective source, drain, gate, and body, and a compensation circuit connected to the respective drain of the at least one FET that compensates a non-linearity effect generated by the at least one FET.

Abstract: An integrated circuit includes: an inductor; a switching element connected to the inductor in series; an oscillator, of which an oscillation frequency is variable; a control unit, which controls the oscillation frequency of the oscillator based on a signal according to an output voltage of a switching power-supply device; a drive signal generating unit, which generates a drive signal used for controlling the switching element based on an output of the oscillator; a drive circuit, which drives the switching element based on the drive signal generated by the drive signal generating unit; and an on-period intermittent control unit, which intermittently performs on-period extension control in which an on-period of the switching element is set to be longer than an on-period based on the drive signal in a state where the oscillation frequency is controlled not to be fixed by the control unit.

Abstract: A drive control device for two semiconductor elements having a transistor structure and a diode structure with a common energization electrode includes: a current detection device outputting a current detection signal of the semiconductor elements; and a first control device outputting a gate drive signal from when a first time period has elapsed from a starting time to when a second time period has elapsed from the starting time, at which an off-command signal is input after it is determined that a current flows through the semiconductor elements in a forward direction of the diode structure during a time period for which an on-command signal is input to the semiconductor elements. The first and the second time periods are preliminary set not to generate an arm short-circuit between two semiconductor elements.

Abstract: A semiconductor device includes a high breakdown voltage, high Gm first transistor and a low breakdown voltage, low Gm second transistor connected in series between first and second nodes, and a low breakdown voltage, high Gm third transistor connected to the second transistor in parallel. When the second transistor is turned on, the first transistor turns on, and furthermore, when the third transistor is turned on, an electrically conducting state is established between the first and second nodes. The second, low breakdown voltage transistor is turned on to turn on the first, high breakdown voltage transistor, and a turn-on time with only limited variation can be achieved.

Abstract: A start-up method for a self-powered gate drive circuit driving a power transistor gate. The method comprises charging, with a single-supply voltage, a first supply capacitor of a first gate drive circuit; switching on a first power transistor by applying a current supplied by a discharge of the first supply capacitor of the first gate drive circuit to the gate of the first power transistor; charging a second supply capacitor of the first gate drive circuit using an output signal from the first power transistor; and re-charging the first supply capacitor by applying a current supplied by a discharge of the second supply capacitor to the first capacitor.

Abstract: A gate drive circuit creates a bipolar voltage to a gate of an IGB power transistor, and compensates for Miller currents of the IGB power transistor. The compensating is performed by a switching element connected in series with a capacitor between the gate (X4) and a supply voltage.

Abstract: An embodiment according to the present invention discloses a gate driving circuit and display panel using the same. The circuit includes a driving unit, a control unit, a first negative voltage input, a driving voltage input and a control signal input. Three inputting ends of the driving unit are connected to the different inputs when the status of the driving unit is changed according to the sequence of first cut-off st atus/first driving status/second driving status/second cutoff status. The benefit of the solution is to prevent circuit invalid due to the drain current generating when the oxide thin film transistor works in the depletion mode.

Abstract: The present application is directed to drive arrangement for semiconductor switches and in particular to a method of driving the gate of a switch with pulses corresponding to turn-on and turn-off commands through separate turn-on and turn-off transformers. The application provides a fail safe reset feature, a more efficient turn-on circuit and an energy recovery circuit for recovering energy from the gate upon turn-off. The application also provides a novel arrangement for assembling multiple pulse transformers on a circuit board.

Abstract: In a semiconductor module, second semiconductor chips (e.g., diodes) are disposed closer to a laminated substrate than first semiconductor chips (MOSFETs). When a control signal supplied to gate electrodes of the first semiconductor chips (MOSFETs) is off, an electric current produced by a voltage from source terminals to a drain board mainly flows through the second semiconductor chips.

Abstract: A touch panel includes a first conductive film having separate areas, each of which has a strip shape with a length direction thereof extending in a first direction, a second conductive film having separate areas, each of which has a strip shape with a length direction thereof extending in a second direction substantially perpendicular to the first direction, and a third conductive film, wherein the separate areas of the first conductive film are arranged side by side in the second direction, and the separate areas of the second conductive film are arranged side by side in the first direction, wherein position detection based on a capacitive method is performed by using the first conductive film and the second conductive film, and wherein a potential of a position of contact between the second conductive film and the third conductive film is detected to detect the position of the contact.

Abstract: An input apparatus capable of preventing a user's unintentional input by notifying the user of a change in a pressure load is provided. The input apparatus has a touch face configured to receive a touch operation, a load detection unit configured to detect a pressure load of the touch operation to the touch panel, a vibration unit configured to vibrate the touch face, and a control unit, when the load detection unit detects a pressure load satisfying a standard load to receive an input, configured to perform a control to receive the input by the touch operation. When the load detection unit detects a pressure load satisfying a standard load, lower than the standard load to receive an input, the control unit controls the vibration unit to vibrate.

Abstract: A buffer circuit may include an amplification unit and an active load unit. The amplification unit is electrically coupled to an output node and configured to sense and amplify first and second signals. The active load unit is configured to form a peak of a signal outputted from the output node when the signal transitions.

Abstract: Apparatus for identifying stable physically unclonable function (PUF) cells includes an array of PUF cells, a bias control circuit, and a selector circuit. The bias control circuit has a plurality of bias control lines that apply one or more bias control signals to each PUF cell in the array of PUF cells. The selector circuit selects a subset of the PUF cells in the array of PUF cells based on whether outputs of the PUF cells in the array of PUF cells change in response to application of the bias control signals. A corresponding method is also disclosed.

Abstract: An operation mode setting circuit of a semiconductor apparatus includes a mode register set configured to update an operation mode information generated internally at the semiconductor apparatus based on preliminary information data in response to a preliminary information setting signal and a preliminary information providing block configured to provide the preliminary information data selected from a plurality of pre-stored preliminary information data to the mode register setting response to the preliminary information setting signal, the selected preliminary information data corresponding to a detected operation parameter detected in response to the preliminary information setting signal.

Abstract: Provided are a reference voltage training device and a method thereof. The reference voltage training device includes a comparator configured to compare a toggle signal with a reference voltage and output a comparison signal, a duty cycle detector configured to check a duty ratio of the comparison signal, and a reference voltage level changing unit configured to fix the reference voltage when the duty ratio meets a predetermined condition and to change a level of the reference voltage when the duty ratio does not meet the predetermined condition. The comparator outputs a changed comparison signal using the changed reference voltage.

Abstract: Clusters of logical elements are interconnected by a switching fabric. Each cluster contains processing elements, storage elements, and switching elements. A circular buffer within a cluster contains multiple switching instructions to control the flow of data throughout the switching fabric. The circular buffer provides a pipelined execution of switching instructions. Each cluster contains multiple processing elements, and each cluster further comprises an additional circular buffer for each processing element. Logical operations are controlled by the circular buffers.

Abstract: An integrated circuit (IC) includes a plurality of pads adapted to send or receive signals, and a plurality of mixed signal interface blocks, each of which is coupled to a corresponding pad in the plurality of pads. Furthermore, each mixed signal interface block in the plurality of mixed signal interface blocks is adapted to be configurable to provide selected functionality independently of the other mixed signal interface blocks.

Abstract: A semiconductor device includes a 2-input NAND decoder and an inverter that have six MOS transistors arranged in a line. The MOS transistors of the decoder are formed in a planar silicon layer disposed on a substrate and each have a structure in which a drain, a gate, and a source are arranged vertically and the gate surrounds a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicon layer on a surface of the planar silicon layer.

Abstract: A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDD?V thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDD+V thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD.

Abstract: A carry-skip one-bit full adder and a field programmable gate array device, the full adder includes: a first multiplexer, a second multiplexer, and an adder, the first multiplexer includes a first addend input end and a first constant input end configured to input a first constant to the first multiplexer; the second multiplexer includes a second addend input end and a second constant input end configured to input a second constant to the second multiplexer; when the first addend input end is not used for input of a first addend, and/or when the second addend input end is not used for input of a second addend, the first multiplexer selects to output the first constant input, and the second multiplexer selects to output the second constant input.