Abstract: Embodiments of the invention relate to a metal configurable hybrid memory for use in integrated circuit designs for implementation in structured ASIC or similar platforms utilizing a base cell or standard cell. In accordance with certain aspects, a hybrid memory according to embodiments of the invention utilizes a fixed custom memory core and a customizable peripheral set of base cells. In accordance with these and further aspects, the hybrid memory can be specified using a macro, in which certain memory features (e.g. ECC, etc.) are implemented using the customizable peripheral set of base cells, and which may be selected or omitted from the design by the user. This enables the overall logic use for the memory to be optimized for a user's particular design.

Abstract: Techniques and mechanisms disclosed herein provide a partial reconfiguration bitstream for a region of configurable logic of a programmable logic device over a communications interface such as the Peripheral Component Interconnect Express (PCIe) protocol.

Abstract: A system-on-chip including circuit instances, a selector module, a circuit instance module, and a comparing module. The circuit instances have respectively nodes. The circuit instances are designed to provide nominally a same value at each of the nodes. The selector module is configured to generate a selection signal. The circuit instance module is configured to (i) monitor states of the nodes, and (ii) based on the selection signal, select (a) two or more of the states of the nodes, or (b) two or more parameter values generated based on the two or more of the states of the nodes. The comparing module is configured to: compare (i) the two or more of the states of the nodes, or (ii) the two or more parameter values; and based on the comparison, output a bit of (i) a silicon fingerprint of the system-on-chip, or (ii) a unique response code of the system-on-chip.

Abstract: A frequency divider includes a multiplexer having a first input terminal coupled to receive a first value M and a second input terminal for receiving a second value that is M+LSB, the multiplexer is configured to alternately output the first value M and the second value. The frequency divider includes a multi-modulus divider coupled to the multiplexer for receiving the output of the multiplexer, the multi-modulus divider operable to alternately generate an output pulse at M input clock cycles and at M+LSB clock cycles. A divide-by-two counter having an input coupled to the output of the multi-modulus divider, is operable to divide the output of the multi-modulus divider to generate a divided clock signal having a frequency of N, where N is equal to 2M+LSB. Duty cycle correction logic is coupled to the output of the divide-by-two counter and is configured to correct the duty cycle of the divided clock signal to a fifty percent duty cycle when N is odd.

Abstract: An ultra-low power clock source includes a compensated oscillator and an uncompensated oscillator coupled by a comparator circuit. In an example, the compensated oscillator is more stable than the uncompensated oscillator with respect to changes in one or more of temperature, voltage, age, or other environmental parameters. The uncompensated oscillator includes a configuration input configured to adjust an operating characteristic of the uncompensated oscillator. In an example, the uncompensated oscillator is adjusted using information from the comparator circuit about a comparison of output signals from the compensated oscillator and the uncompensated oscillator.

Abstract: A semiconductor device includes: a circuit configured to operate according to a clock; a temperature sensor configured to detect a temperature of the circuit; and a controller configured to control a frequency of the clock based on a temporal difference of power consumption of the circuit when the temperature detected by the temperature sensor exceeds a predetermined value.

Abstract: An electronic apparatus including an oscillator, a sampler, a phase detector, a phase rotator and a loop filter is provided. The oscillator generates a reference and an auxiliary clock signal offset by 90 degrees. The sampler samples an input data signal at each transition edges to generate primary sampled signals. The phase detector determines a phase difference of a data transition of the input data signal relative to a data-sampling edge. The phase rotator rotates the primary sampled signals and the reference clock signal according to the phase difference. The loop filter generates a control voltage to control the oscillator to vary phases of the reference clock signal and the auxiliary clock signal according to phase difference of the data transition relative to the rotated reference clock signal.

Abstract: A regulation circuit of a semiconductor apparatus includes a control block configured to generate control signals in response to a reference clock signal and a feedback clock signal; and a noise compensation block configured to compensate for a variation in a level of power in response to the control signals.

Abstract: A circuit device includes a drive circuit that drives a physical quantity transducer, an FLL circuit that includes a frequency comparator and an oscillator, and generates a clock signal with a signal from the drive circuit as a reference clock signal, and a detection circuit that includes a circuit operated based on the clock signal, and performs detection processing on a detection signal from the physical quantity transducer.

Abstract: A device includes a lock detect circuit that is structured and arranged to: convert a reference clock to a reference triangle wave; convert a feedback clock to a feedback triangle wave; determine whether the feedback triangle wave is within a tolerance margin that is defined relative to the reference triangle wave; and generate a determiner output that is a first value when the feedback triangle wave is not within the tolerance margin, and a second value when the feedback triangle wave is within the tolerance margin.

Abstract: In some embodiments, an integrated circuit may include a radio frequency synthesizer configured to provide a local oscillator (LO) signal at a selected frequency related to a frequency of interest. The integrated circuit may also include a re-clocking circuit having a first input to receive a clock signal having a first frequency, a second input to receive a local timing signal related to the LO signal, and an output. The re-clocking circuit may be configured to provide a local timing output signal that is a frequency adjusted version of the clock signal based upon the local re-clocking signal. The integrated circuit further may include a digital circuit including an input to receive the local timing output signal as a digital clock signal in a receive mode.

Abstract: An apparatus for PLL bandwidth expansion including a compensation filter and a phase locked loop, where the compensation filter is programmed with a compensation function derived based on programmable coefficients and parameters of a transmitting device, a frequency response of the phase locked loop, and a wanted frequency response.

Abstract: A radio frequency (RF) signal can be produced with an RF frequency that is responsive to a frequency reference (FREF) clock. An inductive-capacitive (LC) tank oscillator circuit can generate the RF signal. A digital to time converter (DTC) circuit can operate, for a first edge of the FREF clock, in a baseline mode that has a first delay, and for a subsequent edge of the FREF clock, in a delay mode that introduces a second delay value to the FREF clock. A controller circuit can enable the LC-tank oscillator circuit in response to a first edge of the FREF clock and to set or increase the second delay value of the delay mode as a function of the frequency of the RF signal. A phase detector circuit can detect, for the subsequent edge of the FREF clock, a phase difference between the FREF clock and the RF signal.

Abstract: A noise shaping circuit according to an example includes a forward signal path configured to generate an output signal based on an input signal, a feedback signal path configured to feed back a feedback signal based on the output signal to the forward signal path, and a dither generator configured to generate a dither signal and to couple the dither signal into the forward signal path to modify the input signal and into the feedback signal path. Employing a noise shaping circuit according to an example may improve an overall noise performance.

Abstract: A digital-to-analog converter which improves dynamic range by apportioning a least significant bits portion of an incoming digital signal to a low-path circuit and a most significant bits portion of the incoming digital signal to a high-path circuit. The low-path circuit has a low-path digital-to-analog converter, which feeds a low-path resistive element, which feeds an output node. The high-path circuit has a high-path digital-to-analog converter, which feeds a high-path resistive element, which feeds an output node. The output node is a simple electrical connection of the outputs of the low-path and high-path resistive elements. The system can further improve dynamic range by providing a high-path amplifier with control element(s) which reduce or eliminate high-path noise from the output node. Further dynamic range improvement is realized when the high-path control system takes advantage of the effects of psychoacoustic masking.

Abstract: A micro-coded sequencer controls complex conversion sequences independent of a central processing unit (CPU). Micro-coding provides for easily adding new process steps and/or updating existing process steps. Such a programmable sequencer in combination with an analog-to-digital conversion module such as an analog-to-digital converter (ADC) or a charge time measurement unit (CTMU), and digital processing circuits may be configured to work independently of the CPU in combination with the micro-coded sequencer. Thereby providing self-sufficient operation in low power modes when the CPU and other high power modules are in a low power sleep mode. Such a peripheral can execute data collection and processing thereof, then wake the CPU only when needed, thereby saving power. Furthermore, this peripheral does not require CPU processing so that time critical applications that do require control by the CPU can operate more efficiently and with less operating overhead burden.

Abstract: A charge sharing circuit for generating a calibration voltage. The circuit comprises a calibration capacitor for providing at an upper terminal of the calibration capacitor the calibration voltage. The circuit further comprises a series connection of a plurality of N switches, wherein N is an integer>2, and a plurality of at least N?1 switching capacitors. Each switching capacitor is coupled to one connecting node connecting two of the N switches. One side of the series connection of the plurality of N switches is coupled to the upper terminal of the calibration capacitor and the other side of the series connection of the N switches is coupled to a fixed voltage. The circuit is configured to transmit at least two clock signals to selectively drive at least two distinct subsets of the switches. There is further provided a corresponding method and a corresponding design structure.

Abstract: A successive approximation type AD converter includes a charge redistribution type DA conversion circuit, a comparator, and a control circuit. The charge redistribution type DA conversion circuit is configured such that each of k unit elements connects a switch and a unit capacitance in series and includes a unit capacitor array that is connected to a common output line in parallel and a selector that selects one voltage supplied to one input terminal, through m voltage supply lines, among at least three input terminals of switches included in j unit elements which are the targets for dynamic element matching (DEM) in k unit elements based on the DEM.

Abstract: The present invention provides a small-sized inexpensive solid-state imaging apparatus. A D/A converter included in a successive comparison type A/D converter of the solid-state imaging apparatus includes a multiplexer which selects any of reference voltages VR0 to VR16 and sets it as an analog reference signal when coarse A/D conversion is performed, and which selects reference voltages VR (n?1) to VR (n+2) of the reference voltages VR0 to VR16 when fine A/D conversion is performed, and a capacitor array which generates an analog reference signal, based on the reference voltages VR (n?1) to VR (n+2) when the fine A/D conversion is performed. It is thus possible to reduce settling errors in reference voltage without using redundant capacitors.

Abstract: Disclosed herein are embodiments of a precharge sample-and-hold circuit. The circuit has an input terminal, a reference voltage terminal and an output terminal. Further, the circuit has a sampling capacitance coupled between the input terminal and the reference voltage terminal and configured to provide the sample voltage when said sample-and-hold circuit is in a holding mode and a cancellation capacitance. Implementations of a precharge sample-and-hold circuit and of methods to operate a precharge sample-and-hold circuit in an analog/digital converter are also disclosed.

Abstract: Provided is a circuit which can correct an output state in real time and reduce influences of distortion/noise components generated by a delay device. A signal modulation circuit includes a subtractor, an integrator, a phase inverting circuit, a DFF for while inserting a zero level at timing synchronous with the clock signal, delaying and quantizing the signal, a ternary signal generating circuit for generating a ternary signal for selectively driving a load connected to a single power supply into ternary conductive states including a positive current on-state, a negative current on-state, and an off-state, a driver circuit for generating a driving signal for driving a load, and a feedback circuit for feeding back the driving signal from the driver circuit to the input signal.

Abstract: A method of lossless data compression includes receiving a set of parallel data strings; determining compression hash values for each of the parallel data strings; determining bit matches among portions of each of the parallel data strings based, at least in part, on the compression hash values; selecting among literals and the bit matches for each of the parallel data strings; and applying Huffman encoding to the selected literals or the selected bit matches.

Abstract: A nonvolatile memory storage controller is provided for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using a plurality of soft-decision reference voltages to provide a plurality of soft-decision bits representative of the codeword. The controller further includes a plurality of neighboring cell contribution LLR look-up tables representative of the contribution of the neighboring cells to threshold voltage distribution of the memory storage module. The controller provides the LLRs from the appropriate LLR look-up table to an LDPC decoder for the subsequent decoding of the codeword.

Abstract: In general, a minimum determination capability, adapted for determining one or more minimum values from a set of values, is provided. The minimum determination capability may enable, for a set of values, determination of a first minimum value representing a smallest value of the set of values and a second minimum value representing an approximation of a next-smallest value of the set of values. The minimum determination capability may enable, for a set of values where each of the values is represented as a respective set of bits at a respective set of bit positions, determination of a minimum value of the set of values based on a set of bitwise comparisons performed for the respective bit positions of the values.

Abstract: Decoding an LDPC encoded codeword is disclosed. Variable nodes corresponding to a parity check matrix of the LDPC encoded codeword have been divided into a plurality of groups. A selected group of variable nodes from the plurality of groups of variable nodes is updated. Check nodes are updated using a min-sum update. A selected input value provided from a variable node of the selected group of variable nodes and provided to a certain check node of the check nodes is discarded to be not available for use in a future min-sum update.

Abstract: A method of transmitting a broadcast signal includes encoding mobile data for FEC (Forward Error Correction); encoding signaling information for signaling the mobile data; allocating the encoded mobile data and signaling data into a transmission frame; and transmitting the broadcast signal including the transmission frame, wherein the transmission frame includes a service signaling table having service_type information identifying a type of a service of the mobile data and hidden information indicating whether the service of the mobile data is hidden or not.

Abstract: According to one embodiment, a method for reading data includes reading a data set repeatedly using different settings until either: a reconstructed data set is sent to a host and/or stored, or a maximum number of rereads has been reached, after each reading of the data set, storing each row to a reserved data buffer that has no errors or errors in the row are correctable using C1-error correction code (ECC) unless a matching row already exists in the reserved data buffer that has fewer corrected errors therein, assembling the data set from the rows stored in the reserved data buffer to form an assembled data set, correcting any remaining errors in the assembled data set using C2-ECC to form the reconstructed data set, and sending the reconstructed data set to the host and/or storing the reconstructed data set.

Abstract: Various embodiments disclose systems and methods for employing a Sub1G signal (e.g. a signal in the range of approximately 500 Mhz or 800 mHz) for use with internal and/or external components of various user devices. The Sub1G region may provide a path loss advantage over traditional 2.4 and 5 Ghz systems because of the lower frequency in free-space path loss model. Sub 1G may also present less interference compared to 2.4 GHz (e.g., better QoS for applications such as VOIP, Gaming, etc.). In some of the disclosed embodiments, Sub1G may be employed using current 2.4G or 5G Wireless LAN chipset with RF Up/Down Converters. In some embodiments, the Sub1G approach may be used to create a Long Range Bridge, Long Range Extender, Long Range Client, Long Range Hotspot, etc.

Abstract: An apparatus interworking with a metal member used both as an antenna and a sensor element in a portable terminal is disclosed. The apparatus includes the metal member, responsive to a sensed body, and for transmitting and receiving a signal in at least one or more communication service bands, and a main board having a communication module for processing a signal transmitted and received by the metal member and a sensor module for obtaining information in response to the approach of a sensed body.

Abstract: A radio apparatus includes a baseband signal generator to generate a baseband signal; a sine wave substituting device to substitute a transition part of the baseband signal in which a logic level switches from “0” to “1” or “1” to “0” with a sine wave represented with multi-values; and a delta sigma modulator to modulate the signal represented in the multi-values into a binary signal.

Abstract: A method in a network node comprises receiving a first input signal from a baseband processing unit of a first antenna branch, receiving a second input signal from a baseband processing unit of a second antenna branch, determining a first and second compensation coefficient, applying the first compensation coefficient to the second input signal to generate a first output signal, applying the second compensation coefficient to the first input signal to generate a second output signal, outputting the first output signal to a first power amplifier of the first antenna branch, the first output signal compensating for a mutual coupling from the second antenna branch to the first antenna branch, and outputting the second output signal to a second power amplifier of the second antenna branch, the second output signal compensating for a mutual coupling from the first antenna branch to the second antenna branch.

Abstract: A transmitter in a wireless communication system is provided. The transmitter includes a baseband signal processor for detecting an envelope signal, a supply modulator (SM) for producing power to be supplied to a power amplifier using the detected envelope signal, and the power amplifier for receiving voltage from the SM and for amplifying power of a transmit signal. The SM generates a compensation signal corresponding to switching noise generated via switching amplification, and adds the compensation signal and the switching noise. The amplifier of the wireless communication system can produce low switching noise, and the envelope tracking power amplifier can prevent reception degradation due to the noise of the supply modulator.

Abstract: Methods and systems are provided for mitigating noise and/or impedance effects in transmitters. The mitigation comprises, when transmitter is in a non-active mode, decoupling at least a portion of the transmitter and coupling an auxiliary component to a remaining portion of the transmitter. When the transmitter is in an active mode, the auxiliary component is decoupled from the remaining portion of the transmitter, and the at least a portion of the transmitter is coupled to the remaining portion of the transmitter. The auxiliary component comprises one or more of: a resistive element, a capacitive element, and a reactive component. The auxiliary component is configured such that it may achieve a small mismatching error.

Abstract: An apparatus for interference cancellation includes: a front end processing circuit, for receiving at least an interference signal and a desire signal; an inner processing circuit, for channel/noise estimation and for suppressing the interference signal; and a MIMO (multi-input multi-output) processing circuit, for blindly detecting an interference parameter of the interference signal based on the suppressed interference signal, and for jointly cancelling the interference signal from the desire signal and for demodulating the desire signal based on the detected interference parameter and the channel/noise estimation from the inner processing circuit.

Abstract: An approach to digital compensation uses a particular structure for a digital pre-distorter (DPD) which acts as a relatively accurate pre-inverse of a non-linear circuit (e.g., a non-linear transmit chain involving digital-to-analog converter (DAC), lowpass filter, modulator, bandpass filter, and power amplifier) while making use of a relatively small number of parameters that characterize the non-linearity and/or parameters that provide accurate linearization without requiring continual updating.

Abstract: Embodiments include semiconductor devices related to compound varactor circuits. Specifically, a semiconductor device may be constructed of a modified anti-series string of varactor pairs, wherein one varactor in a varactor pair has an effective area larger than the other varactor. Varactor pairs in the anti-series string are arranged such that adjacent varactors coupling varactor pairs have equal effective areas. In some embodiments, the anti-series string may have four varactors (two varactor pairs.) In other embodiments, the anti-series string may have eight varactors (four varactor pairs) or twelve varactors (six varactor pairs). The compound varactor using the modified anti-series string of varactor pairs may be advantageous in reducing second harmonics related to parasitic capacitances in anti-series varactor applications.

Abstract: There is to provide a communication device capable of reducing the power consumption. The communication device includes a battery and a transmission circuit for transmitting a signal of a desired transmission frequency upon receipt of a power supply from the battery. The transmission circuit includes a first oscillator for oscillating a signal, an amplifier for amplifying the signal oscillated by the first oscillator, and a filter circuit for eliminating a harmonic component included in the signal output from the amplifier. The filter circuit includes an extracting unit for extracting a frequency signal of n (n?2) times frequencies of the transmission frequency from the signal output from the amplifier and a recovery unit for recovering the battery with DC component of the extracted n times frequency signal.

Abstract: A detector includes an oscillation source, a frequency multiplier, a transceiver and a demodulator. The oscillation source generates a first injection signal with a first frequency. The frequency multiplier receives the first injection signal, outputs an output signal and receives a second injection signal with a second frequency. The frequency multiplier uses injection locking to lock a frequency of the output signal at a multiple of the first frequency, and uses injection pulling to pull the frequency of the output signal to the second frequency. The transceiver transmits the output signal and receives a received signal with a third frequency for updating the second injection signal. The demodulator performs a demodulation operation according to the output signal so as to generate a displacement signal.

Abstract: Provided are a wireless communication apparatus, an analysis apparatus, an analysis method and a non-transitory computer readable medium on which a program has been stored, in which a threshold value to be used for determining whether received radio waves are noise can be determined independently of an operator's capability. A threshold value is determined, on the basis of a number of intersections between a variation curve of radio wave intensity relative to the frequencies of the radio waves received by a receiver and a first line indicating a given radio wave intensity, a threshold value of radio wave intensity to be used for determining whether the received radio waves are noise.

Abstract: Aspects of the disclosure are directed to interference cancellation and wireless communication. A method of performing analog interference cancellation in a wireless communications device having a transmitter and a receiver includes receiving a reference signal representative of an interfering signal transmitted by the transmitter, selecting a first target interference type from one of a plurality of interference types affecting a an RF signal received by the receiver, configuring a first filter of an interference cancellation circuit using a coefficient computed based on the first target interference type, and cancelling interference in the RF signal using an output of the first filter. Coefficient computation may be performed in a switched manner between analog and digital domain, simultaneously in multiple domains, or in a cascaded manner that provides digital interference cancellation.

Abstract: Semiconductor devices with switchable connection between body and a ground node are presented. Methods for operating and fabricating such semiconductor devices are also presented.

Abstract: A signal receiving apparatus includes: a first amplifying device, a second amplifying device, a feedback device, and a mixing device, wherein the mixing device is a passive mixer, the second amplifying device is arranged to provide an input impedance looking into an input terminal of the second amplifying device to fall within a first impedance range when the second amplifying device operates in a first frequency range, the second amplifying device is arranged to provide the input impedance looking into the input terminal of the second amplifying device to fall within a second impedance range when the second amplifying device operates in a second frequency range, the second frequency range is different from the first frequency range, and the second impedance range is different from the first impedance range.

Abstract: A variable capacitance device includes: a first and second terminal for signals; a plural, even number of variable capacitance elements connected in-series between the first and second terminal; a third and fourth terminal for receiving a same voltage; a fifth and sixth terminal for grounding; a plurality of first resistors connected to either the third or fourth terminal on one end; and a plurality of second resistors connected to either the fifth or sixth terminal on one end. With respect to a series of successive nodes beginning with the first terminal and ending with the second terminal, respective other ends of a pair of the first resistors are connected to every other node, and respective other ends of a pair of the second resistors are connected to the remaining every other node, such that the pairs of first and second resistors are alternately connected to the series of successive nodes.

Abstract: An I/O unit includes a plurality of ports, a mixer includes processing channels, and the mixer and the I/O unit are interconnected via a network. The mixer stores channel data per processing channel. The channel data includes virtual port data for indirectly controlling signal processing of a port to which the channel is patched. The I/O unit stores real port data for controlling a signal processing in a corresponding port per port. In response to a connection instruction, one port and processing channels are interconnected, and real port data of the one port connected with the processing channels is set to a value of virtual port data being maintained for the processing channels.

Abstract: A mobile communication device includes an antenna element, a low-frequency blocking element, an isolation circuit, a first high-frequency blocking element and a second high-frequency blocking element. The antenna element converts a radio-frequency signal into an electromagnetic wave and includes a radiation portion and a parasitic portion. The parasitic portion and the radiation portion generate a first sensing signal and a second sensing signal in response to a proximity of an object. The low-frequency blocking element transmits the radio-frequency signal to the radiation portion. The isolation circuit is connected between the parasitic portion and a ground plane, and the isolation circuit blocks the first sensing signal and transmits the radio-frequency signal. The first high-frequency blocking element transmits the first sensing signal to a first sensing controller through a first metal line.

Abstract: A headset includes a detector providing an output indicating a donned or doffed condition and a processor for executing a user interface control application. The user interface control application enables or disables a user interface responsive to detection of the donned or doffed condition.

Abstract: A cellular phone mounting assembly includes a panel that has a front side, a back side, an upper edge, a lower edge, a first side edge and a second side edge. A foot is attached to and extends forward of the lower edge. A shoulder is attached to and extends rearwardly from the upper edge to form an obtuse angle with the panel. A support is attached to and extends downwardly from the shoulder. A clip is removably attached to and extends rearwardly from the support. The clip engages an automobile console.

Abstract: A method, system, and device provide power-efficient communications within the context of available power. Transmission and receipt data rates are scalable in accordance with output power available from a power source. Data is transmitted at a data rate determined, at least in part, by the available output power.

Abstract: This disclosure relates generally to embodiments disclosing a case designed to contain both a smartphone and a medical device, such as an epinephrine auto-injector. The case contains allows both the smartphone and the medical device to remain within the case while the case is being transported. The case may also include a containment device for securing the medical device and a release mechanism for releasing the medical device from the case.

Abstract: A protective case for a portable electronic device includes a rigid plastic frame bonded to a stretchable rubber cover and a back panel insert that can be removably inserted into a pocket in the rear of the stretchable rubber cover and plastic frame. To position a device in the case, the device is simply inserted into the front opening of the rigid plastic frame and stretchable rubber cover such that the edges of the stretchable cover stretch over the device and secure the device in the case. A variety of different removable back panels allow the stand to be easily reconfigured to include a stand for the device case, a pocket adapted to hold payment cards, a folding style wallet, a mirror or a fabric covering.