Abstract: A distributed object storage system has a monitoring agent and/or a maintenance agent configured to determine for each of a plurality of repair tasks the actual concurrent failure tolerance of a corresponding repair data object. The actual concurrent failure tolerance corresponds to the number of storage elements that store sub blocks of the repair data object and are allowed to fail concurrently.

Abstract: One aspect is a method that includes analyzing, by a processor of an analysis system, an instruction set architecture of a targeted complex-instruction set computer (CISC) processor to generate an instruction set profile for each CISC architectural instruction variant of the instruction set architecture. A combination of instruction sequences for the targeted CISC processor is determined from the instruction set profile that corresponds to a desired stressmark type. The desired stressmark type defines a metric representative of functionality of interest of the targeted CISC processor. Performance of the targeted CISC processor is monitored with respect to the desired stressmark type while executing each of the instruction sequences. One of the instruction sequences is identified as most closely aligning with the desired stressmark type based on performance results of execution of the instruction sequences with respect to the desired stressmark type.

Abstract: A method, non-transitory computer readable medium, and apparatus for assessing efficiency of a data center includes querying, based on a system management protocol, each of a plurality of information technology (IT) devices to obtain utilization information. A power rating value is obtained for each of the plurality of IT devices. An IT power consumption value for the plurality of IT devices is generated based on the utilization information for the plurality of IT devices and the power rating values. A value for at least one efficiency metric is generated and output based on the IT power consumption value.

Abstract: A system and method displaying usage histories of applications by devices on a network are provided. The method includes storing usage histories of applications that a first device has executed with a plurality of other devices through a network connection; setting, in the first device, at least one of a first mode and a second mode for displaying at least a part of the usage histories; displaying, if the first device is set in the first mode, usage histories of the executed applications arranged by device, with respect to the plurality of other devices; and displaying, if the first device is set in the second mode, usage histories of the plurality of other devices arranged by application, with respect to the executed applications.

Abstract: An information processing device that is powered by a battery is provided. The information processing device includes a processor. The processor evaluates a virtual remaining capacity of the battery corresponding to each of a plurality of operating systems running on a hypervisor executed by the information processing device, by using characteristic information that indicates a characteristic of each of the plurality of operating systems and a physical remaining capacity value that indicates a physical remaining capacity of the battery. In addition, the processor reports, to each individual operating system of the plurality of operating systems, a virtual remaining capacity value obtained by evaluating the virtual remaining capacity of the battery corresponding to the individual operating system.

Abstract: A system and method for correlating asynchronous operations via an operation identifier comprises receiving an originating operation from a first system that indicates a change in the first system and generating a first message with respect to the originating operation. The first message is associated with the operation identifier. The system and method further propagates the first message to a second system, which causes a subsequent operation being associated with the operation identifier to be performed by the second system, and correlates the originating operation and the subsequent operation via the operation identifier.

Abstract: A method(s) and system(s) of monitoring and logging of various identified events of the operating system or the software application hosted on the operating system is disclosed. The method includes configuring the events associated with at least one event handler for monitoring. The method further includes assigning the at least one event handler to active processes of an operating system for handling of the events. Further, the method includes capturing of events by a different daemons and collecting the captured events. To this end, the captured similar events are grouped in one or more groups. The method further includes filtering of collected events based on a definable filter configuration and generating a dashboard representation of the filtered events. The dashboard representations of filtered events are then reported to the user.

Abstract: Various technologies described herein pertain to performing time travel debugging. A computer-executable program can be executed. The computer-executable program can be executable under control of a virtual machine. The virtual machine can interact with a browser system during execution of the computer-executable program. Moreover, nondeterministic events can be logged via an interrogative virtual machine interface (VMI) during the execution of the computer-executable program. The nondeterministic events can be logged as part of event logs. Moreover, the interrogative VMI is between the virtual machine and the browser system. Further, snapshots of the virtual machine can be captured during the execution of the computer-executable program. The snapshots can be captured via the interrogative VMI. At least a portion of the execution of the computer-executable program can be replayed based at least in part on a snapshot and at least a portion of the event logs.

Abstract: The invention relates to a method and system for discovering and documenting the business knowledge contained in the functions of each program of existing software applications as expressed in the source code of each program using a novel method of dynamic business rule extraction that overcomes the inherent limitations of previous methods. The novelty of the method results from the deterministic relationship between program functions and the program code executed to perform each function as revealed by empirical analysis of the actual code execution, hence “dynamic” business rule extraction. This compares to previous methods which utilized a manual process, a fully automated process, and/or a process of analysis against the non-executing source code of each programs in which the analyst must infer the execution path, hence “static” business rule extraction. Furthermore, dynamic business rule extraction can deliver results without errors or omissions and document forensically that it has done so.

Abstract: Systems and techniques are described for tracking software code paths. A described technique includes receiving a first log of stack traces that includes a respective stack trace for each of a plurality of calls to access any of a plurality of data objects created during a first execution of an application, generating, for each of the stack traces in the first log, a script for a respective probe that identifies the data object accessed by the call corresponding to the stack trace, a respective instruction called to access the data object, and whether the access is a read or a write access for the data object, generating, for at least one of the probes, a second log that identifies the data object for the respective probe and the data stored in the data object, and generating a representation of the execution of the application using the second log.

Abstract: A list of classes found in a core dump file is determined. One or more classes requested by a classloader is also determined. A set of one or more classes requested by the classloader that are found in the core dump file is then determined.

Abstract: Pairing information is used by the target application to determine how to connect to the correct controller. A network pipe is established between the target application and the controller. The network pipe is used to pass information, such as to deliver/receive test information, between the controller and target application. A bridge may also be established between the controller and an analysis tool for the device hosting the target application. The bridge creates a communication path for the controller to send/receive information (e.g. commands, queries) to the analysis tool s to perform tests of the target application. Code may also be injected into the target application such that dynamic linked libraries may be simulated. Crash data may also be obtained by the controller (or some other device) that may not be typically available by a particular device platform.

Abstract: A method, computer program product, and system is described. A continuous integration environment is identified. A first software test associated with the continuous integration environment is identified. A probationary status for the first software test is determined, the probationary status indicating, at least in part, a potential lack of reliability for the first software test.

Abstract: Information about a failed build of a computer software project under development can be accessed, where the information describes symptoms of the failed build. Committed change collections can be identified as collections that were committed since a previous successful build of the computer software project. Also, respective scores for the committed change collections can be produced. Each score can represent an estimate of a likelihood that an associated one of the committed change collections is at least a partial cause of the build failure.

Abstract: According to one exemplary embodiment, a method for preparing a software component for verification is provided. The method may include receiving the software component and a design model. The method may also include generating a wrapper program based on the received software component and the received design model. The method may then include associating the received software component with the generated wrapper program. The method may further include determining a plurality of inputs for the received software component based on the received design model. The method may also include sending the determined plurality of inputs and the received software component with associated wrapper program to a verification tool.

Abstract: A computer comprises an input unit configured to acquire an input operation; a first program execution unit configured to execute a computing program performing a computation based on the input operation acquired by the input unit; a test scenario storage unit configured to store a plurality of test scenarios for the computing program; and a second program execution unit configured to execute a monitoring program determining whether or not the input operation acquired by the input unit corresponds to any of the plurality of the stored test scenarios.

Abstract: Methods, computer-readable media, and systems are provided for usability testing. Usability testing can include recording, via a testing toot, actions of a user of an application and interactions of the user with the application. Usability testing can also include comparing, via the testing tool, the actions and interactions of the user with a baseline flow of actions for the application. Usability testing can include identifying, via the testing tool, a usability problem with the application based on the comparison.

Abstract: An adaptive memory address translation method includes the following steps. Multiple request instructions are received. A memory address corresponding to each request instruction includes a bank address. The memory addresses corresponding to the request instructions are translated, such that the bank addresses corresponding to at least one part of the any two adjacent request instructions are different. A numerical translation is utilized to translate the memory addresses corresponding to the request instructions, such that the memory addresses corresponding to the any two adjacent request instructions have less different bits.

Abstract: A stack processor and method implemented using a ferroelectric random access memory (F-RAM) for code and a portion of the stack memory space having an instruction set optimized to minimize processor stack accesses and thus minimize program execution time. This is particularly advantageous in low power applications and those in which the power supply is only available for a finite period of time such as RFID implementations. Disclosed herein is a relatively small but complete set of instructions enabling a multitude of possible applications to be supported with a program execution time that is not too long.

Abstract: Methods and apparatus related to non-volatile memory page sector rotation are described. In one embodiment, logic rotates the order of one or more sectors by a rotation value prior to storage of the one or more sectors in a non-volatile memory device. Logic then rotates the one or more sectors back by the rotation value after reading the one or more sectors from the non-volatile memory device. Furthermore, at least one indirection block (corresponding to the one or more sectors) is stored in at least two different logical memory pages of the non-volatile memory. Other embodiments are also disclosed and claimed.

Abstract: A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.

Abstract: A method, and system for carrying out the method, for in-place reorganization of content, organized according to an original organization scheme, which is stored in a non-volatile storage of a device, to a target organization scheme. The method includes obtaining instructions to reorganize the content to a defined target organization scheme. The method further includes (i) generating, based on the instructions and applying target organization logic to a virtual storage, a sequence of update commands for generating, in the non-volatile storage, at least one target storage unit organized according to the defined target organization scheme, and (ii) executing the update commands on the non-volatile storage. Potential write-before-read conflicts may be identified based on the sequence of update commands, and potential conflicts resolved by reordering, adding, deleting, altering commands, and/or backing up content.

Abstract: A method for collection instance resizing. The method may include identifying at least one collection object within a collection framework of a virtual machine. The method may also include determining the at least one identified collection object satisfies at least one preconfigured criteria. The method may further include determining a garbage collection cycle count associated with the at least one identified collection object exceeds a preconfigured threshold. The method may also include determining an occupancy ratio associated with the at least one identified collection object is less than a preconfigured shrink threshold. The method may further include restructuring the at least one identified collection object based on the at least one identified collection object satisfying the at least one preconfigured criteria, the garbage collection cycle count exceeding the preconfigured threshold, and the occupancy ratio being less than the preconfigured shrink threshold.

Abstract: A data storage system includes data storage and random access memory. A sorting module is communicatively coupled to the random access memory and is configured to sort data blocks of incoming write data received in the random access memory. A storage controller is communicatively coupled to the random access memory and the data storage and is configured to write the sorted data blocks as individually-sorted data block sets to a staging area of the data storage. A method and processor-implemented process provide for sorting data blocks of incoming write data received in a random access memory of data storage and writing the sorted data blocks as individually-sorted data block sets to a staging area of the data storage.

Abstract: A data storage system includes data storage and random access memory. A sorting module is communicatively coupled to the random access memory and is configured to sort data blocks of incoming write data received in the random access memory. A storage controller is communicatively coupled to the random access memory and the data storage and is configured to write the sorted data blocks as individually-sorted data block sets to a staging area of the data storage. A method and processor-implemented process provide for sorting data blocks of incoming write data received in a random access memory of data storage and writing the sorted data blocks as individually-sorted data block sets to a staging area of the data storage.

Abstract: A memory device and method for altering a performance characteristic of a memory array to increase a rate at which the memory device writes data in response to the memory device experiencing a demand for bandwidth above a threshold. The memory device may include a memory controller and a memory array, which may include memristive memory elements. To alter a performance characteristic, for example, the memristive memory elements may be written at sub-full resistive states which have a smaller difference between high and low resistive states, and/or the memory controller may disable a subset of memory elements and/or memory cells along a bit line and/or word line of the memory array. The subset of memory elements may be re-enable in response to the demand for bandwidth falling below the threshold, and data may be moved and/or rearranged within the memory device when the subset of memory elements is re-enabled. Altering the performance characteristic may increase a rate at which the memory device writes data.

Abstract: Method and apparatus to efficiently maintain cache coherency by reading/writing a domain state field associated with a tag entry within a cache tag directory. A value may be assigned to a domain state field of a tag entry in a cache tag directory. The cache tag directory may belong to a hierarchy of cache tag directories. Each tag entry may be associated with a cache line from a cache belonging to a first domain. The first domain may contain multiple caches. The value of the domain state field may indicate whether its associated cache line can be read or changed.

Abstract: The disclosed technology provides an electronic device includes a semiconductor memory that includes a first contact plug over a substrate; an interlayer dielectric layer located over the first contact plug and having a hole which exposes at least a portion of the first contact plug; a first electrode layer formed along a sidewall and a bottom surface of the hole to be in contact with the first contact plug; a variable resistance layer over the first electrode layer and structured to include (1) a first portion that extends along the sidewall of the hole in a direction perpendicular to the substrate and exhibits a variable resistance and (2) a second portion that is parallel to the bottom surface of the hole and does not exhibit a variable resistance, and a second electrode layer formed over the variable resistance layer.

Abstract: Apparatuses, systems, and methods are disclosed for managing cache pools. A storage request module monitors storage requests received by a cache. The storage requests include read requests and write requests. A read pool module adjusts a size of a read pool of the cache to increase a read hit rate of the storage requests. A dirty write pool module adjusts a size of a dirty write pool of the cache to increase a dirty write hit rate of the storage requests.

Abstract: A method for generating a virtual volume (VV) in a storage system architecture. The architecture comprises a host and one or more disk array subsystems. Each subsystem comprises a storage controller. One or more of the subsystems comprises a physical storage device (PSD) array. The method comprises the following steps: mapping the PSD array into a plurality of media extents (MEs), each of the MEs comprises a plurality of sections; providing a virtual pool (VP) to implement a section cross-referencing function, wherein a section index (SI) of each of the sections contained in the VP is defined by the VP to cross-reference VP sections to physical ME locations; providing a conversion method or procedure or function for mapping VP capacity into to a VV; and presenting the VV to the host. A storage subsystem and a storage system architecture performing the method are also provided.

Abstract: A method to merge one or more non-transactional stores and one or more thread-specific transactional stores into one or more cache line templates in a store buffer in a store cache. The method receives a thread-specific non-transactional store address and a first data, maps the store address to a first cache line template, and merges the first data into the first cache line template, according to a store policy. The method further receives a thread-specific transactional store address and a second data, maps the thread-specific store address into a second cache line template, according to a store policy. The method further writes back a copy of a cache line template to a cache and invalidates a third cache line template, which frees the third cache line template from a store address mapping.

Abstract: A method to merge one or more non-transactional stores and one or more thread-specific transactional stores into one or more cache line templates in a store buffer in a store cache. The method receives a thread-specific non-transactional store address and a first data, maps the store address to a first cache line template, and merges the first data into the first cache line template, according to a store policy. The method further receives a thread-specific transactional store address and a second data, maps the thread-specific store address into a second cache line template, according to a store policy. The method further writes back a copy of a cache line template to a cache and invalidates a third cache line template, which frees the third cache line template from a store address mapping.

Abstract: Methods and apparatus for supporting cached volumes at storage gateways are disclosed. A storage gateway appliance is configured to cache at least a portion of a storage object of a remote storage service at local storage devices. In response to a client's write request, directed to at least a portion of a data chunk of the storage object, the appliance stores a data modification indicated in the write request at a storage device, and asynchronously uploads the modification to the storage service. In response to a client's read request, directed to a different portion of the data chunk, the appliance downloads the requested data from the storage service to the storage device, and provides the requested data to the client.

Abstract: A computer includes a first memory, a second memory having an I/O speed lower than an I/O speed of the first memory, a storage device, and a processor. The first memory has a work area and a first cache area where data input to and output from the storage device is temporarily stored and the second memory has a second cache area where the data input to and output from the storage device is temporarily stored and a swap area to be a saving destination of data stored in the work area. The processor reduces the work area and expands the first cache area, when an input/output amount to be an amount of data input to and output from the storage device is larger than a predetermined input/output amount.

Abstract: A method for pre-loading contents in a cache of a mobile terminal, and a mobile terminal using the method, are provided. The method includes determining specific contents for pre-loading, determining circumstances for pre-loading the specific contents, and monitoring circumstances of the mobile terminal. If the circumstances for pre-loading are detected, the method determines whether the specific contents are already present in cache, and if the specific contents are not present in cache, loads the specific contents into the cache when the circumstances for pre-loading are detected.

Abstract: A data storage system incorporating a write-caching subsystem that implements a steady-state media-based cache is described. The steady-state of the media-based cache can be obtained by directing non-sequential write commands and data received from the host device to multiple independent cache locations and, thereafter, selectively copying or moving such data between the caches so that none of the caches are either too full or too empty. In this manner, a non-sequential write command can be cached in a power-safe manner until it is efficient and/or convenient to write such data to the mainstore portion of the physical media.

Abstract: Method and apparatus for sending packets using optimized PIO write sequences without sfences. Sequences of Programmed Input/Output (PIO) write instructions to write packet data to a PIO send memory are received at a processor supporting out of order execution. The PIO write instructions are received in an original order and executed out of order, with each PIO write instruction writing a store unit of data to a store buffer or a store block of data to the store buffer. Logic is provided for the store buffer to detect when store blocks are filled, resulting in the data in those store blocks being drained via PCIe posted writes that are written to send blocks in the PIO send memory at addresses defined by the PIO write instructions. Logic is employed for detecting the fill size of packets and when a packet's send blocks have been filled, enabling the packet data to be eligible for egress.

Abstract: Techniques described herein generally include methods and systems related to cooperatively caching data in a chip multiprocessor. Cooperatively caching of data in the chip multiprocessor is managed based on an eviction rate of data blocks from private caches associated with each individual processor core in the chip multiprocessor. The eviction rate of data blocks from each private cache in the cooperative caching system is monitored and used to determine an aggregate eviction rate for all private caches. When the aggregate eviction rate exceeds a predetermined value, for example the threshold beyond which network flooding can occur, the cooperative caching system for the chip multiprocessor is disabled, thereby avoiding network flooding of the chip multiprocessor.

Abstract: Various systems and methods for caching and tiering in cloud storage are described herein. A system for managing storage allocation comprises a storage device management system to maintain an access history of a plurality of storage blocks of solid state drives (SSDs) managed by the storage device management system; and automatically configure each of a plurality of storage blocks to operate in cache mode or tier mode, wherein a ratio of storage blocks operating in cache mode and storage blocks operating in tier mode is based on the access history.

Abstract: A method for translating a virtual memory address into a physical memory address includes parsing the virtual memory address into a page directory entry offset, a page table entry offset, and an access offset. The page directory entry offset is combined with a virtual memory base address to locate a page directory entry in a page directory block, wherein the page directory entry includes a native page table size field and a page table block base address. The page table entry offset and the page table block base address are combined to locate a page table entry, wherein the page table entry includes a physical memory page base address and a size of the physical memory page is indicated by the native page table size field. The access offset and the physical memory page base address are combined to determine the physical memory address.

Abstract: One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table. In operation, the microcontroller receives a page fault generated by the MMU in response to an invalid memory access via a virtual memory address. To remedy such a page fault, the microcontroller performs actions to map the virtual memory address to an appropriate location in the physical memory. By contrast, in prior-art systems, a fault handler would typically remedy the page fault. Advantageously, because the microcontroller executes these tasks locally with respect to the MMU and the physical memory, latency associated with remedying page faults may be decreased. Consequently, overall system performance may be increased.

Abstract: Hierarchical address virtualization within a memory controller and configurable block device allocation are disclosed. Respective virtual block devices (VBDs) are defined in flash memory managed by a common memory controller, with data access managed using address virtualization techniques. The common memory controller then tracks the need for maintenance operations independently for each VBD. Information may be received from the common memory controller regarding the need for maintenance operations in respective virtual block devices (VBDs), and commands are then selectively issued to the common memory controller in a manner so as to independently schedule these operations for the respective VBDs; performance of maintenance operations by the memory controller in a first VBD is unconstrained by performance characteristics associated with a second VBD.

Abstract: Methods, systems, and computer program products are provided for optimizing selection of files for eviction from a first storage pool to free up a predetermined amount of space in the first storage pool. A method includes analyzing an effective space occupied by each file of a plurality of files in the first storage pool, selecting one or more of the plurality of files as one or more candidate files for eviction, based on the identified one or more data blocks, and evicting the one or more candidate files for eviction from the first storage pool to a second storage pool.

Abstract: Embodiments of the present invention provide a method and apparatus for removing cached data. The method comprises determining activeness of a plurality of divided lists; ranking the plurality of divided lists according to the determined activeness of the plurality of divided lists. The method comprises removing a predetermined amount of cached data from the plurality of divided lists according to the ranking result when the used capacity in the cache area reaches a predetermined threshold. Through embodiments of the present invention, the activeness of each divided list may be used to wholly measure the heat of access to the cached data included by each divided list, and upon removal, the cached data with lower heat of access in the whole system can be removed and the cached data with higher heat of access in the whole system can be retained so as to improve the read/write rate of the system.

Abstract: In a portable data carrier having a non-volatile memory, a memory controller and a memory interface, an effected initial operation of the data carrier is checked through a request to a security unit of the data carrier via a security interface connected to the security unit. For this purpose, the data carrier comprises a memory portion comprising the memory interface and a body portion comprising the security interface, which are interconnected such that the memory portion can be folded out of the body portion, so that simultaneously the memory interface is laid open for a connection to an end device and the electrical connection between the security unit and the security interface is disconnected irreversibly.

Abstract: A memory circuit using resistive random access memory (ReRAM) arrays in a secure element. The ReRAM arrays can be configured as content addressable memories (CAMs) or random access memories (RAMs) on the same die, with the control circuitry for performing comparisons of reference patterns and input patterns located outside of the ReRAM arrays. By having ReRAM arrays configured as CAMs and RAMs on the same die, certain reference patterns can be stored in CAMs and others in RAMs depending on security needs. For additional security, a heater can be used to erase reference patterns in the ReRAM arrays when desired.

Abstract: An information processing apparatus includes a storage managing unit configured to manage a storage device by dividing the storage device into a plurality of physical storage regions corresponding to respective modes used by the information processing apparatus, and a storage processing unit configured to cause data generated by the information processing apparatus during operation in a mode to be stored in a physical storage region corresponding to the mode. For example, the storage managing unit stores a policy in the storage device. The policy defines whether to permit the use of data between a plurality of security attributes corresponding to the respective physical storage regions.

Abstract: There is provided an electronic apparatus that performs a linked operation with an information processing device via first driver software that is installed in the information processing device and also performs a linked operation with an external device that performs a linked operation with the information processing device via second driver software that is installed in the information processing device. A linked operation is performed with the external device when only the first driver software and second driver software are installed in the information processing device. The first driver software includes a software portion that serves as application software capable of being invoked by the second driver software.

Abstract: In a semiconductor device which calculates an interaction model, a technique capable of executing interaction calculation in non-synchronization with a clock is provided. The semiconductor device includes a plurality of units each of which includes: a first memory cell for storing a value indicating a state of one node of an interaction model; a second memory cell for storing an interaction coefficient indicating an interaction from a node connected to the one node; and an interaction calculation circuit for determining a value indicating a next state of the one node based on a current determined by a value indicating a state of the connected node and the interaction coefficient.

Abstract: A method and an apparatus are provided for controlling a memory in an electronic device. A kernel of a control unit in the electronic device receives importance information, based on program information, and memory usage, from an Operating System (OS) framework of the control unit. It is determined whether a memory request signal is received at the kernel from the OS framework. The kernel terminates at least one program based on the memory request signal and the importance information, when the memory request signal is received.