Patents Issued in March 21, 2017
  • Patent number: 9600413
    Abstract: Technologies for one-level memory (1LM) and two-level memory (2LM) configurations in a common platform are described. A processor includes a first memory interface coupled to a first memory device that is located off-package of the processor and a second memory interface coupled to a second memory device that is located off-package of the processor. The processor also includes a multi-level memory controller (MLMC) coupled to the first memory interface and the second memory interface. The MLMC includes a first configuration and a second configuration. The first memory device is a random access memory (RAM) of a one-level memory (1LM) architecture in the first configuration. The first memory device is a first-level RAM of a two-level memory (2LM) architecture in the second configuration and the second memory device is a second-level non-volatile memory (NVM) of the 2LM architecture in the second configuration.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventors: Joydeep Ray, Varghese George, Inder M. Sodhi, Jeffrey R. Wilcox
  • Patent number: 9600414
    Abstract: Subject matter disclosed herein relates to performing concurrent memory operations.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: March 21, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Luca Porzio, Rodolphe Sequeira
  • Patent number: 9600415
    Abstract: Disclosed is a method of managing a storage server in a database system. Provided is a storage server including a cache device to store at least one block that includes data; a permanent storage medium to record the at least one block stored in the cache device; and a controller to record the at least one block stored in the cache device in the permanent storage medium, wherein the controller includes a grade determiner to determine a grade of each of the at least one block based on a size of each of the at least one block; a victim block determiner to determine a victim block to be recorded in the permanent storage medium among blocks stored in the cache device based on the determined grade of each of the at least one block; and a block recorder to record the determined victim block in the permanent storage medium.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: March 21, 2017
    Inventors: Moon Hoen Lee, Hun Young Park
  • Patent number: 9600416
    Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventors: Raj K. Ramanujan, Rajat Agarwal, Kai Cheng, Taarinya Polepeddi, Camille C. Raad, David J. Zimmerman, Muthukumar P. Swaminathan, Dimitrios Ziakas, Mohan J. Kumar, Bassam N. Coury, Glenn J. Hinton
  • Patent number: 9600417
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for caching data not frequently accessed. One of the methods includes receiving a request for data from a component of a device, determining that the data satisfies an infrequency condition, in response to determining that the data satisfies the infrequency condition: determining a target cache level which defines a cache level within a cache level hierarchy of a particular cache at which to store infrequently accessed data, the target cache level being lower than a highest cache level in the cache level hierarchy, requesting and receiving the data from a memory that is not a cache of the device, and storing the data in a level of the particular cache that is at or below the target cache level in the cache level hierarchy, and providing the data to the component.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: March 21, 2017
    Assignee: Google Inc.
    Inventors: Richard Yoo, Liqun Cheng, Benjamin C. Serebrin, Parthasarathy Ranganathan, Rama Krishna Govindaraju
  • Patent number: 9600418
    Abstract: Certain embodiments herein relate to using tagless access buffers (TABs) to optimize energy efficiency in various computing systems. Candidate memory references in an L1 data cache may be identified and stored in the TAB. Various techniques may be implemented for identifying the candidate references and allocating the references into the TAB. Groups of memory references may also be allocate to a single TAB entry or may be allocated to an extra TAB entry (such that two lines in the TAB may be used to store L1 data cache lines), for example, when a strided access pattern spans two consecutive L1 data cache lines. Certain other embodiments are related to data filter cache and multi-issue tagless hit instruction cache (TH-IC) techniques.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: March 21, 2017
    Assignee: Florida State University Research Foundation, Inc.
    Inventors: David Whalley, Hans Magnus Sjalander, Alen Bardizbanyan, Per Larsson-Edefors, Peter Gavin
  • Patent number: 9600419
    Abstract: An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration, and the use of a particular translation structure format in translating an address is selectable.
    Type: Grant
    Filed: October 8, 2012
    Date of Patent: March 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Bybell, Bradly G. Frey, Michael K. Gschwind
  • Patent number: 9600420
    Abstract: Aspects include computing devices, systems, and methods for implementing executing decompression of a compressed page. A computing device may determine a decompression block of a compressed page that contains a code instruction requested in a memory access request. Decompression blocks, other than the decompression block containing the requested code instruction, may be selected for decompression based on being situated between an end of the compressed page and the decompression block containing the requested code instruction. Decompression blocks not identified for decompression may be substituted for a fault or exception code. The computing device may decompress decompression blocks identified for decompression, starting at the end of the compressed page and terminating the decompression of the compressed page upon filling all blocks with decompressed blocks, faults, or exception code.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: March 21, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Andres Alejandro Oportus Valenzuela, Richard Senior, Raghuveer Raghavendra, Nieyan Geng, Gurvinder Singh Chhabra
  • Patent number: 9600421
    Abstract: Encrypted storage often introduces unwanted latency in access. This delay can result in a processor having to wait for critical data thus slowing performance. Generally speaking, the latency is at most an issue when reading from encrypted storage, since the processor may need the information read from encrypted storage to proceed. During a write operation, there typically is not an issue because the processor does not need to wait for the end of the write operation to proceed. A variant of counter (CTR) mode for a block cipher can be used to perform the majority of the decryption operation without knowledge of the ciphertext, therefore the majority of the decryption operation can be performed concurrently with the retrieval of the ciphertext from memory. In order to further secure the encrypted storage, a light encryption can be performed to further obfuscate the ciphertext.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: March 21, 2017
    Assignee: Conexant Systems, Inc.
    Inventor: Mark E. Miller
  • Patent number: 9600422
    Abstract: Embodiments of the present invention provide methods and apparatus in a multiprocessor system, whereby a set of rules relating to memory access are created and implemented in a hardware element. The rules can be updated dynamically, for example by the sequence processor (or sequencer) used to control the multiple processing elements.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: March 21, 2017
    Assignee: u-blox AG
    Inventors: Paul Tindall, Erkut Uygun
  • Patent number: 9600423
    Abstract: An example includes periodic access of a hardware resource of a computer by instructions in firmware of the computer that are executed by an interpreter in the context of the operating system without a driver. The access occurs in response to a periodic interrupt generated by a timer.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: March 21, 2017
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kimon Berlin, Stephen G Uhlmann
  • Patent number: 9600424
    Abstract: Semiconductor chips are provided. The semiconductor chip includes a first data pad, a first data strobe pad and a second data pad sequentially arrayed from a command address pad in a first direction. In addition, the semiconductor chip includes a third data pad, a second data strobe pad and a fourth data pad sequentially arrayed from the command address pad in a second direction. Data are inputted and outputted through the first and fourth data pads or through the second and third data pads in a predetermined bit organization. Related semiconductor chip packages and semiconductor systems are also provided.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: March 21, 2017
    Assignee: SK hynix Inc.
    Inventors: Bok Rim Ko, Dong Kyun Kim
  • Patent number: 9600425
    Abstract: A method for serial data transmission in a bus system having at least two subscribed data processing units, the data processing units exchanging messages via the bus, the transmitted messages having a logical structure in accordance with the CAN standard ISO 11898-1, the logical structure including a start-of-frame bit, an arbitration field, a control field, a data field, a CRC field, an acknowledge field and an end-of-frame sequence, the control field including a data length code, which contains information regarding the length of the data field. The CRC field of the transmitted messages may have at least two different numbers of bits as a function of the content of the data length code.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: March 21, 2017
    Assignee: ROBERT BOSCH GMBH
    Inventor: Florian Hartwich
  • Patent number: 9600426
    Abstract: A bus control device includes a plurality of bus masters classified into a plurality of groups according to a priority level, a plurality of group buses each group bus being connected to a corresponding group of bus masters and assigned with a priority level determined according to the priority levels of the corresponding group of bus masters, an upper priority bus that arbitrates a plurality of bus obtaining requests received from the plurality of bus maters via the plurality of group buses, a plurality of masks respectively provided for the plurality of bus masters to mask the bus obtaining request addressed to the corresponding group bus from the corresponding bus master, and a plurality of mask controllers respectively provided for the plurality of group buses to output at least one mask signal that controls operation of at least one corresponding mask connected to the corresponding group bus.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: March 21, 2017
    Assignee: Ricoh Company, Ltd.
    Inventor: Yoshikazu Gyobu
  • Patent number: 9600427
    Abstract: A receiver circuit includes: a plurality of first holding circuits respectively latching a plurality of reception data pieces on the basis of a same clock signal; a comparison circuit respectively comparing first reception data pieces and second reception data pieces after a certain time elapses since the latch of the plurality of first holding circuits, the first reception date pieces being respectively latched by the plurality of first holding circuits, the second reception data pieces being respectively input to the plurality of first holding circuits; and a plurality of second holding circuits respectively latching the first reception data pieces when a first output signal of the comparison circuit indicates that the first reception data pieces and the second reception data pieces are identical.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: March 21, 2017
    Assignee: SOCIONEXT INC.
    Inventor: Masahiro Kudo
  • Patent number: 9600428
    Abstract: A method, system and computer program product are provided for implementing block extent granularity authorization command flow processing for a Coherent Accelerator Processor Interface (CAPI) adapter. An Application Client builds a command including start LBA and number of LBAs and Child Authorization Handle. The Application Client sends the command directly to the CAPI Adapter via the Application Clients CAPI Server Registers assigned to the specific Application Client. The CAPI adapter validate that the requesting Client is authorized to perform the command using the Authorization Handle and the receiving CAPI Server Register address. The CAPI Adapter executes the validated command and sends completion back to the Application Client.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: March 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Brian E. Bakke, Adrian C. Gerhard, Daniel F. Moertl
  • Patent number: 9600429
    Abstract: A data processing system comprising: a host computer system supporting a software entity and a receive queue for the software entity; a network interface device having a controller unit configured to provide a data port for receiving data packets from a network and a data bus interface for connection to a host computer system, the network interface device being connected to the host computer system by means of the data bus interface; and an accelerator module arranged between the controller unit and a network and having a first medium access controller for connection to the network and a second medium access controller coupled to the data port of the controller unit, the accelerator module being configured to: on behalf of the software entity, process incoming data packets received from the network in one or more streams associated with a first set of one or more network endpoints; encapsulate data resulting from said processing in network data packets directed to the software entity; and deliver the network
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: March 21, 2017
    Assignee: SOLARFLARE COMMUNICATIONS, INC.
    Inventor: Steven L. Pope
  • Patent number: 9600430
    Abstract: Provided is a computer-implemented method of managing data paths between a computer application and a storage device. The I/O (input/output) load data of a computer application is obtained. If the I/O load data of the computer application is above a pre-determined threshold, data paths are provisioned between the computer application and the storage device based on a pre-defined policy applicable to the computer application.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: March 21, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Narsimha Reddy Challa, Mohammed Sakhavullah, Vamsi Penumatsa
  • Patent number: 9600431
    Abstract: A set of training sequences is generated, each training sequence to include a respective training sequence header, and the training sequence header is to be DC-balanced over the set of training sequences. The set of training sequences can be combined with electric ordered sets to form supersequences for use in such tasks as link adaptation, link state transitions, byte lock, deskew, and other tasks.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Darren S. Jue, Sitaraman V. Iyer
  • Patent number: 9600432
    Abstract: A verification environment enables verification of runtime switch-over—i.e., a switch-over without restarting the device under test—between multiple I/O protocols that share a same physical interface. The device under test can be a switch unit having multiple logical protocol processing units and a logical protocol multiplexor. The verification environment includes a switch-over detector which monitors the state of the device under test, and a switch-over controller that controls the switch-over sequence by pausing and re-starting traffic on all or specific protocol drivers of the verification environment.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: March 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas M. Armstead, John H. Klaus, Paul E. Schardt, Scott M. Willenborg
  • Patent number: 9600433
    Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventors: Arvind Mandhani, Woojong Han, Ken Shoemaker, Madhu Athreya, Mahesh Wagh, Shreekant S. Thakkar
  • Patent number: 9600434
    Abstract: A switch fabric is disclosed that includes a serial communications interface and a parallel communications interface. The serial communications interface is configured for connecting a plurality of slave devices to a master device in parallel to transmit information between the plurality of slave devices and the master device, and the parallel communications interface is configured for separately connecting the plurality of slave devices to the master device to transmit information between the plurality of slave devices and the master device, and to transmit information between individual ones of the plurality of slave devices. The parallel communications interface may comprise a dedicated parallel communications channel for each one of the plurality of slave devices. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: March 21, 2017
    Assignee: Bedrock Automation Platforms, Inc.
    Inventors: James G. Calvin, Albert Rooyakkers
  • Patent number: 9600435
    Abstract: New techniques for establishing communications connections for computer peripheral devices are provided. In some aspects, new forms of audio-jack-connecting peripheral devices are disclosed, which permit the continued use of the phone jack of a PDA for purposes other than communication with the peripheral device. In other aspects, a new technique for rapidly establishing a uniform, secure wireless peripheral device network is provided. In some embodiments of the invention, the secure peripheral device network is activated by physical docking and/or interlocking, without any use of a wired network connection, based on precise proximity and location information. In other embodiments, a secure, encrypted peripheral device network is established by a system in response to terminating a wired network connection, easing the transition from wired to wireless connection status, and easing the creation of a wireless network, generally.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 21, 2017
    Inventor: Christopher V. Beckman
  • Patent number: 9600436
    Abstract: A method of and apparatus for communicating between a host and an agent. The method includes the step of performing a first transaction between a host controller and a hub. The hub is operable to perform a single transaction with an agent based on the first transaction. The method then includes the step of performing a second transaction between the host controller and the hub. The second transaction is based on the single transaction.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventors: John I. Garney, John S. Howard
  • Patent number: 9600437
    Abstract: The present disclosure includes a master device, a plurality of slave devices performing a communication through Profibus and a configuration tool providing network configuration information of Profibus DP by generating the network configuration information, wherein the configuration tool includes an automatic configuration module configured to request the master device of information relative to the plurality of slave devices in response to an automatic configuration command inputted through a user communication module, to receive the information and provide profiles of relevant types by determining the types of the plurality of slave devices using the received information, and a network configuration information configured to generate the network configuration information in response to the types and profiles determined by the automatic configuration module and to provide the network configuration information to the master device.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: March 21, 2017
    Assignee: LSIS CO., LTD.
    Inventor: Duk Yun Cho
  • Patent number: 9600438
    Abstract: A method and apparatus for controlling and coordinating a multi-component system. Each component in the system contains a computing device. Each computing device is controlled by software running on the computing device. A first portion of the software resident on each computing device is used to control operations needed to coordinate the activities of all the components in the system. This first portion is known as a “coordinating process.” A second portion of the software resident on each computing device is used to control local processes (local activities) specific to that component. Each component in the system is capable of hosting and running the coordinating process. The coordinating process continually cycles from component to component while it is running.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: March 21, 2017
    Assignee: Florida Institute for Human and Machine Cognition, Inc.
    Inventors: Kenneth M. Ford, Niranjan Suri
  • Patent number: 9600439
    Abstract: A location manager includes a memory and a processor coupled to the memory. The processor executes a process including extracting a combination of a transfer device and a path by using topology information indicating a relation of connections among transfer devices. The process including calculating a sum of an amount of electric power consumed by the transfer device being included in the combination to store the data and an amount of electric power consumed by transfer devices on a path included in the combination to transfer the data. The process including selecting a combination of which the sum of electric power calculated at the calculating is a minimum sum out of the combinations extracted at the extracting. The process including outputting information indicating the combination selected at the selecting.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: March 21, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Satoshi Imai
  • Patent number: 9600440
    Abstract: An interconnection system comprising a plurality of nodes, each comprising at least two ports, and a plurality of links configured to interconnect ports among the nodes to form a hierarchical multi-level ring topology, wherein the ring topology comprises a plurality of levels of rings including a base ring and at least two hierarchical shortcut rings, and wherein each node connected to a higher-level shortcut ring is also connected to all lower-level rings including the base ring.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: March 21, 2017
    Assignee: Futurewei Technologies, Inc.
    Inventors: Iulin Lih, William Lynch
  • Patent number: 9600441
    Abstract: An apparatus and method for configuring a firewall application for controlling network access of applications included on a mobile terminal are provided. The method includes executing the firewall application displaying a list of at least one application stored on the mobile terminal, selecting at least one of the applications from the displayed list, selecting at least one parameter type corresponding to the at least one selected application, and configuring at least one parameter setting corresponding to the at least one selected parameter type, wherein the firewall application is executed according to the configured at least one parameter setting.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: March 21, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Gaurav Sharad Tungatkar
  • Patent number: 9600442
    Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode a no-locality hint vector memory access instruction. The no-locality hint vector memory access instruction to indicate a packed data register of the plurality of packed data registers that is to have a source packed memory indices. The source packed memory indices to have a plurality of memory indices. The no-locality hint vector memory access instruction is to provide a no-locality hint to the processor for data elements that are to be accessed with the memory indices. The processor also includes an execution unit coupled with the decode unit and the plurality of packed data registers. The execution unit, in response to the no-locality hint vector memory access instruction, is to access the data elements at memory locations that are based on the memory indices.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventor: Christopher J Hughes
  • Patent number: 9600443
    Abstract: Mechanisms for tracking an entity are provided. A time is determined by a sensor having a clock, the time being within a time slot in a series of time slots. First data of the time slot is provided and shared between a plurality of sensors. The sensor receives data from the movable entity. The sensor calculates identifying data from the received data for identifying the entity. Derivative identifying data is calculated by applying a modifying function using the provided first data for modifying the identifying data. The sensor calculates a hash value by taking the derivative identifying data as input. The sensor sends a message to a central server for determining the position of the entity, the message comprising the hash value and an identifier of the sensor.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: March 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Gherardo Albano, Dario De Judicibus
  • Patent number: 9600444
    Abstract: A signal generation method for generating an information signal F(b) by performing a Fourier transform on a signal f(a) includes the following steps: detecting the maximum peak intensity of the information signal F(b); calculating an amplitude, a phase, and a frequency of the signal f(a) corresponding to the maximum peak intensity; generating a signal by causing the signal f(a) corresponding to the maximum peak intensity to extend along an ‘a’ axis on the basis of information about the amplitude, the phase, and the frequency of the signal f(a); generating an extrapolation signal by extracting a signal in a region smaller than a1 and a signal in a region larger than a2 from the signal, where a1<a2; generating a composite signal by combining the extrapolation signal with the signal f(a) in a range from a1 to a2; and performing a Fourier transform on the composite signal.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: March 21, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takefumi Ota
  • Patent number: 9600445
    Abstract: A machine-implemented method for computerized digital signal processing including obtaining a digital signal from data storage or from conversion of an analog signal, and determining, from the digital signal, one or more measuring matrices. Each measuring matrix has a plurality of cells, and each cell has an amplitude corresponding to the signal energy in a frequency bin for a time slice. Cells in each measuring matrix having maximum amplitudes along a time slice and/or frequency bin are identified as maximum cells. Maxima that coincide in time and frequency are identified and a correlated maxima matrix, called a “Precision Measuring Matrix” is constructed showing the coinciding maxima and the adjacent marked maxima are linked into partial chains.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: March 21, 2017
    Assignee: Digital Harmonic LLC
    Inventors: Paul Reed Smith, Jack W. Smith, Frederick M. Slay
  • Patent number: 9600446
    Abstract: A preconditioner processor and a method of computing a preconditioning matrix. In one embodiment, the preconditioner processor has parallel computing pipelines including: (1) a graph coloring circuit operable to identify parallelisms in a sparse linear system, (2) an incomplete lower triangle, upper triangle factorization (ILU) computer configured to employ the parallel computing pipelines according to the parallelisms to: (2a) determine a sparsity pattern for an ILU preconditioning matrix, and (2b) compute non-zero elements of the ILU preconditioning matrix according to the sparsity pattern, and (3) a memory communicably couplable to the parallel computing pipelines and configured to store the ILU preconditioning matrix.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: March 21, 2017
    Assignee: Nvidia Corporation
    Inventors: Robert Strzodka, Julien Demouth, Patrice Castonguay
  • Patent number: 9600447
    Abstract: A layout manager can generate a layout for displaying a plurality of content units in a display area using a layout strategy, with the layout strategy specifying a layout design rule. The generated layout can indicate a position in the display area for the plurality of content units. In some embodiments, the design rule(s) may in effect “codify” traditional graphic design principles. When the layout is generated, the content units can be placed into a display area of a page and then the layout can be checked against at least one design rule and the layout adjusted as needed to meet the design rule. The system can comprise a user interface module that renders the content units in the display area using the generated layout. In some embodiments, content units are placed into a layout on a one-by-one basis according to priority, available display space, and one or more design rules.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: March 21, 2017
    Assignee: Adobe Systems Incorporated
    Inventors: Daniel Wabyick, Justin Van Slembrouck
  • Patent number: 9600448
    Abstract: Document management system includes a composite document (CD) and a mixed workflow, which includes an unordered stage followed by one of i) an ordered stage or ii) another unordered stage. The system includes a map-file (map) of the document (CD) for a participant (P) in the mixed workflow that is associated with the ordered or other unordered stage, and a wrap (W) of the map-file (map). Wrap (W) includes a number of map-file fragments (F) equal to or greater than a number of workflow participants (P) within a group (G) associated with the unordered stage. The number of map-file fragments (F) renders the document (CD) inaccessible to the participant (P) that is associated with the ordered or other unordered stage until each of the number of map-file fragments (F) is released by each of the workflow participants (P) within the group (G).
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: March 21, 2017
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Helen Balinsky, Steven J. Simske
  • Patent number: 9600449
    Abstract: An authoring tool for authoring wrap packages of cards. The authoring tool includes a set of tools that enable an author to create a new card of a wrap selected from a variety of card templates. In various embodiments, the card templates include textual, video, image/photo, document, gallery, chat, widgets, global components, location/GPS, transact, appointment, and end-of-wrap card templates. When a particular card template is selected, the template is then duplicated to create the new card. Thereafter, the author may author the card to include various components, content, attributes, layouts, styles triggers and/or behaviors. As the cards of the wrap are created, the authoring tool provides the author with the ability to order the sequence of the cards. The authoring tool thus enables authors to selectively create wrap packages that include media that conveys a narrative story and application functionality.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: March 21, 2017
    Assignee: Wrap Media, LLC
    Inventors: Eric H. Greenberg, John M. Garris, Ian McFarland, Jared L. Ficklin, Mark E. Rolston, Matthew J. Santone, Jon Stevens, Eric J. Wicks
  • Patent number: 9600450
    Abstract: A system for and method of displaying non-rectangular images in electronic content on an electronic device in accordance with exemplary embodiments may include identifying, using a template identification computing apparatus, an image shape template associated with a non-rectangular image that is part of electronic content to be displayed on the electronic device, determining, using a boundary region determination computing apparatus, a boundary region of the image shape template, placing, using an image placement computing apparatus, the non-rectangular image inside the boundary region of the image shape template and on the electronic content, flowing, using a text flow computing apparatus, text that is part of the electronic content outside and along the boundary region of the image shape template, and transmitting, using a communication computing apparatus, the electronic content along with the non-rectangular image to the electronic device via a network.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: March 21, 2017
    Assignee: Google Inc.
    Inventors: Brady Duga, John Rivlin, Vincent Le Chevalier, Garth Conboy
  • Patent number: 9600451
    Abstract: A method for a terminal to display a file includes sending to a server a file specification corresponding to the file; receiving from the server a data package for trimming page margins of the file, wherein the data package is generated according to the file specification, and includes margin trimming data of a page of the file; and displaying the page of the file based on the received data package.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: March 21, 2017
    Assignee: Xiaomi Inc.
    Inventor: Ruiheng Qiu
  • Patent number: 9600452
    Abstract: Creating and delivering advertisements within wrapped packages of cards, which selectively include (i) media content, including advertisement(s) for item(s) available for purchase, (ii) application functionality and/or (iii) e-commerce related transactional services. By defining the sequence order in which the cards are navigated when consumed, wraps may deliver advertisements in the context of a “story” or “narrative”, which unfolds as the cards are sequentially browsed, similar to the turning of the pages of a book or magazine. Ads thus become more compelling. In addition, with built-in transactional functionality, advertised Item(s) can be immediately purchased without having to exit the wrap.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: March 21, 2017
    Assignee: Wrap Media, LLC
    Inventors: Eric H. Greenberg, John M. Garris, Ian McFarland, Jon Stevens, Francis C. Li, Dana A. Levine, Mark E. Rolston, Jared L. Ficklin, Sylvio H. Drouin
  • Patent number: 9600453
    Abstract: Multimedia content is featured on user pages of an online social network using embed codes that are generated using a configuration file associated with the source ID for the multimedia content and a content ID for the multimedia content. The configuration file, the source ID and the content ID are stored locally by the online social network so that any changes to the embed codes can be made by changing the configuration file associated with the source and regenerating the embed codes. By managing multimedia content in this manner, greater control can be exercised by the online social network over the multimedia content that are featured on its user pages.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: March 21, 2017
    Assignee: Facebook, Inc.
    Inventors: William K. Tiu, Jr., Jeffrey J. Roberto
  • Patent number: 9600454
    Abstract: A method to generate an effective schema of an electronic document for optimizing the processing thereof may include performing a programmatic analysis to determine all required portions of the electronic document. The method may also include generating a parser or deserializer to build an optimized document model; and specializing a document processing program against the optimized document model.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: March 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Abraham Heifets, Joseph J. Kesselman, Eric David Perkins
  • Patent number: 9600455
    Abstract: There is disclosed a system, including apparatus, methods and computer programs, for running native software applications (apps) and HTML5 web-based apps on a computing device, particularly a mobile computing device, in a multitasking mode of operation. In one embodiment, touch screen displays having one or more browsers are adapted to run one or more HTML5 apps, and receive input from hand gestures. One or more software modules execute on the operating system and are responsive to a dragging gesture applied to an HTML5 app displayed in a full screen mode, to subdivide the screen display and display the HTML5 app in one of the subdivided areas and display icons used to launch a second HTML5 app in a different one of the subdivided areas. The second HTML5 app is run concurrently with the first HTML5 app in order to provide multi-tasking between the first and second apps.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventors: Rita H Wouhaybi, David Shaw
  • Patent number: 9600456
    Abstract: In a method for automatically performing a web service operation, input regarding actions of a user performing a task on a web service are received, an automated web task from the received input is generated, in which the automated web task is to perform the received actions, In addition, an image containing an object is accessed, the object contained in the image is associated with the automated web task to cause the automated web task to be automatically performed by another image containing the object, and the association between the object and the automated web task is stored in a data store.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: March 21, 2017
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Madhvanath Sriganesh, Manjunath Geetha, Kuchibhotla Anjaneyulu, Vimal Sharma, Mathur Nidhi
  • Patent number: 9600457
    Abstract: Personalized metadata may be selected from a group of tags, where the tags include annotations, synopsis, references, etc. and owner controlled rules for visibility and control options such as removal, combining, weighting, adding, sharing, privatizing, assigning etc. are provided.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: March 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael G. Alexander, Jose L. Lopez, Matthew S. Rosno
  • Patent number: 9600458
    Abstract: Methods and systems are provided for styling elements of a web document at a time of rendering the web document. In one embodiment, a method comprises: performing steps on a processor. The steps comprise: identifying a rule associated with a property of an element of the web document; determining whether the rule is to be grouped with multiple elements of the web document; generating an overriding rule when the rule is associated with multiple elements of the web document; and updating a style sheet based on the overriding rule.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: March 21, 2017
    Assignee: Google Technology Holdings LLC
    Inventors: Eric Guzman, Jose Antonio Marquez
  • Patent number: 9600459
    Abstract: A Visual Macro Program records and replays desired actions performed by a user in creating or editing a document. The recorded actions are appended to the document as an attachment that can be replayed by a user at a later time by enabling a tag associated with the recorded actions.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: March 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Susann Marie Keohane, Gerald Francis McBrearty, Jessica Carol Murillo, Johnny Meng-Han Shieh, Shawn Patrick Mullen
  • Patent number: 9600460
    Abstract: A digital publishing platform enables users to create and organize notes associated with electronic, published documents. Sets of notes, each associated with a document, are uploaded to the publishing platform by notepad applications executing on user devices. Each set of notes has one or more notes, and each note includes a link to a location in the associated document. The publishing platform is configured to aggregate a plurality of sets of notes, combining the notes of the sets into a single set while maintaining their link to an associated document.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: March 21, 2017
    Assignee: Chegg, Inc.
    Inventors: Yehuda Gilead, Arieh Glazer, Shahaf Shakuf, Shannyn Timrott, Brent Tworetzky, Ohad Eder-Pressman, Gerard Genesse, Vincent Le Chevalier, Charles Geiger
  • Patent number: 9600461
    Abstract: A system, and computer program product for discovering relationships in tabular data are provided in the illustrative embodiments. A set of documents is received, a document in the set including the tabular data. A cell in the tabular data is selected whose dependencies are to be determined. A hypothesis to use in conjunction with the cell is selected. Whether the hypothesis applies to a selected portion of the document is tested by determining whether a conclusion in the hypothesis can be computed using a function specified in the hypothesis on the selected portion. The selected portion can be a selected cell-range in the tabular data or content in a non-tabular portion of the document. The hypothesis is utilized to describe the cell relative to the selected portion.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: March 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Donna Karen Byron, Scott N. Gerard, Alexander Pikovsky, Matthew B. Sanchez
  • Patent number: 9600462
    Abstract: A computer system receives a request to combine tabular data of a first table with tabular data of a second table. The computer system creates a profile for the second table indicating organization of types of data within the second table. The computer system determines a placement for at least one data element of the tabular data of the first table, into the second table, such that the placement agrees, to at least a specified confidence level, with the organization of types of data within the second table indicated by the profile. The computer system adds the at least one data element to the second table based on the determined placement.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: March 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Paul R. Bastide, Matthew E. Broomhall, Robert E. Loredo