Abstract: An audio system is described including an audio processor, an amplifier and a speaker and a distortion estimator. The distortion estimator calculates at least one of an expected response of the amplifier to an audio signal and an expected response of the loudspeaker to an audio signal. The distortion estimator is operable to generate a distortion prediction signal determined by a difference between an expected non-linear response of at least one of the loudspeaker and the amplifier and an expected linear response of at least one of the loudspeaker and the amplifier. A controller coupled to the audio processor and a control input of the audio processor may vary the operating parameters of the audio processor depending on the estimated distortion.

Abstract: A system and method are provided for displaying a frequency response for a sound system design. Coverage map data is processed for a listening area. The coverage map data comprises a plurality of samples. Frequency response data is computed for each sample. The frequency response data is accumulated into a plurality of distributions. A statistical frequency response display is generated based on the distributions.

Abstract: Preventing unintended distribution of audio information may comprise analyzing audio data of a speaker's speech received by a microphone; determining automatically by a processor, from the analyzing whether the speaker's speech is intended to be distributed to an audience via the microphone; and in response to determining that the speaker's speech is not intended to be distributed to the audience via the microphone, performing one or more actions.

Abstract: A storage device includes a storage controller configured to write a band of data tracks using a first recording method until criterion is met. The first method may be a conventional recording method. After the criterion is met, the storage controller is configured to write data to the band using a second recording method. The second recording method may be an enhanced capacity recording method such as interlaced magnetic recording (IMR) or shingled magnetic recording (SMR).

Abstract: Methods, apparatuses, and systems for allowing a single-die preamp to act as two or more virtual preamps for reading or writing data through multiple heads or elements concurrently. A selection register of a preamplifier is set to enable access to a primary register map. Values of registers in the primary register map are set to program a primary preamp channel for performing read or write operations to a first head. The selection register is then set to enable access to a secondary register map, and values of registers in the secondary register map are set to program a secondary preamp channel for performing read or write operations to a second head. Read or write operations can be performed to the first head through the primary preamp channel at a same time that read or write operations are performed to the second head through the second preamp channel.

Abstract: Method and apparatus for positioning shingled magnetic recording (SMR) tracks on a rotatable data storage medium. In some embodiments, a first band of partially overlapping tracks is written the medium at a first track pitch. An adjacent, second band of partially overlapping tracks is written to the medium at the first track pitch. The second band has a first written track at a second track pitch with respect to a last written track in the first band. The second track pitch is determined in response to an error rate established for a test track using an adjacent track written at the first track pitch.

Abstract: Various embodiments of a magnetic stack are disclosed. In one or more embodiments, the magnetic stack includes first and second shield layers, and a magnetically responsive lamination disposed between the first and second shield layers. The magnetically responsive lamination can be configured to receive a sense current IS therethrough. The magnetic stack also includes a cooling element disposed between the first and second shield layers and thermally coupled to the magnetically responsive lamination. The cooling element can be configured to receive a bias current IB therethrough. And the cooling element can be configured to cool the magnetically responsive lamination during a read function.

Abstract: An apparatus according to one embodiment includes a transducer structure having a lower shield and an upper shield above the lower shield, the upper and lower shields providing magnetic shielding. A current-perpendicular-to-plane sensor is positioned between the upper and lower shields. An electrical lead layer is positioned between the sensor and one of the shields. The electrical lead layer is in electrical communication with the sensor. A spacer layer is positioned between the electrical lead layer and the one of the shields. A conductivity of the electrical lead layer is higher than a conductivity of the spacer layer.

Abstract: A computer program product for monitoring head wear includes reading from a cartridge a high frequency pattern and a low frequency pattern, determining a first read amplitude corresponding to the high frequency pattern and a second read amplitude corresponding to the low frequency pattern, and determining a head wear metric according to the first read amplitude and the second read amplitude.

Abstract: Head assembly and magnetic disk device, wherein reaction force induced by warpage of driving element during operation can be decreased and unnecessary resonance can be suppressed, in addition, displacement amount of head element can be efficiently obtained.

Abstract: A recording head includes a layer of plasmonic metal deposited on a surface of the recording head. One or more non-self-supporting layers of crystalline material are attached to the plasmonic metal, the one or more layers of crystalline materials configured to form an active region of a laser. A waveguide is configured to receive plasmons from the laser and direct the plasmons to a recording medium.

Abstract: In one general embodiment, an apparatus includes at least two modules, each of the modules having an array of transducers, wherein the at least two modules are fixed relative to each other, wherein an axis of each array is defined between opposite ends thereof, wherein the axes of the arrays are oriented about parallel to each other, wherein the array of a first of the modules is offset from the array of a second of the modules in a first direction parallel to the axis of the array of the second module such that the transducers of the first module are about aligned with the transducers of the second module in an intended direction of tape travel thereacross; and a mechanism for orienting the modules about an axis orthogonal to the plane in which the arrays reside to control a transducer pitch presented to a tape.

Abstract: An apparatus includes a slider of a recording head comprising a plurality of electrical bond pads coupled to bias sources and a ground pad. Each of a plurality of electrical components of the slider is coupled to at least one of the electrical bond pads. At least one of the electrical bond pads is a shared electrical bond pad coupled to at least two of the electrical components. At least one diode is coupled to at least one of the electrical bond pads and at least one of the electrical components.

Abstract: A slider of a magnetic recording head comprises a plurality of electrical bond pads coupled to bias sources. A first writer on the slider is coupled between first and second bond pads. A second writer on the slider is coupled between third and fourth bond pads. At least one heater is coupled between two of the first, second, third, and fourth bond pads. The first writer can have a center-tap coupled to first and second bond pads. The second writer can have a center-tap coupled to third and fourth bond pads. A first writer heater can be coupled between the center-tap of the second writer and the ground pad. A second writer heater can be coupled between the center-tap of the first writer and the ground pad.

Abstract: An AC signal having a specified frequency and a DC offset voltage is applied to a slider substrate or a magnetic recording medium. A low- or non-modulation interface is defined between the slider and medium. In response to applying the AC signal, an oscillation in an electrostatic force occurs between the slider and the medium at the specified frequency, which causes an oscillation in thermal sensor signal at the slider, which oscillates at the specified frequency. A heater of the slider is adjusted to decrease spacing between the slider and medium during oscillation of the electrostatic force. For each heater adjustment, thermal sensor resistance is measured over a specified number of medium revolutions. Head-medium contact is detected using one of an amplitude of a harmonic of the thermal sensor signal and a summation of amplitudes of all frequency components at the specified frequency.

Abstract: A magnetic recording medium having a thick magnetic recording layer of excellent magnetic characteristics is provided. The magnetic recording medium includes a non-magnetic substrate and a magnetic recording layer. The magnetic recording layer includes a plurality of first magnetic recording layers located at odd-numbered positions from the non-magnetic substrate, and one or more second magnetic recording layers located at even-numbered positions from the non-magnetic substrate. The first magnetic recording layers each have a granular structure that has first magnetic crystal grains with an ordered alloy and a first non-magnetic portion surrounding the first magnetic crystal grains and formed of a material having carbon as main component.

Abstract: A magnetic recording device includes: a magnetic recording medium containing a plurality of recording layers; a magnetic recording head for conducting magnetic writing of information in the magnetic recording medium; and a magnetic reproducing head for conducting magnetic reading out of the information from the magnetic recording medium; wherein the magnetic recording head includes a high frequency oscillator for magnetically assisting the magnetic writing of the information so as to change a magnetization of at least one of the plurality of recording layers of the magnetic recording medium, thereby recording a plurality of information different from one another in the magnetic recording medium commensurate with a total amount of magnetization of the plurality of recording layers.

Abstract: Systems and methods are illustrated for manufacturing hard disks with double lubrication layers that allow minimization of a HDD head DFH touchdown point while maintaining good tribology performance for HDD reliability. An exemplary hard disk includes a magnetic recording layer, a carbon overcoat, and a double lubrication layer: a bonded lubrication layer and a mobile lubrication layer. The bonded lubrication layer includes a high conformity and high density first lubricant. The mobile layer include a high lubricity lubricant that promotes HDI reliability.

Abstract: A magnetic-disk glass substrate of the present invention has a pair of main surfaces, and an arithmetic mean roughness (Ra) for wavelength components of 10 to 50 nm of the surface of the main surfaces is 0.15 nm or less.

Abstract: This recording/reproducing apparatus that records or reproduces information by radiating light to a recording medium is provided with: a medium rotating unit that rotates the recording medium; a moving unit having a movable unit that is capable of moving within a predetermined plane; a rotation angle detecting unit that detects a rotating angle of the recording medium using an angle detection mark that is provided on the recording medium; a position detecting unit that detects a position of the recording medium using an eccentricity detection mark that is provided on the recording medium; and a member for fixing the rotation angle detecting unit and the position detecting unit. With respect to the member, the movable unit relatively moves within a plane substantially parallel to the recording surface of the recording medium, and the medium rotating unit is fixed to the movable unit.

Abstract: A test involves iterations over a series of laser powers of a heat-assisted read/write head. The iterations involve writing to a recording medium at the selected laser power for a sufficient duration to ensure thermal equilibrium of the read/write head at an end of the write. A clearance-control heater of the read/write head is transitioned from a pre-write power before a start of the write to a steady-state write power. The iterations further involve measuring a temperature of the read/write head during the write and adjusting the steady-state write power to achieve a predefined difference between the temperature at the start of the write and the end of the write. The adjusted steady state write power is stored for each iteration. A write-induced protrusion is determined based on the iterations and used for calibration of the read/write head.

Abstract: Systems and methods are disclosed relating to electro-mechanical devices and related computer control and audio processing systems intended to optimize playback fidelity of phonograph records. Said recordings are manufactured by a process that employs a cutting head assembly driven in a straight path from the outer to the inner-most radius of the recordable surface. However, most record turntables device that are used to play back phonograph records rely on a stylus transducer attached to the end of a pivoting arm. Instead of the linear path followed by the original cutting head, said tonearm traces an arc across the surface of the recorded disk resulting in playback distortion proportional to error in alignment of said stylus relative to the tangent of the groove. This invention addresses this deficiency and produces an optimal audio quality of playback of phonograph records.

Abstract: Provided is a method and apparatus for playing contents in an electronic device. The method of playing contents may include displaying a reference image of a content, when sensing a user's input, determining a playback scheme matched with the user's input, and playing the content on the basis of the playback scheme matched with the user's input.

Abstract: A sensor event detection and tagging system that analyzes data from multiple sensors to detect an event and to automatically select or generate tags for the event. Sensors may include for example a motion capture sensor and one or more additional sensors that measure values such as temperature, humidity, wind or elevation. Tags and event detection may be performed by a microprocessor associated with or integrated with the sensors, or by a computer that receives data from the microprocessor. Tags may represent for example activity types, players, performance levels, or scoring results. The system may analyze social media postings to confirm or augment event tags. Users may filter and analyze saved events based on the assigned tags. The system may create highlight and fail reels filtered by metrics and by tags.

Abstract: Embodiments of the present invention relate to a media processing engine that produces an age progression video of a person by using photos of the person. The processing engine sequences and manipulates the photos such that the focus in each chronological photo is on the person. The processing engine uses a sliding window for facial recognition across a wide age range such that pictures of the person at a younger age (e.g., infancy) are positively associated with pictures of the person at an older age (e.g., teenager). In some embodiments, the processing engine is implemented on a remote server that provides a backup or storage service to its members. The photos are located at the remote server. The age progression video can be downloaded and/or shared by a member with others. In some embodiment, the age progression video includes a text caption, such as a message promoting the service.

Abstract: A method, an apparatus and a computer program are provided. The method comprises: causing a computing device to enter a video editing mode in which first video content, captured by a first camera in a location, is played back on a display of the computing device and included in a video edit; and causing the display to overlay at least one visual indicator on the first video content, the at least one visual indicator indicating that second video content, captured by a second camera at the location, is available for inclusion in the video edit.

Abstract: Systems and methods are provided for seamless assembly of video/audio segments. To achieve such seamless assembly during streaming/online progressive download of media, a second segment is downloaded to a client during the presentation of a first segment. The first segment is then attached to the beginning of the second segment, where no jitter or gap results with the transition point either in the video or audio portion of the segments. Hence, the merged segments are presented as a seamless assembly of video/audio segments, where the user is “unaware” that the merged segments are the result of two separate or different segments. To effectuate such gapless assembly of segments, a gapless media file is created for encoding the video and audio segments using a gapless audio encoding scheme, such as Ogg Vorbis, where synchronized, gapless audio tags are interleaved in the video segments.

Abstract: Techniques are described for providing playback of media content based on dynamic multiple video ratings. Scenes of media content can be associated with content indicators describing the types of activities within the scene. The content indicators can be used to generate ratings for scenes of the media content and the ratings can be used to modify playback of the media content, for example, by skipping playback of scenes.

Abstract: A media playback component includes a demultiplexer for receiving a data stream and for demultiplexing media content items provided at a first demultiplexer output and at least one type of non-media content items provided at a second demultiplexer output. The media playback component includes playback queue, a queue input of which is connected to the first demultiplexer output. A bypass input of a queue bypass is connected to the second demultiplexer output. The media playback component includes a decoder including a first decoder input connected to a queue output of the playback queue and a second decoder input connected to a bypass output of the queue bypass. The decoder is configured for decoding the media content items in accordance with commands contained within the at least one type of non-media content items. Further embodiments relate to a method for (distributed) media playback, and to a server component for distributed playback architecture for media data.

Abstract: Methods and systems for generating and applying scene-stable metadata for a video data stream are disclosed herein. A video data stream is divided or partitioned into scenes and a first set of metadata may be generated for a given scene of video data. The first set of metadata may be any known metadata as a desired function of video content (e.g., luminance). The first set of metadata may be generated on a frame-by-frame basis. In one example, scene-stable metadata may be generated that may be different from the first set of metadata for the scene. The scene-stable metadata may be generated by monitoring a desired feature with the scene and may be used to keep the desired feature within an acceptable range of values. This may help to avoid noticeable and possibly objectionably visual artifacts upon rendering the video data.

Abstract: A data storage system includes a recording head and a compensating resistor. The recording head has a heating element. The compensating resistor is in electrical series with the heating element and is external to the recording head. A method includes applying an alternating current at a first angular frequency to a recording head. A voltage drop across the recording head heating element is measured. A component of the voltage drop is extracted. The component has a frequency that is three times the frequency of the first angular frequency.

Abstract: A data storage carrier includes a middle member with at least one handle between ends of the middle member. Side members are coupled to the respective ends of the middle member via living hinges. The side members each include at least two protrusions configured to interface with side mounting holes of a data storage drive. The living hinges are bendable so that the protrusions interface with the side mounting holes of the drive and the middle member interfaces with a back side of the drive.

Abstract: The invention relates to a storage case comprising two parts, each with an outer side and an inner side, where a side area on each part may comprise a connecting element for hinged connection with the other part, where at least one of the two parts on the outer side comprises a circumferential frame connectable with the part and with a central aperture and where further a display element is positioned on the outer side of the at least one part and interlocked between the outer side and the frame connectable to the part.

Abstract: A disc-drive enclosure system comprising an enclosure assembly having an interior area, a divider separating the interior area into two chambers. An opening in the divider receives the end of a disc drive the a disc tray being openable into the first chamber, while the disc drive's body remains in the second chamber. A sled assembly in the enclosure assembly support the disc drive and is movable relative to the divider between first and second positions. The sled assembly has a sealing member coupled to a leading end portion and positioned to form a seal around the drive opening when the sled assembly is in the first position with the end portion of the housing in the first chamber and the body portion in the second chamber.

Abstract: A memory circuit includes a first bit line, a second bit line, and a memory cell that is coupled to first bit line and the second bit line. The memory cell includes a capacitor, a first pass gate transistor, a non-volatile (NV) element, and a second pass gate transistor. The first capacitor has a first terminal coupled to a first storage node and a second terminal coupled to a reference. The first pass gate transistor is coupled between the first bit line and the first storage node. The NV element and a second pass gate transistor are coupled in series, wherein the first NV element and the second pass gate transistor are coupled between the first storage node and the first program line.

Abstract: A memory device and techniques for its operation are presented. After operating on power received from a host, the memory device determines that it is no longer receiving host power and, in response, activates a power source on the memory device itself. Using this reserve power, the memory device can then perform data management operations. The techniques can also be applied to a digital appliance having a non-volatile memory. The memory device or digital appliance can prioritize its memory management operation during the host/user operating window based on the ability to perform these operations outside of the host/user operating window.

Abstract: The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a controller. The controller is configured to provide power and power availability information to the memory, and the memory is configured to determine whether to adjust its operation based, at least in part, on the power availability information.

Abstract: An input/output circuit according to an embodiment includes a plurality of memory cell units configured to independently perform output operations, each of the memory cell units including an input/output line, a selection circuit including a plurality of selection units, each selection unit setting a path to a global input/output line connected to each of the selection units, the number of the selection units being the same as the number of the memory cell units, the selection circuit selecting one of the plurality of memory cell units based on a path control signal and electrically connecting the input/output line of the selected memory cell unit to the global input/output lines of the plurality of selection units, and a plurality of input/output pad groups coupled to the global input/output lines.

Abstract: A memory device includes a plurality of channels that respectively include memory cell arrays and local input/output lines electrically coupled to the memory cell arrays and are independently operable, shared global input/output lines electrically coupled to the local input/output lines included in the plurality of channels and having a connection relation controlled through one or more path switch circuits arranged among the plurality of channels, and the path switch circuits that control the connection relation of the shared global input/output lines according to a path control signal.

Abstract: Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage representative of data to be placed on the first line and then precharged to a first precharge voltage. A second line is configured to be driven to a second voltage representative of data to be placed on the second line and then precharged to a second precharge voltage. A charge sharing device is coupled between the first line and the second line. The charge sharing device is configured to selectively allow charge from the first line to flow to the second line after the first and second lines are driven to the respective first and second voltages representative of data to be placed on the respective lines.

Abstract: According to one embodiment, a semiconductor memory device includes first, second, third and fourth MOS transistors, and first and second precharge circuits. A memory cell includes the first, second, third and fourth MOS transistors. Source and drain of the third MOS transistor are connected to between the source or the drain of the first MOS transistor and a first bit line. Source and drain of the fourth MOS transistor are connected to between the source or the drain of the second MOS transistor and a second bit line. The first precharge circuit supplies a voltage to the first and second bit lines in a precharge period during a read operation or a write operation. The second precharge circuit supplies the voltage to the first and second bit lines while in a data holding state.

Abstract: A data input circuit may include a data latch unit suitable for latching input data as latch data in response to first and second latch signals; a data signal generation unit suitable for outputting first and second data signals corresponding to the latch data; a first drive unit suitable for pulling up or down a first input/output data line of an input/output data line pair in response to the first and second data signals; and a second drive unit suitable for pulling up or down a second input/output data line of the input/output data line pair in response to the first and second data signals, wherein the first and second drive units adjust pull-up levels of the first and second input/output data lines in response to a data input control signal.

Abstract: Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors.

Abstract: An apparatus for controlling memory includes a memory controller, and a data interface that interfaces with and is in data communication with data lines, each having inherent skew. Each data line carries a data signal. The data lines connect the memory controller to the memory. The apparatus also includes data de-skewers, each associated with a corresponding data line, a strobe interface that interfaces with a strobe line that connects the memory controller to the memory and that applies a timing signal to the strobe line, and a strobe de-skewer connected to the strobe line. Each data de-skewer operates in read or write mode. A particular data line's data de-skewer applies a compensation skew to a data signal carried by that line.

Abstract: Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices. Controller-side and memory-side embodiments of such channel interfaces are disclosed which require a low pin count and have low power utilization. In some embodiments of the invention, different voltage, current, etc. levels are used for signaling and more than two levels may be used, such as a vector signaling code wherein each wire signal may take on one of four signal values.

Abstract: A method and an apparatus for generating an internal memory clock are provided. The apparatus includes a pulse generator configured to receive a first clock signal in a first power domain and initiate a second clock signal in a second power domain in response to the first clock signal. The first power domain provides a first voltage for logic operations and the second power domain provides a second voltage for memory operations. The apparatus includes a tracking circuit configured to generate a reset signal based on a voltage level of the first power domain. The reset signal may be configured to reset the pulse generator in the first power domain. The apparatus may further include a latch configured to receive the second clock signal in the second power domain.

Abstract: A read/write control device of resistive type memory includes a first logic unit and a second logic unit. In a bit line driving circuit, the first logic unit is connected to a gate of a first transistor set for outputting a bit line signal, wherein the first transistor set includes one PMOS and one NMOS serially connected to each other. The first logic unit has a pair of input terminals respectively for receiving a column selection signal and receiving a control signal that decides if data “0” is to be written. In a source line driving circuit, the second logic unit is connected to a gate of a second transistor set for outputting a source line signal, wherein the second transistor set includes one PMOS and one NMOS serially connected to each other. The second logic unit has a pair of input terminals respectively for receiving a column selection signal and receiving a control signal that decides if data “1” is to be written.

Abstract: A non-volatile memory system includes a first circuit and a second circuit both coupled to a magnetoresistance tunnel junction (MTJ) cell to substantially reduce the level of current flowing through the MTJ with rise in temperature, as experienced by the MTJ. The first circuit is operable to adjust a slope of a curve representing current as a function of temperature and the second circuit is operable to adjust a value of the current level through the MTJ to maintain current constant or to reduce current when the temperature increases. This way sufficient current is provided for the MTJ at different temperatures, to prevent write failure, over programming, MTJ damage and waste of current.

Abstract: An example apparatus includes an address counter configured to provide refresh addresses to a refresh circuit, wherein the address counter includes a plurality of counter cells configured to count through count values between a minimum count value to a maximum count value, wherein an output of each of the plurality of counter cells each corresponds to an address bit of the refresh address, and a reset circuit coupled to a counter cell of the plurality of counter cells, wherein the reset circuit is configured to reset the counter cell of the plurality of counter cells to an initial value responsive to the plurality of counter cells changing from a first count value to a second count value to skip at least some of the count values to provide the refresh addresses, wherein the first and second count values are less than the maximum count value.

Abstract: A method of operating a semiconductor memory device is provided as follows. The semiconductor memory device receive a bank address for a first bank including a first word line, a second word line and a third word line. The semiconductor memory device receive a first row address to activate the first world line for a read operation or a write operation. The semiconductor memory device generates a second row address to refresh a plurality of memory cells associated with the second word line.