Abstract: A method of surface functionalization for high-k deposition is provided in several embodiments. The method provides interface layer growth with low effective oxide thickness and good nucleation behavior for high-k deposition. The method includes providing a substrate that is at least substantially free of oxygen on a surface of the substrate, forming an interface layer on the surface of the substrate by exposing the surface of the substrate to one or more pulses of ozone gas, modifying the interface layer by exposing the interface layer to one or more pulses of a treatment gas containing a functional group to form a functionalized interface layer terminated with the functional group, and depositing a high-k film on the functionalized interface layer.

Abstract: There is provided a method of forming a germanium (Ge) film on a surface of a target object, which includes: supplying an aminosilane-based gas into a processing chamber in which the target object is loaded; supplying a high-order silane-based gas of disilane or higher into the processing chamber; and supplying a Ge source gas into the processing chamber. A process temperature in supplying the Ge source gas is set to fall within a range from a temperature, at which the Ge source gas is thermally decomposed or higher, to 300 degrees C. or less.

Abstract: A method for depositing an aluminium nitride layer on a substrate is provided that comprises: providing a silicon substrate; placing the substrate in a vacuum chamber; conditioning a surface of the substrate by etching and providing a conditioned surface; depositing an aluminum film onto the conditioned surface of the substrate by a sputtering method under an atmosphere of Argon and depositing an epitaxial aluminium nitride layer on the aluminum film by a sputtering method under an atmosphere of Nitrogen and Argon.

Abstract: Provided is an epitaxial wafer manufacturing device (1) that deposits and grows epitaxial layers on the surfaces of wafers W while supplying a raw material gas to a chamber, wherein a shield (12), arranged in close proximity to the lower surface of a top plate (3) so as to prevent deposits from being deposited on the lower surface of the top plate (3), is removably attached inside the chamber, has an opening (13) in the central portion thereof that forces a gas inlet (9) to face the inside of a reaction space K, and has a structure in which it is concentrically divided into a plurality of ring plates (16), (17) and (18) around the opening (13).

Abstract: The method includes performing a photolithography process which includes using a photomask to pattern a radiation beam. The photolithography process also includes exposing a target substrate to the patterned radiation beam. During the exposing of the target surface, there is a real-time monitoring for particles incident or approximate the photomask.

Abstract: A method for etching an antireflective coating on a substrate is disclosed. The substrate comprises an organic layer, an antireflective coating layer disposed above the organic layer, and a photoresist layer disposed above the antireflective coating layer. The method includes patterning the photoresist layer to expose a non-masked portion of the antireflective coating layer and selectively depositing a carbon-containing layer on the non-masked portions of the antireflective coating layer and on non-sidewall portions of the patterned photoresist layer. The method further includes etching the film stack to remove the carbon-containing layer and to remove a partial thickness of the non-masked portions of the antireflective coating layer without reducing a thickness of the photoresist layer.

Abstract: A transistor including a gate structure with a first portion and a second portion; the first and second portions each have a first edge and an opposing second edge that are substantially collinear. The gate structure also includes an offset portion interposing the first portion and the second portion. The offset portion has a third edge and an opposing fourth edge. The third edge and the fourth edge are non-collinear with the first and second edges of the first and second portions of the gate structure. For example, the offset portion is offset or shifted from the first and second portions.

Abstract: A manufacturing method of a semiconductor device includes: forming an electric metal layer by depositing metal as art electrode material on an inside of an opening of an insulating layer on a surface of an SiC semiconductor substrate; widening a gap between an inner wall surface in an opening formed in the insulating layer and the electrode metal layer by etching the insulating layer after the electrode metal layer is formed; and forming an ohmic contact between the electrode metal layer and the SiC semiconductor substrate by heating the SiC semiconductor substrate and the metal electrode layer after the insulating layer is etched.

Abstract: A method for protecting a doped silicate glass layer includes: forming a doped silicate glass layer on a substrate in a reaction chamber by plasma-enhanced atomic layer deposition (PEALD) using a first RF power; and forming a non-doped silicate glass layer having a thickness of less than 4 nm on the doped silicate glass layer in the reaction chamber, without breaking vacuum, by plasma-enhanced atomic layer deposition (PEALD) using a second RF power, wherein the second RF power is at least twice the first RF power.

Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

Abstract: An N-type Lateral Diffused Metal-Oxide-Semiconductor (NLDMOS) transistor is provided. The NLDMOS transistor comprises a P-type substrate; and a semiconductor layer having a deep N-type well region formed on the P-type substrate. Further, the NLDMOS transistor also includes at least a P-type body region and an N-type drift region formed in the deep N-type well region; and an N-type heavily doped drain region formed in the N-type drift region. Further, the NLDMOS transistor includes a P-type doped reverse type region formed below the N-type drift region in the deep N-type well region, being physically connected with the first P-type body region, and preventing carriers from escaping between the N-type source region and external devices.

Abstract: A method for forming spacers of a gate of a transistor is provided, including forming a protective layer covering the gate; after the forming the protective layer, at least one step of forming a carbon film on the transistor; removing portions of the carbon film located on a top and on either side of the gate; modifying the protective layer on the top of the gate and on either side of the gate; and removing the modified protective layer.

Abstract: Provided is a semiconductor device and a method of fabricating the same. The method may include forming trenches in a substrate and lower gate patterns on the substrate between the trenches, forming sacrificial patterns filling the trenches, forming a porous insulating layer on the lower gate patterns to cover top surfaces of the sacrificial patterns, removing the sacrificial patterns through pores of the porous insulating layer to form air gaps surrounded by the trenches and the porous insulating layer, and forming a liner insulating layer on inner surfaces of the trenches through the pores of the porous insulating layer.

Abstract: A method of forming a metal silicide can include depositing an interface layer on exposed silicon regions of a substrate, where the interface layer includes a silicide forming metal and a non-silicide forming element. The method can include depositing a metal oxide layer over the interface layer, where the metal oxide layer includes a second silicide forming metal. The substrate can be subsequently heated to form the metal silicide beneath the interface layer, using silicon from the exposed silicon regions, the first silicide forming metal of the interface layer and the second silicide forming metal of the metal oxide layer.

Abstract: A method of patterning a silicon containing ARC (anti-reflective coating) layer underlying a patterned layer is described that includes establishing a flow of a process gas to a plasma processing system, selecting a process condition that increases an etch selectivity of the silicon containing ARC layer relative to the patterned layer, igniting plasma from the process gas using a plasma source in accordance with the process condition, and exposing the substrate to the plasma to extend the feature pattern of the patterned layer into the silicon containing ARC layer. The composition of the process gas and the flow rate(s) of the gaseous constituents in the process gas are selected to adjust the carbon-fluorine content.

Abstract: The method includes holding a substrate horizontally with a holding and rotating mechanism; introducing processing liquid from a fluid introduction portion of, in a processing liquid pipe in which a processing liquid nozzle having a discharge port at a tip end is provided at one end, the other end of the processing liquid pipe into the processing liquid pipe so as to discharge the processing liquid from the discharge port toward the substrate; introducing, after stopping the processing liquid discharge step, a gas from the fluid introduction portion into the processing liquid pipe so as to extrude the processing liquid within the processing liquid pipe and within the processing liquid nozzle outwardly; and stopping, after starting the introduction of the gas, the introduction of the gas into the processing liquid pipe with the processing liquid being left within the processing liquid pipe and/or the processing liquid nozzle.

Abstract: A device includes a crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by using a planarization process configured with a selectivity of the crystalline material to the insulator greater than one. In a preferred embodiment, the planarization process uses a composition including abrasive spherical silica, H2O2 and water. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique.

Abstract: A cavity is formed in a semiconductor substrate wherein the width of the cavity is greater than the depth of the cavity and wherein the depth of the cavity is non uniform across the width of the cavity. The cavity may be formed under an electronic device in the semiconductor substrate. The cavity is formed in the substrate by performing a first cavity etch followed by repeated cycles of polymer deposition, cavity etch, and polymer removal.

Abstract: A method for etching features with different aspect ratios in an etch layer is provided. A plurality of cycles is provided wherein each cycle comprises a pre-etch transient conditioning of the etch layer, which provides a transient condition of the etch layer, wherein the transient condition has a duration and etching the etch layer for a duration, wherein the duration of the etching with respect to the duration of the transient condition is controlled to control etch aspect ratio dependence.

Abstract: A pattern-forming method includes providing a resist underlayer film on a substrate using a resist underlayer film-forming composition. The resist underlayer film-forming composition includes a first polymer having a glass transition temperature of 0 to 180° C. A silicon-based oxide film is provided on a surface of the resist underlayer film. A resist pattern is provided on a surface of the silicon-based oxide film using a resist composition. The silicon-based oxide film and the resist underlayer film are sequentially dry-etched using the resist pattern as a mask. The substrate is dry-etched using the dry-etched resist underlayer film as a mask.

Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a first hard mask layer over a semiconductor device layer, forming a set of mandrels over the first hard mask layer, and forming a first spacer layer over the set of mandrels and the first hard mask layer. The method further includes forming a second spacer layer over the first spacer layer, patterning the first spacer layer and the second spacer layer to form a mask pattern, and patterning the first hard mask layer using the mask pattern as a mask.

Abstract: Disclosed is a method for removing a polysilicon protection layer (12) on a back face of an IGBT having a field stop structure (10). The method comprises thermally oxidizing the polysilicon protection layer (12) on the back face of the IGBT until the oxidation is terminated on a gate oxide layer (11) located above the polysilicon protection layer (12) to form a silicon dioxide layer (13), and removing the formed silicon dioxide layer (13) and the gate oxide layer (11) by a dry etching process. The method for removing the protection layer is easier to control.

Abstract: Target pattern layouts that include lower and upper target patterns are designed. Each lower target pattern is combined with a upper target pattern that at least partially overlaps a top surface thereof to form combination structures. The combination structures are divided into first and second combination structures. A first target pattern is formed from the lower target pattern in the first combination structure and a third target pattern is formed from the upper target pattern in the first combination structure. The first and third target patterns are formed in first and third lithography processes, respectively. A second target pattern is formed from the lower target pattern in the second combination structure and a fourth target pattern is formed from the upper target pattern in the second combination structure. The second and fourth target patterns are formed in second and fourth lithography processes, respectively.

Abstract: A patterning method using a metal mask includes sequentially forming a lower metal layer and an upper metal layer on an etching object layer, forming an upper metal mask, forming the upper metal mask including patterning the upper metal layer, forming a lower metal mask, forming the lower metal mask including patterning the lower metal layer using the upper metal mask, and patterning the etching object layer using the upper metal mask.

Abstract: A method comprises providing a handle substrate having a front surface and a back surface; providing a layer of flexible semiconductor material having a front surface and a back surface and an at least partially sacrificial backing layer stack on the back surface of the layer of flexible semiconductor material; bonding the front surface of the layer of flexible semiconductor material to the front surface of the handle substrate; removing at least a portion of the at least partially sacrificial backing layer stack from the back surface of the layer of flexible semiconductor material; opening outgassing paths through the layer of flexible semiconductor material; and processing the layer of flexible semiconductor material.

Abstract: An etching method includes: disposing a target substrate including a silicon and a silicon-germanium within a chamber; and performing both of selectively etching the silicon-germanium with respect to the silicon and selectively etching the silicon with respect to the silicon-germanium by varying ratios of F2 gas and NH3 gas in an etching gas that has a gas system including the F2 gas and the NH3 gas.

Abstract: Methods are described herein for selectively etching titanium nitride relative to dielectric films, which may include, for example, alternative metals and metal oxides lacking in titanium and/or silicon-containing films (e.g. silicon oxide, silicon carbon nitride and low-K dielectric films). The methods include a remote plasma etch formed from a chlorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the titanium nitride. The plasma effluents react with exposed surfaces and selectively remove titanium nitride while very slowly removing the other exposed materials. The substrate processing region may also contain a plasma to facilitate breaking through any titanium oxide layer present on the titanium nitride. The plasma in the substrate processing region may be gently biased relative to the substrate to enhance removal rate of the titanium oxide layer.

Abstract: The invention provides a method of forming at least one Metal Germanide contact on a substrate for providing a semiconducting device (100) by providing a first layer (120) of Germanium (Ge) and a second layer of metal. The invention provides a step of reacting the second layer with the first layer with high energy density pulses for obtaining a Germanide metal layer (160A) having a substantially planar interface with the underlying first (Ge) layer.

Abstract: Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.

Abstract: A method for fabricating an electronic package structure is provided, which includes the steps of: forming a circuit layer on a conductor; disposing an electronic element on the circuit layer; forming an insulating layer on the conductor to encapsulate the electronic element and the circuit layer; and removing portions of the conductor so as to cause the remaining portions of the conductor to constitute a plurality of conductive bumps. As such, when the electronic package structure is disposed on a circuit board through an SMT (Surface Mount Technology) process, the conductive bumps are easily aligned with contacts of the circuit board, thereby effectively improving the yield of the SMT process.

Abstract: A method of manufacturing a semiconductor device, including steps of: (a) bonding a support plate to a first main face of a wafer, the first main face having an integrated circuit disposed thereon; (b) thinning the wafer by polishing or grinding a second main face after step (a), the second main face being opposite to the first main face; (c) dividing the wafer into multiple chip bodies concurrently with or after step (b); (d) bonding multiple reinforcing layers to second main faces of the respective chip bodies after step (c); and (e) removing the support plate after step (d).

Abstract: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, a method can include: providing a precursor interconnect structure having: a photosensitive polyimide (PSPI) layer; a controlled collapse chip connection (C4) bump overlying the PSPI layer; and a solder overlying the C4 bump and contacting a side of the C4 bump. The method can further include recessing a portion of the PSPI layer adjacent to the C4 bump to form a PSPI pedestal under the C4 bump. The method can additionally include forming an underfill abutting the PSPI pedestal and the C4 bump, wherein the underfill and the solder form an interface separated from the PSPI pedestal.

Abstract: Integrated circuit packages with cavity are disclosed. A disclosed integrated circuit package includes a first die. A second die may be coupled to the first die by attaching the first die to a top surface of the second die. A blocking element such as a barrier structure may be formed that surrounds the second die. A cavity may be formed between the blocking element and the first die that encloses the second die. The barrier structure may help prevent underfill material from entering the cavity during underfill deposition processes. A heat spreading lid may cover the first die, second die and package substrate.

Abstract: The present disclosure is directed to fluid filtering systems and methods for use during semiconductor processing. One or more embodiments are directed to fluid filtering systems and methods for filtering ions and particles from a fluid as the fluid is being provided to a semiconductor wafer processing tool, such as to a semiconductor wafer cleaning tool.

Abstract: A substrate processing device 100 includes a cleaning liquid supply unit 114 supplying a cleaning liquid to a surface of a substrate W, a solvent supply unit 115 supplying a volatile solvent to the surface of the substrate W supplied with the cleaning liquid to replace the cleaning liquid on the surface of the substrate W with the volatile solvent, a heating unit 117 heating the substrate W supplied with the volatile solvent, and a drying unit 118 drying the surface of the substrate W by removing a droplet of the volatile solvent produced on the surface of the substrate W by a heating operation of the heating unit 117, and the heating unit 117 and the drying unit 118 are arranged in a course of transportation of the substrate W transported from the solvent supply unit 115.

Abstract: A plasma processing apparatus includes a process container configured to accommodate a target substrate and to be vacuum-exhausted. A first electrode and a second electrode are disposed opposite each other within the process container. The first electrode includes an outer portion and an inner portion both facing the second electrode such that the outer portion surrounds the inner portion. An RF power supply is configured to apply an RF power to the outer portion of the first electrode. A DC power supply is configured to apply a DC voltage to the inner portion of the first electrode. A process gas supply unit is configured to supply a process gas into the process container, wherein plasma of the process gas is generated between the first electrode and the second electrode.

Abstract: The invention provides a substrate processing device and a substrate processing method for cooling a substrate, which are capable of conveying a substrate in a cleaner condition. A substrate cooling device serving as a substrate processing device of an embodiment of the invention includes: a chamber; a cooling unit which performs cooling; a substrate holder which is provided with a substrate mounting surface for mounting a substrate inside the chamber, and is cooled by the cooling unit; and a shield which is provided with a side surface portion surrounding a lateral side of the substrate mounting surface inside the chamber, and is cooled by the cooling unit. Moreover, a shield heater is provided in the vicinity of a surface on the inside of the shield.

Abstract: The present invention provides a substrate heat treatment apparatus capable of uniformly heat a substrate at high speed with less breakage of constituent members due to thermal expansion even at high temperature. An embodiment of the present invention is a substrate heat treatment apparatus to perform heat treatment for a substrate and includes: a peripheral ring capable of supporting the substrate; a connection ring; a lifting device to raise and lower the peripheral ring; balls having a lower heat conductivity than that of the peripheral ring; and a lamp to heat the substrate supported by the peripheral ring. The balls are different members from both of the peripheral ring and the connection ring. The lifting device raises and lowers the peripheral ring between a first position close to the lamp and a second position distant from the lamp.

Abstract: An object of the present disclosure is to reduce a footprint. A bonding system of the present disclosure includes a first processing station, a second processing station, and a carry-in/out station. The first processing station includes a first conveyance region, a coating device, a heating device, and a first delivery block. The second processing station includes a plurality of bonding devices, a second conveyance region, and a second delivery block. Each of the plurality of bonding devices bonds the first substrate to the second substrate. The second conveyance region is a region configured to convey the first substrate and the second substrate to and from the plurality of bonding devices. The second delivery block delivers the first substrate, the second substrate and the superimposed substrate between the first conveyance region and the second conveyance region.

Abstract: A flash heating part in a heat treatment apparatus includes 30 built-in flash lamps, and irradiates a semiconductor wafer held by a holder in a chamber with a flash of light. Thirty switching elements are provided in a one-to-one correspondence with the 30 flash lamps. Each of the switching elements defines the waveform of current flowing through a corresponding one of the flash lamps by intermittently supplying electrical charge thereto. Radiation thermometers measure an in-plane temperature distribution of the semiconductor wafer during flash irradiation. Based on the results of measurement with the radiation thermometers, a controller individually controls the operations of the 30 switching elements to individually define the light emission patterns of the 30 flash lamps.

Abstract: An object is to prevent down flow gas from entering into a pod in an open state in an EFEM system. An upper canopy is provided along the upper edge of an opening portion on the mini-environment side to block down flow along the opening portion. The upper canopy provides a space in which inert gas supplied through a supply port provided in the pod flows into the mini-environment through the opening of the pod after circulating inside the pod. The down flow has no effect in this space, and the entrance of down flow into the pod can be prevented.

Abstract: An inline system including a first apparatus having a first processing unit for processing a workpiece and an unloading area for unloading the workpiece processed by the first processing unit, a second apparatus having a loading area for loading the workpiece unloaded from the unloading area and a second processing unit for processing the workpiece loaded to the loading area, a transfer unit for transferring the workpiece from the unloading area to the loading area, and a position detecting unit for imaging the unloading area to detect the position of the unloading area and also imaging the loading area to detect the position of the loading area. The transfer unit transfers the workpiece from the unloading area to the loading area according to the position of the unloading area and the position of the loading area detected by the position detecting unit.

Abstract: An apparatus includes a body and a surface for receiving a semiconductor wafer carrier is provided. A nozzle and a venting hole are provided on the surface. The semiconductor wafer carrier has at least one selectively closable capped opening at a bottom, top and/or side surface thereof. The capped opening is configured to couple to, and be accessible by, the nozzle and receive gas output from the nozzle so as to create a substantially oxygen free environment within the semiconductor wafer carrier. The vent hole is configured to allow gas to flow out of the semiconductor wafer carrier. In addition, the apparatus includes a sensor and a controller. The sensor is configured to monitor an ambient condition in the semiconductor wafer carrier, and the controller is configured to adjust a control valve based on the ambient condition so as to control the gas flow or output from the nozzle.

Abstract: A plasma processing apparatus includes a stage in a processing chamber where plasma is formed, a wafer to be processed, and an electrode arranged at an upper part of the stage and supplied with power to electrostatically attract and hold the wafer on the stage, and consecutively processing a plurality of wafers one by one. There are plural processing steps of conducting processing using the plasma under different conditions and there are plural periods when formation of plasma is stopped between the processing steps. An inner wall of the processing chamber is coated before starting the processing of any wafer, and voltage supplied to the electrode is changed according to a balance of respective polarities of particles floating and charged in the processing chamber in each period when formation of plasma is stopped.

Abstract: An adhesive composition for temporarily attaching a substrate to a support plate which supports the substrate, and includes a thermoplastic resin and a release agent.

Abstract: Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.

Abstract: The present invention provides a substrate structure, a semiconductor device, and a manufacturing method thereof. The substrate structure comprises: a semiconductor substrate; and a first isolation region, wherein the first isolation region comprises: a first trench extending through the semiconductor substrate; and a first dielectric layer filling the first trench. Due to the isolation region extending through the substrate, it is possible to make device structures on both surfaces of the substrate, so as to increase the utilization of the substrate and the integration degree of the devices.

Abstract: One or more methods of forming shallow trench isolation (STI) and resulting semiconductor arraignments are provided. A method of forming STI includes forming a nitride liner in a first opening and second opening and recessing the nitride liner in the first opening and second opening while forming an oxide structure in the first opening and second opening, thus forming a first STI region in the first opening and a second STI region in the second opening. A semiconductor arraignment includes a first STI region in an active area and a second STI region in an isolation area, where a first recessed nitride layer height in the first STI region is different than a second recessed nitride layer height in the second STI region.

Abstract: A process for fabrication of a structure includes assembling at least two substrates. At least one of these two substrates is intended to be used in electronics, optics, optoelectronics and/or photovoltaics. The structure includes at least two separation interfaces extending parallel to the main faces of the structure. The assembling process is carried out with a view to a separation of the structure along one interface selected from the interfaces, the separation being carried out by inserting a blade between the substrates and applying a parting force, via the blade. The interface chosen for the separation is formed so that it is more sensitive than the other interface(s) to stress corrosion. Separation occurs due to the combined action of the parting force and of a fluid capable of breaking siloxane (Si—O—Si) bonds present at the interface. A structure obtained by such a process may be separated along the chosen interface.

Abstract: A method of manufacturing a silicon-on-insulator (SOI) substrate is provided. The method includes forming an island-shaped insulating layer on a first surface of a first semiconductor substrate in a first region, forming a silicon epitaxial layer on the first surface of the first semiconductor substrate so as to cover the island-shaped insulating layer, forming a trench by etching the silicon epitaxial layer so as to expose the island-shaped insulating layer, and forming a first insulating adhesive layer on the silicon epitaxial layer and the island-shaped insulating layer so as to fill the trench.