Patents Issued in March 28, 2017
  • Patent number: 9607679
    Abstract: A refresh control device is disclosed, which relates to a technology for efficiently storing weak cell refresh addresses. The refresh control device includes a weak cell address storage circuit to store a weak address, a weak cell address control circuit, and a row address control circuit. The weak cell address control circuit outputs a weak enable signal and a row address by comparing a refresh address with the weak address, and only activates the refresh address according to the comparison result or activates both the refresh address and the row address. The row address control circuit controls a refresh operation by selectively activating a word line of a bank in response to the refresh address, the weak enable signal, and the row address.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: March 28, 2017
    Assignee: SK HYNIX INC.
    Inventors: Youk Hee Kim, Jun Gi Choi
  • Patent number: 9607680
    Abstract: One or more integrated circuits including at least one integrated circuit that is fabricated in a DRAM fabrication process. Capacitors in the DRAM-fabricated integrated circuit can be used for decoupling for logic components of the integrated circuits, and may be used for fine-grain on-chip PMUs. The capacitors may be physically placed near the logic components for which the capacitors are providing decoupling capacitance, in an embodiment. The capacitors may be series connections of at least two capacitors, or at least one capacitor and a switch, to provide decoupling capacitance in the face of defects, in an embodiment. Embedded DRAM memories can be used instead of SRAM memories, with increased density and reduced leakage. More compact systems can be implemented using the integrated circuits.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: March 28, 2017
    Assignee: Apple Inc.
    Inventor: Sanjay Dabral
  • Patent number: 9607681
    Abstract: A memory device comprises: a plurality of memory configuration modes; an option selection logic for selecting one of the plurality of memory configuration modes to operate the memory device; and bonding pads. The bonding pads are connected to inputs of the option selection logic. The bonding pads are configurable to allow for a default mode selection for the selected one of the plurality of memory configuration modes to operate the memory device.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: March 28, 2017
    Assignee: EVERAM TECHNOLOGY INC.
    Inventors: Adrian E. Ong, Byeong Cheol Na, Tim Lao
  • Patent number: 9607682
    Abstract: A decoder is disclosed that is used to select an area of address space in an Integrated Circuit. The decoder uses a hardware shifting module that performs shift operations on constants. Such a structure reduces an overall area consumption of the shifting module. Additionally, the decoder can perform a multi-bit shift operation in a single clock cycle.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: March 28, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Ron Diamant, Jonathan Cohen, Elad Valfer
  • Patent number: 9607683
    Abstract: In some embodiments, a semiconductor device includes an SRAM cell, an emulator and a suppressing device. The SRAM cell, enabled by a word line, includes a first inverter formed by a first PMOS transistor and a first NMOS transistor and stores a first data at an output of the first inverter. The emulator is configured to emulate the first inverter operating in a condition that the PMOS transistor is weaker than the first NMOS transistor in driving strength. The suppressing device is configured to, in response to a voltage at an output of the emulator, selectively suppress a voltage level of the word line.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: March 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hidehiro Fujiwara, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 9607684
    Abstract: A method for predicting a condition in a circuit under design includes obtaining a set comprising first static noise margin curve for the circuit and a second static noise margin curve for the circuit, wherein the second static noise margin curve is complementary to the first static noise margin curve, matching the set to a two-dimensional model of a cell, and predicting the condition in accordance with hardware characterization data corresponding to the cell.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Rajiv V. Joshi, Keunwoo Kim
  • Patent number: 9607685
    Abstract: A memory array comprises a plurality of memory cells arranged in columns and rows. The memory array also comprises a plurality of first-type strap cells arranged in a row, wherein each first-type strap cell comprises a first-type well strap structure. The memory array further comprises a plurality of second-type strap cells arranged in a row. Each second-type strap cell comprises a second-type well strap structure. Each column of memory cells is bracketed by at least one first-type strap cell of the plurality of first-type strap cells or at least one second-type strap cell of the plurality of second-type strap cells.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: March 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9607686
    Abstract: A semiconductor memory device includes data path circuits and control circuits alternately disposed along a first direction. A first metal layer is disposed on the data path circuits and control circuits. Each of data path circuits includes a memory cells disposed in rows along the first direction and columns along a second direction crossing the first direction and a read/write circuit disposed at an end of the columns of memory cells. At least one pair of adjacent columns of memory cells has an electrical separation between the gate polysilicon layer the pair of adjacent memory cell columns—that is, gate conductor layer of the adjacent memory columns are electrically distinct. A word line in the first metal layer is segmented along the first direction into separately addressable portions.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: March 28, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yukihiro Fujimoto
  • Patent number: 9607687
    Abstract: In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: March 28, 2017
    Assignee: Intel Corporation
    Inventors: Pramod Kolar, Gunjan H. Pandya, Uddalak Bhattacharya, Zheng Guo
  • Patent number: 9607688
    Abstract: According to example embodiments, a nonvolatile memory includes a plurality of memory cells and a plurality of bit lines respectively connected to the plurality of memory cells, and a method of programming the nonvolatile memory includes loading data to the nonvolatile memory for a first program operation, starting the first program operation on the plurality of memory cells, based on the loaded data, and loading at least two page data to the nonvolatile memory before the first program operation is completed. The at least two page data include first page data and second page data for a second program operation following the first program operation. The first page data and the second page data respectively correspond to a first bit and a second bit to be programmed at a memory cell among the plurality of memory cells.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: March 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Donghun Kwak
  • Patent number: 9607689
    Abstract: A method comprises steps of mapping a same physical page to two mutually coupled logic pages, one logic page being formed by mapping the least significant bit on the physical page, and the other logic page being formed by mapping the most significant bit on the physical page; buffering write data in a buffer memory, and merging the data, which is corresponding to the two mutually coupled logic pages, in the buffer memory into a piece of data corresponding to the physical page according to the mapping relationship between the physical page and the two mutually coupled logic pages; and performing charging/discharging control for the multi-layer memory cell of the physical page according to the merged data, so that a voltage state of the multi-layer memory cell is expressed as a numerical value of the merged data.
    Type: Grant
    Filed: April 28, 2013
    Date of Patent: March 28, 2017
    Assignee: Ramaxel Technology (Shenzhen) Limited
    Inventor: Ming Jin
  • Patent number: 9607690
    Abstract: Provided are modified one-hot (MOH) constructions for WOM codes with low encoding and decoding complexity, that achieve high sum-rates. Features include maximizing writing of data information values for successive rewrites, all-zero and all-one cell state vectors that represent a unique data information value that can be written for many generations, a very high number of writes, and does not sacrifice capacity. One embodiment comprises ordered or unordered MOH code that approaches the upper-bound for large n wits. According to the embodiments, before an erasure is needed, the majority of the wits are encoded, which provides level wearing and maximizes life of cells.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: March 28, 2017
    Assignee: Queen's University at Kingston
    Inventors: Jay Hua, Shahram Yousefi
  • Patent number: 9607691
    Abstract: Methods, systems, and devices for operating and forming a multilevel memory cell and array are described. A multilevel memory cell includes two or more binary memory elements, which may include phase change material. Each memory element may be programmed to one of two possible states—e.g., a fully amorphous state or a fully crystalline state. By combining multiple binary memory elements in a single memory cell, the memory cell may be programmed to store more than two states. The different memory elements may be programmed by selectively melting each memory element. Selective melting may be controlled by using memory elements with different melting temperatures or using electrodes with different electrical resistances, or both.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: March 28, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Mario Allegra, Mattia Boniardi
  • Patent number: 9607692
    Abstract: Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to determine a first current on a source line of an array of memory cells, the first current corresponding to a first quantity of memory cells of a group of memory cells that conducts in response to a first sensing voltage applied to an access line and determine a second current on the source line, the second current corresponding to a second quantity of memory cells of the group that conducts in response to a second sensing voltage applied to the access line. The number of apparatuses can include a controller configured to determine at least a portion of a Vt distribution corresponding to the group of memory cells based, at least in part, on the first current and the second current.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: March 28, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Qiang Tang, Feng Pan, Ramin Ghodsi, Mark A. Helm
  • Patent number: 9607693
    Abstract: A semiconductor storage device according to the present embodiments includes a first bit line and a first word line. A resistance-change memory element is connected to the first bit line and the first word line. A sense node is connected to the first bit line in a data read operation. A first transistor is connected between the sense node and the first bit line. A second transistor connects the first bit line and a power supply to each other in a data write operation. A first operational amplifier has one input connected to the first bit line, other input receiving a reference voltage, and an output connected in common to a gate of the first transistor and a gate of the second transistor. A sense circuit is connected to the sense node.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: March 28, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryu Ogiwara, Daisaburo Takashima
  • Patent number: 9607694
    Abstract: A semiconductor memory device according to the embodiments includes a first wiring, a second wiring that extends to intersect with the first wiring, a memory cell that is disposed on each intersection portion of the first wiring and the second wiring, and includes a variable resistive element, and a control circuit to control a voltage applied to the memory cell. The control circuit applies a read voltage with respect to the memory cell for a plurality of times to determine a resistive state of the memory cell for a plurality of times, so as to obtain a first determination result or a second determination result. The control circuit compares the number of the first determination result with the number of the second determination result, terminates a reading operation when the comparison result satisfies a certain condition, and starts the reading operation again when the condition is not satisfied.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: March 28, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Reika Ichihara
  • Patent number: 9607695
    Abstract: Multi-bit non-volatile random access memory cells are disclosed. A multi-bit non-volatile random access memory cell may include a volatile storage element and a non-volatile storage circuit. The non-volatile storage circuit may include at least one first pass transistor connected to a data true (DT) node of the volatile storage element and at least one second pass transistor connected to a data complement (DC) node of the volatile storage element. The non-volatile storage circuit may also include multiple non-volatile storage elements. Each non-volatile storage element may be configured to be selectively connectable to the DT node of the volatile storage element via the at least one first pass transistor and selectively connectable to the DC node of the volatile storage element via the at least one second pass transistor, allowing the multi-bit non-volatile random access memory cell to store/recall more than one databit per cell.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: March 28, 2017
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Joseph Tandingan, Judith Allen, David Still, Jayant Ashokkumar
  • Patent number: 9607696
    Abstract: A method for writing data, the method may include evaluating current levels of multiple memory cells that belong to a certain set of memory cells or receiving an indication about the current levels of the multiple memory cells; encoding a new data unit to provide an encoded data unit to be written to the multiple memory cells while minimizing an amount of changes in levels of the maximum cell level among the multiple memory cells required for storing the encoded data unit; and writing the encoded data unit to the multiple memory cells.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: March 28, 2017
    Assignee: Technion research and development foundation Ltd.
    Inventors: Yitzhak Birk, Amit Berman
  • Patent number: 9607697
    Abstract: Provided herein are semiconductor memory devices and operating methods thereof. A semiconductor memory device may include a memory cell array including a plurality of cell strings, and a peripheral circuit. The peripheral circuit may include a voltage generating unit configured to perform a program loop for alternately performing a program operation and a verification operation on the memory cell array. The peripheral circuit may include a control logic configured to control the voltage generating unit to perform the program loop. Wherein, in performing the program loop, a second pass voltage applied to an unselected word line adjacent to a selected word line among a plurality of word lines connected with the memory cell array is lower than a first pass voltage applied to a remaining unselected word line during the program operation.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: March 28, 2017
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 9607698
    Abstract: A semiconductor memory device may include a plurality of memory cells programmed to have one of first to Nth program states differentiated according to threshold voltages of the memory cells, the method including determining whether there exists over program cells from among memory cells programmed to a N?1th program state, by using a first verify voltage of a Nth program state from among the first to Nth program states; when there exists over program cells, determining whether the number of the over program cells exceeds a reference value; and when the number of over program cells exceeds the reference value, outputting a program fall signal to a controller.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: March 28, 2017
    Assignee: SK Hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 9607699
    Abstract: An operating method of a memory system including first and second one half pages includes acquiring first and second partial data from main data; performing a first program operation to the first one half page of a selected page with the first partial data; and performing a second program operation to the second one half page of the selected page with the second partial data. The first and second partial data may be programmed in the same first column region in the first and second one half pages, respectively.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: March 28, 2017
    Assignee: SK Hynix Inc.
    Inventor: Tae Hoon Kim
  • Patent number: 9607700
    Abstract: The method of operating a non-volatile memory device includes dumping data stored in input latches of a page buffer to other latches of the page buffer to receive second data to be written to a second cell group of a memory cell array from outside the non-volatile memory device during writing of first data to a first cell group of the memory cell array. In the method, receiving of the second data may be finished before the writing of the first data is finished.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: March 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seung-Bum Kim
  • Patent number: 9607701
    Abstract: The present inventions are related to systems and methods for storing data, and more particularly to systems and methods for writing data to a storage device.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: March 28, 2017
    Assignee: Seagate Technology LLC
    Inventors: Bruce A. Wilson, Erich F. Haratsch
  • Patent number: 9607702
    Abstract: A NAND array includes blocks of memory cells. A block of memory cells includes a plurality of strings having channel lines between first and second string select switches. The strings share a set of word lines between the first and second string select switches. A channel-side voltage can be applied to the channel lines. A control voltage can be applied to a selected subset of the first string select switches. The channel lines can be floated at ends of the second string select switches. Tunneling in memory cells coupled to an unselected subset of the first string select switches can be inhibited. Word line-side erase voltages can be applied to word lines in the set of word lines in the block to induce tunneling in memory cells coupled to the word lines and coupled to the selected subset of the first string select switches.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: March 28, 2017
    Assignee: Macronix International Co., Ltd.
    Inventor: Kuo-Pin Chang
  • Patent number: 9607703
    Abstract: According to one embodiment, a memory system includes a memory and a setting unit. The memory includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory cells, each of which holds an electrical charge. The peripheral circuit is configured to read a value from each memory cell by comparing a quantity of an electrical charge held in the memory cell with a determination threshold. The memory stores first data in the memory cell array. The first data include a plurality of values. The setting unit is configured to change the determination threshold according to the number of values which are different in second data and third data among the plurality of values. The second data are first data before being written to the memory. The third data are first data that have been read from the memory.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: March 28, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinichi Kanno
  • Patent number: 9607704
    Abstract: A data reading method is provided. The data reading method includes receiving a read command from a host system; sending a first read command sequence to obtain a first data string from memory cells of a rewritable non-volatile memory module; performing a decoding procedure on the first data string to generate a decoded first data string; and, if there is an error bit in the decoded first data string, sending a second read command sequence to obtain a second data string from the memory cells, performing a logical operation on the decoded first data string and the second data string to obtain an adjusting data string, adjusting the decoded first data string according to the adjusting data string to obtain an adjusted first data string, and using a data string obtained after re-performing the decoding procedure on the adjusted first data string as the decoded first data string.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: March 28, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Tien-Ching Wang, Kuo-Hsin Lai
  • Patent number: 9607705
    Abstract: Apparatuses and methods for charging a global access line prior to accessing a memory are described. An example apparatus may include a memory array of a memory. A plurality of global access lines may be associated with the memory array. The global access line may be charged to a ready-access voltage before any access command has been received by the memory. The global access line may be maintained at the ready-access voltage during memory access operations until the receipt of a post-access command. The post-access command may reset the global access line to an inactive voltage.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: March 28, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 9607706
    Abstract: A semiconductor memory device includes a first memory bank and a second memory bank; an address counter unit including: a first address counter suitable for outputting a first counting address signal corresponding to the first memory bank; and a second address counter suitable for outputting a second counting address signal corresponding to the second memory bank; a first output control unit suitable for generating first column address signals in response to the first counting address signal during a data input operation, and generating the first column address signals in response to the second counting address signal during a data output operation; and a second output control unit generating second column address signals in response to the second counting address signal during the data input operation and the data output operation.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: March 28, 2017
    Assignee: SK Hynix Inc.
    Inventors: Kyeong Min Chae, Min Su Kim
  • Patent number: 9607707
    Abstract: Techniques are disclosed for accurately sensing memory cells without having to wait for a voltage that creeps up on word line after a sensing operation to die down. The word line creep up could cause electrons to trap in shallow interface traps of a memory cell, hence impacting its threshold voltage. In one aspect, trapped electrons are removed (e.g., de-trapped) from shallow interface traps of a memory cell using a weak erase operation. Therefore, problems associated with word line voltage creep up are reduced or prevented. Thus, the memory cell can be sensed without waiting, while still providing an accurate result. The weak erase could be part of a sensing operation, but that is not required. For example, the weak erase could be incorporated into the beginning part of a read operation, which provides for a very efficient solution.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: March 28, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Liang Pang, Yingda Dong, Xuehong Yu, Jingjian Ren
  • Patent number: 9607708
    Abstract: Electrically erasable flash memory and method. The memory has a data storage element and a voltage sensing circuit. The data storage element is configured to store data bits, each of the data bits having a data state. The voltage sensing circuit is selectively coupled to individual ones of data bits and is configured to bias the data bits with at least one of a bias current and a bias resistance and to read the data state of the individual ones of the plurality of data bits.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: March 28, 2017
    Assignee: Medtronic, Inc.
    Inventors: Kevin K. Walsh, Paul B. Patterson, Glen W. Benton, Jeffrey D. Wilkinson
  • Patent number: 9607709
    Abstract: A voltage generator that includes an operation mode determination circuit suitable for determining an active mode or a standby mode based on a chip enable signal to activate an active mode signal or a standby mode signal according to a result of the determination; and a bulk voltage generation circuit outputting a bulk voltage having an internal power voltage when the active mode signal is activated, and outputting the bulk voltage having an external power voltage when the standby mode signal is activated.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: March 28, 2017
    Assignee: SK Hynix Inc.
    Inventor: Min Su Kim
  • Patent number: 9607710
    Abstract: A read-threshold calibration method in a solid state storage system including measuring a threshold voltage distribution of solid state storage elements; determining a threshold voltage; decoding data according to the determined threshold voltage; filtering the threshold voltage distribution of solid state storage elements with a predetermined filter length when the decoding fails; changing the filter length; and repeating the determining, decoding, filtering, and changing steps with the changed filter length until the decoding is successful.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: March 28, 2017
    Assignee: SK hynix memory solutions Inc.
    Inventors: Fan Zhang, June Lee
  • Patent number: 9607711
    Abstract: There are provided a semiconductor memory device and an operating method thereof. A semiconductor memory device includes a memory cell array including a plurality of memory strings, a peripheral circuit for performing a program operation on the plurality of memory strings, and a control logic for controlling the peripheral circuit to apply a program voltage increased by at least two steps to a selected word line among a plurality of word lines connected to the plurality of memory strings and sequentially apply an initial setting voltage and a pass voltage to word lines adjacent to the selected word line, wherein the initial setting voltage is decreased as the program voltage is increased.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: March 28, 2017
    Assignee: SK Hynix Inc.
    Inventor: Jung Hwan Lee
  • Patent number: 9607712
    Abstract: A shift register group includes a plurality of series-coupled shift registers each being configured to provide an output signal. The third control signal of a first sift register of the plurality of shift registers is the output signal provided by the shift register N stages after the first shift register, and the fourth control signal of the first sift register is the voltage at the driving node of the shift register 2N stages after the first shift register, wherein N is a natural number. A driving method of the aforementioned shift register group is also provided.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: March 28, 2017
    Assignee: AU OPTRONICS CORP.
    Inventors: Wei-Li Lin, Che-Wei Tung, Chia-Heng Chen
  • Patent number: 9607713
    Abstract: An electronic device includes a semiconductor memory that includes: a first line; a second line intersecting the first line; a memory cell coupled at a cross point of the first line and the second line; and a test control circuit coupled between the first line and the second line and suitable for controlling parameters corresponding to operational characteristics of the memory cell and outputting a result information signal corresponding to the control result to a pad based on a clock signal and an initial value set signal.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: March 28, 2017
    Assignee: SK Hynix Inc.
    Inventor: Ho-Seok Em
  • Patent number: 9607714
    Abstract: A method of training a command signal for a memory module. The method includes programming a memory controller into a mode where a single bit of an address signal is active for a single clock cycle. The method then programs a programmable delay line of the address signal with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode. A write leveling procedure is then performed and a response to the write leveling procedure is determined from the memory module. A determination is made whether the memory module is in a pass state or an error state based on the response.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: March 28, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: Venkata Ramana Malladi, Tony Yuhsiang Cheng, Sharath Raghava, Ambuj Kumar, Arunjit Sahni, Paul Lam
  • Patent number: 9607715
    Abstract: In some embodiments, a system includes a memory testing circuit configured to perform a test of an internal comparator of a memory circuit by performing operations. The operations may include causing a first value to be stored at the memory circuit as a current data value. The operations may further include subsequently causing the first value to be sent to the memory circuit as a current comparison data value. The operations may further include causing the internal comparator to compare the current data value to the current comparison data value. The operations may further include receiving a current match value that indicates whether the current data value matches the current comparison data value. In some embodiments, the memory testing circuit may be configured to enable a self-test circuit to detect errors regarding functions of the memory circuit that the self-test circuit is not designed to test.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: March 28, 2017
    Assignee: Apple Inc.
    Inventor: Dragos F. Botea
  • Patent number: 9607716
    Abstract: A method for testing a stacked memory device having a plurality of memory chips connected to and arranged on top of a logic chip for a connection defect is disclosed. The method may include testing a memory chip by writing a data value into a first location in the memory chip, reading a data value from the first location, detecting a first bit error and recording a bit number of the first bit error. The method may also include testing the memory chip by writing a data value into a second location in the memory chip, reading a data value from the second location in the memory chip, detecting a second bit error and recording a bit number of the second bit error. The method may also include replacing a connection common to the first and second bit errors with a spare connection.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: March 28, 2017
    Assignee: Internatiional Business Machines Corporation
    Inventors: Charles A. Kilmer, Warren E. Maule, Saravanan Sethuraman
  • Patent number: 9607717
    Abstract: A data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays. A reference voltage level is determined for each integrated circuit being tested, corresponding to the read of a high polarization capacitance data state. A number of FRAM cells in the integrated circuit are programmed to that data state, and then read at an elevated temperature, with the number of failing cells compared against a pass/fail threshold to determine whether the integrated circuit is vulnerable to long-term data retention failure.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: March 28, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Richard Bailey, John A. Rodriguez
  • Patent number: 9607718
    Abstract: A semiconductor memory device includes: a word line driving unit suitable for performing activation operations for a plurality of normal word lines and a plurality of redundancy word lines in response to test addresses; and a test control unit suitable for controlling a number of activations of each of the plural normal and redundancy word lines to be equal based on repair information corresponding to a repair target word line among the plural normal word lines during a test operation.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: March 28, 2017
    Assignee: SK Hynix Inc.
    Inventor: Sung-Soo Chi
  • Patent number: 9607719
    Abstract: A system and apparatus for controlled fusion in a field reversed configuration (FRC) magnetic topology and conversion of fusion product energies directly to electric power. Preferably, plasma ions are magnetically confined in the FRC while plasma electrons are electrostatically confined in a deep energy well, created by tuning an externally applied magnetic field. In this configuration, ions and electrons may have adequate density and temperature so that upon collisions ions are fused together by the nuclear force, thus forming fusion products that emerge in the form of an annular beam. Energy is removed from the fusion product ions as they spiral past electrodes of an inverse cyclotron converter. Advantageously, the fusion fuel plasmas that can be used with the present confinement and energy conversion system include advanced (aneutronic) fuels.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: March 28, 2017
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Alan VanDrie, Eusebio Garate, Yuanxu Song
  • Patent number: 9607720
    Abstract: The design of a compact, high-efficiency, high-flux capable compact-accelerator fusion neutron generator (FNG) is discussed. FNG's can be used in a variety of industrial analysis applications to replace the use of radioisotopes which pose higher risks to both the end user and national security. High efficiency, long lifetime, and high power-handling capability are achieved though innovative target materials and ion source technology. The device can be scaled up for neutron radiography applications, or down for borehole analysis or other compact applications. Advanced technologies such as custom neutron output energy spectrum, pulsing, and associated particle imaging can be incorporated.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: March 28, 2017
    Assignee: Starfire Industries LLC
    Inventors: Robert Andrew Stubbers, Brian Edward Jurczyk, Darren Adam Alman, Matthew David Coventry, Michael Jerome Schaus
  • Patent number: 9607721
    Abstract: A method for separating amorphous iron oxides is provided. The method includes steps of sampling, filtering, dissolving and separating, analyzing the solution containing amorphous radioactive iron oxides and analyzing granules containing crystalline radioactive iron oxides. Characteristics of the radioactive iron oxides during various periods are acquired to solve the radiation buildup problem. Parameters for improving water quality and chemistry performance indicator are thus provided. Crystalline deposits are separated while the dissolving rate of radioactive iron oxides reaches more than 90%. The present invention does not use complex utilities, is easy to use and has a low operation cost for fast analysis.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: March 28, 2017
    Assignee: INSTITUTE OF NUCLEAR ENERGY RESEARCH, ATOMIC ENERGY COUNCIL, Executive Yuan, R.O.C.
    Inventors: Yu-Hung Shih, Tung-Jen Wen, Dah-Yu Kao, Yu-Te Tsai
  • Patent number: 9607722
    Abstract: Methods for setting up, maintaining and operating a radiopharmaceutical infusion system, that includes a radioisotope generator, are facilitated by a computer of the system. The computer includes pre-programmed instructions and a computer interface, for interaction with a user of the system, for example, in order to track contained volumes of eluant and/or eluate, and/or to track time from completion of an elution performed by the system, and/or to calculate one or more system and/or injection parameters for quality control, and/or to perform purges of the system, and/or to facilitate diagnostic imaging.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: March 28, 2017
    Assignee: Bracco Diagnostics Inc.
    Inventors: Stephen E. Hidem, Aaron M. Fontaine, Janet L. Gelbach, Patrick M. McDonald, Kathryn M. Hunter, Rolf E. Swenson, Julius P. Zodda
  • Patent number: 9607723
    Abstract: For manufacturing a radiation window for an X-ray measurement apparatus, and etch stop layer is first produced on a polished surface of a carrier. A thin film deposition technique is used to produce a structural layer on an opposite side of said etch stop layer than said carrier. The combined structure comprising said carrier, said etch stop layer, and said structural layer is attached to a region around an opening in a support structure with said structural layer facing said support structure. The carrier is etched away.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: March 28, 2017
    Assignee: HS FOILS OY
    Inventor: Heikki Johannes Sipilä
  • Patent number: 9607724
    Abstract: Objects undergoing processing by a high resolution x-ray microscope with a high flux x-ray source that allows high speed metrology or inspection of objects such as integrated circuits (ICs), printed circuit boards (PCBs), and other IC packaging technologies. The object to be investigated is illuminated by collimated, high-flux x-rays from an extended source having a designated x-ray spectrum. The system also comprises a stage to control the position and orientation of the object; a scintillator that absorbs x-rays and emits visible photons positioned in very close proximity to (or in contact with) the object; an optical imaging system that forms a highly magnified, high-resolution image of the photons emitted by the scintillator; and a detector such as a CCD array to convert the image to electronic signals.
    Type: Grant
    Filed: June 6, 2015
    Date of Patent: March 28, 2017
    Assignee: SVXR, Inc.
    Inventor: David Lewis Adler
  • Patent number: 9607725
    Abstract: Provided are a graphene structure and a method for producing the same in which graphene can be patterned with high precision, and thereby microfabrication of electronic device elements and electronic devices using graphene is possible and the manufacturing cost can be notably reduced. A resist film is precisely patterned on a substrate, hydrophilized films are formed in openings of the resist film, and then GO is selectively fixed on the portions of the hydrophilized films by a chemical bond utilizing the hydrophilicity of the GO, and the GO is reduced to obtain a graphene structure in which graphene is selectively fixed to only the portions of the hydrophilized films. Thus, the graphene structure is constituted by disposing graphene on a substrate and forming a bond, by hydrophilization treatment, between the hydrophilized portion of the substrate and the graphene and/or between the unhydrophobized portion of the substrate and the graphene.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: March 28, 2017
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Adarsh Sandhu
  • Patent number: 9607726
    Abstract: A composition for forming a conductive film. The composition comprises a plurality of nanowires comprising silver; a latex comprising polymer particles; and an aqueous-based carrier.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: March 28, 2017
    Assignee: XEROX CORPORATION
    Inventor: Yiliang Wu
  • Patent number: 9607727
    Abstract: An anisotropic electroconductive particle including a first insulating layer, a first conductive layer disposed on the first insulating layer, and a second insulating layer disposed on the first conductive layer.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: March 28, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Sein Chang
  • Patent number: 9607728
    Abstract: Free radically crosslinked, electrically conductive compositions exhibiting a highly stable volume resistivity comprise an olefin multiblock copolymer (OBC) having a high, e.g., greater than 20 mole percent comonomer content, e.g., butylene or octene, and carbon black. These compositions exhibit a highly stable volume resistivity relative to a composition similar in essentially all aspects save that the high comonomer OBC is replaced with a low comonomer OBC of similar density and melt index.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: March 28, 2017
    Assignee: Dow Global Technologies LLC
    Inventors: Mohamed Esseghir, Gary R. Marchand