Abstract: An apparatus includes a plurality of adjustable driver circuits having output nodes coupled to a signal line. Each adjustable driver circuit is configured to drive the signal line with a portion of a total drive strength indicated by a value of a binary control signal. The apparatus also includes a delay circuit configured to delay the binary control signal provided to each adjustable driver circuit by a respective time period unique to the adjustable driver circuit.

Abstract: A routing network is associated with a logic island in a logic block of a programmable logic device and includes switches for each of feedback, street, and highway networks. Some of the switches include multiple stages. The street network switch receives the signals from the feedback network switch, signals from neighboring highway network switches, and direct feedback from selected logic island outputs and provides outputs to the logic island. The street network switch includes multiple stages, where outputs to the logic island are provided directly by each stage in the street network switch. The output terminals of a first stage of the street network switch that are connected to the logic island are also connected to the second stage of the street network switch. The second stage of the street network switch receives feedback output signals from the feedback network and directly from the associated logic island.

Abstract: A reconfigurable logic device includes logic units and allows logic circuits to be formed according to configuration data. The logic units each include a configuration memory that stores first and second configuration data, a first address input line through which a clock is inputted as a first address for the configuration memory, a second address input line through which an input of a data input line is inputted as a second address for the configuration memory, a register unit that, according to the clock, reads the second configuration data specified by the first address from the configuration memory and retains the second configuration data, and outputs the first configuration data in a previous state, and a multiplexer that, according to the first or second configuration data outputted from the register unit, selectively combines a data input from the data input line and a data output to a data output line.

Abstract: A method for accessing signals of a programmable logic device having a functional level and a configuration level at run time when the programmable logic device is executing a predefined configuration. An access to at least one signal value that has a number of bits is requested. The individual bits in the configuration are each located in an address unit with one address offset apiece such that one or more bits of a signal value are located in one address unit. A bitwise access to the requested signal values takes place, wherein the accesses to the individual bits are sorted as a function of the address unit containing the applicable bit in such a manner that the accesses to all bits located in an address unit take place in sequence as a function of the address offset, independently of the signal containing the applicable bit.

Abstract: An antifuse apparatus can include a cantilever extending from a first electrode portion to terminate in a distal end. A second electrode portion can be spaced apart from the cantilever by an air gap. In response to a program voltage across the first and second electrode portions, the cantilever can be adapted to move from an unprogrammed condition, corresponding to an open circuit condition where the cantilever is spaced apart from the second electrode portion, to at least one permanent programmed condition, corresponding to a short circuit condition between the first and second electrode portions where the cantilever engages the second electrode portion.

Abstract: A radio transmission apparatus includes a radio transmission IC including a vibration element and a fractional N-PLL circuit and a power amplifier generating a radio transmission signal and a control device that controls the radio transmission IC, and a temperature detection element. The control device controls the fractional N-PLL circuit based on temperature information obtained from the temperature detection element such that a frequency of the radio transmission signal is temperature-compensated.

Abstract: Digital control of a crystal oscillator is implemented in a manner that allows frequency accuracy to be traded off dynamically with power consumption. The oscillator transitions between a less accurate/lower power mode and a high accuracy/higher power mode smoothly without requiring any external clock source during the transition. Power consumption is optimized because the crystal oscillator provides the clock source during transitions between the power modes and no other clock source is needed for these transitions. The system can also optimize the startup time and steady state power consumption independently.

Abstract: An adaptive clock distribution (ACD) system with a voltage tracking clock generator (VTCG) is disclosed. The ACD system includes a tunable-length delay (TLD) circuit, to generate a TLD clock by adding a preselected delay to a root clock, and a voltage droop detector for detecting a voltage droop in a supply voltage. The VTCG is configured to generate a VTCG clock, wherein a frequency of the VTCG clock is finely tuned to one of two or more values to correspond to a magnitude of the supply voltage during the voltage droop. A clock selector selects the VTCG clock as an ACD clock to be provided to an electronic circuit during the voltage droop and the TLD clock as the ACD clock when there is no voltage droop detected.

Abstract: While transmission of data to be transmitted and gap data to be transmitted by the same transmission path as that data is controlled so that a frequency of a data signal may become equal to or more than a certain frequency, a data output driver selects and outputs the data or the gap data as the data signal, a valid signal generation circuit outputs a valid signal that indicates whether or not the data is effective, and a reception circuit that is formed in a different die receives the data signal and the valid signal transmitted via the transmission path that includes a through silicon via and acquires the data from the data signal based on the valid signal.

Abstract: A phase detector includes a clock delay circuit, a data delay circuit, a control circuit, a D flip-flop, and a logic circuit. The clock delay circuit delays a clock signal so as to generate a delay clock signal. The data delay circuit delays a data signal so as to generate a delay data signal. The control circuit adjusts the delay time of the clock delay circuit and the delay time of the data delay circuit according to the clock signal and the delay clock signal. The D flip-flop generates a register signal according to the data signal and the clock signal. The logic circuit generates an up control signal and a down control signal according to the data signal, the delay data signal, and the register signal so as to control a charge pump of a CDR (Clock Data Recovery) circuit.

Abstract: Described is an apparatus comprising: a delay line including at least four delay stages coupled together in a series; a first multiplexer having a first input coupled to an output of a first delay stage of the at least four delay stages, and a second input coupled to an output of a third delay stage of the at least four delay stages; a second multiplexer having a first input coupled to an output of a second delay stage of the at least four delay stages, and a second input coupled to an output of a fourth delay stage of the at least four delay stages; and a phase interpolator coupled to outputs of the first and second multiplexers, the phase interpolator having an output.

Abstract: A charge pump circuit comprises a first bipolar transistor device and a second bipolar switching device arranged in a differential pair configuration. A first terminal of each of the first and second bipolar switching devices are coupled to a supply. A second like terminal of each of the first and second bipolar switching devices are coupled together and to ground potential via a pulsed current source. A field effect switching device is also provided and the first terminal of the first bipolar switching device is coupled to the voltage supply via the field effect switching device.

Abstract: Described is an integrated circuit (IC) with a phase locked loop with capability of fast locking. The IC comprises: a node to provide a reference clock; a digitally controlled oscillator (DCO) to generate an output clock; a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock; and control logic operable to reset the DCO and the divider, and operable to release reset in synchronization with the reference clock. An apparatus for zeroing phase error is provided which comprises a first node to provide a reference clock; a second node to provide a feedback clock; a time-to-digital converter, coupled to the first and second nodes, to measure phase error between the reference and feedback clocks; a digital loop filter; and a control unit to adjust the measured phase error, and to provide the adjusted phase error to the digital loop filter.

Abstract: Methods for designing and developing models for simulating the behavior of clock signals and in particular those generated by phase-locked loop (PLL) circuits are provided. The clock period of a phase-locked loop circuit's variable frequency oscillator signal may be modeled by combining the inverse of the oscillator frequency rounded up to the simulation time scale with the inverse rounded down to the simulation time scale. The variable frequency oscillator signal may further be synchronized with a reference clock signal at a rate determined by the relationship between the reference clock signal and the variable frequency oscillator signal. A parameter may indicate a target range for the deviation between the two signals and a runtime monitor may be used together with the parameter setting to decide whether synchronization is required and make the appropriate adjustments.

Abstract: In order to configure an oscillation circuit, an oscillator, a fractional N-PLL circuit, and the like that can output a plurality of frequencies, while decreasing an influence of an integer value boundary spurious at one reference frequency, the oscillation circuit includes a circuit for oscillation that oscillates a resonator, a fractional N-PLL circuit to which a signal from the circuit for oscillation is input, and a non-volatile memory that stores a plurality of division ratios, which can be selected from outside, of the fractional N-PLL circuit. A fractional portion of at least two of the plurality of division ratios is equal to or higher than 0.05 and is equal to or lower than 0.95.

Abstract: A method and device for handling an in-phase and quadrature (“I/Q”) channel mismatch of an I/Q down-converted signal, and a use of the device. A discrete-time complex valued signal r(n) based on an analog-to-digital conversion of the I/Q down-converted signal is obtained. The obtained discrete-time complex valued signal r(n) is oversampled by a factor of two or more. An intermediate signal v(n) is formed from the discrete-time complex valued signal r(n). The intermediate signal v(n) corresponds to the real part of a ?/2 frequency shifted version of the obtained discrete-time complex valued signal r(n). A procedure for obtaining an estimate of a frequency dependent mismatch of a two-channel time-interleaved analog-to-digital converter (“TI-ADC”) is applied on the formed intermediate signal v(n). Thereby a TI-ADC mismatch estimate is obtained. The I/Q channel mismatch is estimated and/or compensated based on the obtained TI-ADC mismatch estimate.

Abstract: The present disclosure is directed to multichannel transducer devices and methods of operation thereof. One example device includes at least two acquisition modules that have different sensitives and a signal processing stage that generates a blended signal representative of a lower gain signal mapped onto a higher gain signal. One example method of operation includes receiving a first signal from a first sensor having a first sensitivity, receiving a second signal from a second sensor having a second sensitivity that is different from the first sensitivity, generating a blended signal by mapping the second signal to the first signal, outputting the first signal while the first signal is below a first threshold and above a second threshold, and outputting the blended signal when the first signal is above the first threshold and when the first signal is below the second threshold.

Abstract: Systems and methods for load current compensation for analog input buffers. In various embodiments, an input buffer may include a first transistor (Q1) having a collector terminal coupled to a power supply node and a base terminal coupled to a first input node (vinp); a second transistor (Q2) having a collector terminal coupled to an emitter terminal of the first transistor (Q1); a third transistor (Q3) having an emitter terminal coupled to an emitter terminal of the second transistor (Q2) and to a ground node, a collector terminal coupled to a current source (Ibias), and a base terminal coupled the collector terminal and to a base terminal of the second transistor (Q2); and a capacitor (C1) coupled to the base terminals of the second and third transistors (Q2 and Q3) and to a second input node (vinn), wherein the first and second input nodes (vinp and vinn) are differential inputs.

Abstract: An analog-to-digital conversion device for multiple input signals includes a sample-and-hold amplifier and an analog-to-digital converter for converting an analog signal output from the sample-and-hold amplifier into a digital signal. According to the analog-to-digital conversion device for multiple input signals and a conversion method therefor, even if an input buffer is not provided, the dynamic range of the analog-to-digital converter may be optimally set depending on the input signals, and current consumption may be reduced.

Abstract: Various embodiments of the present technology may comprise a method and apparatus for an analog-to digital converter (ADC). Methods and apparatus for an ADC according to various aspects of the present invention may operate in conjunction with a reference voltage that varies according to the frequency of a timing signal. By varying the reference voltage according to the frequency of the timing signal, the ADC generates a digital output having a substantially fixed voltage variation regardless of the frequency of the timing signal.

Abstract: An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type digital-to-analog converter (DAC) and at least one second channel type DAC. The integrated circuit further includes a plurality of sample and hold (S/H) circuits, each of the plurality of S/H circuits being coupled with a single DAC of the DAC circuit. A number of the at least one first channel type DAC is different than a number of the at least one second channel type DAC.

Abstract: A method and an apparatus for splitting a switched capacitor integrator of a delta-sigma modulator are provided. The apparatus configures a first integrator and a second integrator to be coupled in parallel to each other, switches between a first mode and a second mode, enables the first integrator to operate on an input signal to generate an output signal in the first mode, and enables the first integrator and the second integrator to cooperatively operate on the input signal in the second mode, wherein in the second mode, the apparatus generates a first output via the first integrator, generates a second output via the second integrator, and converges the first output with the second output to generate the output signal.

Abstract: A single plate capacitance sensor includes a sensor capacitor and a reference capacitor that share common plate. A capacitance-to-digital sigma delta modulator provides separate sensor excitation and reference excitation signals to the sensor capacitor and the reference capacitor to provide high resolution detection. Programmable ratio-metric excitation voltages and adaptive excitation voltage sources can be used to enhance modulator performance.

Abstract: The present disclosure provides a delta-sigma modulator circuit for use in a pixelated image sensor or a readout integrated circuit. In one aspect, the modulator circuit includes a dynamic resistance element configured to have a variable resistance that changes in accordance with a voltage difference across the dynamic resistance element.

Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.

Abstract: Each binary floating-point value in a set of binary floating-point values is converted to a decimal floating-point value. Data are determined including an exponent, a mantissa and a quantity of decimal digits of the mantissa for each decimal floating-point value. The exponents, the mantissas and the quantity of decimal digits are individually compressed to produce compressed floating-point values based on the individual compressions.

Abstract: System and method to encode and decode raw data. The method to encode includes receiving a block of uncoded data, decomposing the block of uncoded data into a plurality of data vectors, mapping each of the plurality of data vectors to a respective bit marker, wherein the respective bit marker is shorter than said respective mapped data vector, and storing the bit marker in a memory to produce an encoded representation of the uncoded data. Encoding may further include decomposing the block of uncoded data into default data and non-default data, and mapping only the non-default data. In some embodiments, bit markers may include a seed value and replication rule, or a fractalized pattern.

Abstract: Operation of a multi-slice computer processor that includes a plurality of execution slices. Operation of such a computer processor includes: matching one or more sub strings of a data string to one or more substrings of a data set; determining that a particular substring of the one or more substrings of the data string corresponds to a highest priority value among one or more priority values mapped to one or more encodings for the one or more substrings of the data string; and encoding, in dependence upon the particular substring of the data string corresponding to the highest priority value, the data string into an encoding that encodes the particular substring of the one or more substrings of the data string.

Abstract: The encoding apparatus registers, in a dynamic dictionary, strings in input text data that are not contained in a static dictionary. The encoding apparatus adds, to first hashed data obtained by individually N-dimensionally hashing words contained as registered items in the static dictionary, hashed data obtained by individually hashing strings registered in the dynamic dictionary. The encoding apparatus 100 determines, by using the first hashed data, whether each input string has been registered in the static dictionary 124 and whether the string has been registered in the dynamic dictionary 122. In accordance with the result of the determination, the encoding apparatus 100 performs encoding based on a content registered in the static dictionary or the dynamic dictionary.

Abstract: A engine of a hardware data compressor maintains first and second hash tables while it scans an input block of characters to be compressed. The first hash table is indexed by a hash of N characters of the input block. The second hash table is indexed by a hash of M characters of the input block. M is greater than two. N is greater than M. The engine uses the first hash table to search the input block behind a current search target location for a match of at least N characters at the current search target location, and uses the second hash table to search the input block behind the current search target location for a match of at least M characters at the current search target location when no match of at least N characters at the current search target location using the first hash table is found.

Abstract: A method and apparatus for encoding data and for decoding data using LDPC (low density parity check) codes includes providing a mother LDPC matrix of a particular size. A data payload of a smaller size is encoded by shortening the mother matrix to a smaller daughter matrix corresponding in size to the data payload and using the smaller daughter matrix for the encoding. The portions of the mother matrix to be removed in the shortening are derived from a control signal. The encoded data is transmitted with the control signal so that the receiver can derive the portions of the mother matrix to be removed to obtain the daughter matrix. At the receiver, a mother matrix is shortened to a daughter matrix and is then used to decode the data. The data at the encoder may be further reduced by puncturing to remove selected information bits and selected parity bits. The decoder inserts the selected information bits and parity bits when decoding the data.

Abstract: An encoding method for encoding input information bits using an encoder implemented with concatenation of a CRC-? coder and a polar coder is provided. The method includes performing Cyclic Redundancy Check (CRC) coding on as many information bits as a determined number of CRC coding bits among input information bits and performing polar coding on the CRC-coded information bits and other information bits than the CRC-coded information bits.

Abstract: A method for increasing coding reliability includes generating a generator matrix for an extended polar code including a standard polar code part and an additional frozen part. The standard polar code part has N bit-channels, including K information bit-channels and N?K frozen bit-channels. The additional frozen part has q additional frozen bit-channels. Among the K information bit-channels, q information bit-channels are re-polarized using the q additional frozen bit-channels. The method further includes receiving an input vector including K information bits and N+q?K frozen bits, and transforming, using the generator matrix, the input vector to an output vector including N+q encoded bits. The K information bits are allocated to the K information bit-channels, and the N+q?K frozen bits are allocated to the N?K frozen bit-channels and the q additional frozen bit-channels.

Abstract: A wireless communication device that has a circuit board, an RF signal module, a capacitive touch-sensing component and an antenna component is provided. The touch-sensing signal module is disposed on the circuit board. The capacitive touch-sensing component includes a sensing layer and a ground layer. The sensing layer is electrically connected to the touch-sensing signal module. The antenna component includes a feed point and a radiating body. The feed point is disposed on the ground layer and is electrically connected to the RF single module. The radiating body incorporates at least parts of the ground layer. Alternatively, the feed point is disposed on the sensing layer, and the radiating body incorporates at least parts of the sensing layer. Therefore, the radiating body is incorporated into the sensing layer or ground layer of the capacitive touch-sensing component and can save accommodating space.

Abstract: Aspects of the subject disclosure may include, for example, an antenna structure having a feed point for coupling to a dielectric core of a cable that propagates electromagnetic waves without an electrical return path, and a dielectric antenna, substantially or entirely devoid of conductive external surfaces, coupled to the feed point, the dielectric antenna facilitating receipt, at the feed point, the electromagnetic waves for propagating the electromagnetic waves to an aperture of the dielectric antenna for radiating a wireless signal. Other embodiments are disclosed.

Abstract: Mobile devices such as mobile phones include amplifiers for example audio and RF amplifiers which may consume a significant amount of the available power supplied by a battery. An amplifying system 100 for a mobile device is described the amplifying system comprising a current monitor 12 arranged between a first supply node and a second supply node and operable to monitor a current flow between the first and second supply nodes and to output a monitored current value; a peak current limiter 14 configured to limit an amplifier current to an amplifier to not exceed a maximum peak current value and coupled to a one of the first supply node and the second supply node; a controller coupled to the current monitor output and configured to control the peak current limiter. The amplifying system can dynamically manage the peak current available to the amplifier dependent on the load current being supplied by a battery.

Abstract: An RF PA is designed to operate efficiently for average powers when biased at the system supply voltage, and uses an envelope tracking power supply to boost the bias voltage to maintain good efficiency at higher powers. As a result, for a majority of the time when transmitting average power signals, the RF PA bias voltage is the system-wide supply voltage (e.g. 3.4V in cell phones), which eliminates the need for stepping down voltages. The bias voltage is boosted during the less frequent times when higher power is needed. As a result, only a boost type of DC voltage converter is needed. The efficiency of the RF PA is therefore increased because voltage conversion is required less frequently and only when higher power RF signals are transmitted.

Abstract: A method is described for predistorting an input signal to compensate for non-linearities caused to the input signal in producing an output signal. The method comprises: providing an input for receiving a first input signal as a plurality of signal samples, x[n], to be transmitted over a non-linear element; providing at least one digital predistortion block comprising, a plurality of IQ predistorter cells coupled to the input, each comprising a lookup table (LUT) for generating an LUT output. The at least one digital predistortion block block is configured to apply interpolation between LUT entries for the plurality of LUTs; and generate an output signal, y[n], by each of the plurality of IQ predistorter cells by adaptively modifying the first input signal using interpolated LUT entries to compensate for distortion effects in the non-linear element.

Abstract: A system includes a crest-factor reduction circuit, a signal analyzer, and a pre-distortion circuit. The crest-factor reduction circuit reduces a crest factor of a baseband signal and generates a feedforward signal. The signal analyzer generates parameters based on the feedforward signal and an output signal from a power amplifier. The pre-distortion circuit generates a pre-distorted baseband signal based on the parameters for input to the power amplifier.

Abstract: A programmable-current transmit continuous-time filter (TX-CTF) system can be included in a radio frequency (RF) transmitter. The input of the TX-CTF can receive a baseband transmission signal, and the output of the TX-CTF can be provided to an upconversion mixer for conversion to RF for transmission. The TX-CTF includes amplifier circuitry and passive circuitry that together define the filter parameters. The TX-CTF further includes programmable current circuitry that provides a programmable bias current to the amplifier circuitry. The TX-CTF system also includes control logic that receives one or more transmitter control signals and, in response, generates signals that control the bias current provided to the TX-CTF.

Abstract: A system is provided with circuits and methods for dynamically reducing interference to maintain linear system operation and mitigate interference degradation to desired signal components. The system can include a binning subcircuit system configured to divide the digitized input signal into a plurality of spectral bins each having a power level. A power analysis subcircuit can be coupled to the binning subcircuit and configured to compare a collective power level of spectral bins to a threshold level that would produce nonlinear system operation. Based upon the collective power level exceeding the threshold level, outputting a gain control signal to a variable gain amplifier so that the system remains linear. This dynamic gain control can be applied to systems that receive and/or transmit signals. Residual interference components that degrade signal components can be dynamically removed by excision and the distortion introduced by the excision process can be reduced with equalization circuitry.

Abstract: A method and apparatus for mitigating a phase anomaly in an analogue-to-digital converter (ADC) output signal is disclosed. A plurality of codewords output by the ADC are received and information about an estimated level of interference between an output of the ADC and an input of the ADC due to the codeword is obtained for each codeword based on the logic values of bits in the codeword. In-phase (I) and quadrature (Q) corrections are obtained based on the information about the estimated level of interference, and applied to I and Q values obtained from the ADC output signal.

Abstract: Embodiments of the present disclosure provide techniques and configurations for an apparatus for mitigating interference in sensor signals. In one instance, the apparatus may include sensors and a processing block couplable with the sensors. The processing block may include a front end block to receive sensor signals, and tunable filter block to filter the sensor signals. The apparatus may further include a correction block. The correction block may include a replica of the front end block, and may be configured to receive interference information. A controller may operate the correction block to adjust the tunable filter block, based on interference information, and connect the sensors with the processing block after adjustment. The controller may operate the processing block, in response to connection of the processing block with the sensors, to initiate processing of sensor signals filtered by the filter block, to mitigate interference. Other embodiments may be described and/or claimed.

Abstract: A device is provided for correlating at least one noisy analog signal which is one of a plurality of signals obtained by a plurality of receivers. The device comprises a 1-bit quantization element to which the noisy signal is supplied; a comparator configured to compare the quantized signal with a reference signal which is a consensus signal obtained by averaging data from the plurality of receivers; and an up/down counter that is configured to be incremented by a subset of the comparison signal.

Abstract: A dual modulation network is disclosed. The dual modulation network includes a primary network hub (PNH) having a PNH Long range transceiver and a PNH microcontroller. The PNH microcontroller has communication firmware for long range spread spectrum (SS) and narrowband frequency shift keying (FSK) signal communication via the PNH Long range transceiver, and includes a PNH clock signal. The dual modulation network also includes a peripheral device (PD). The PD includes an actuation mechanism, a PD Long range transceiver, and a PD microcontroller. The PD microcontroller has actuation firmware, communication firmware for communication via the PD Long range transceiver, and location firmware, and includes a clock signal. The location firmware instructs the PD long range transceiver to transmit a location signal encoded with a PD transmit time stamp notifying a receiving device of the time the PD transmitted the location signal.

Abstract: Dynamic power class re-registration of wireless devices is provided. A wireless device can exchange data with a communications network. While exchanging data, the device can monitor its usage and based on the usage, generate a power change request. The device can then send the power change request to the communications network, prior to or in conjunction with powering down the device. In this regard, the communications network can receive the power change request, generate instructions for the wireless device, and adjust network resources based on the power change request. The instructions can then be sent to the wireless device. Since the device re-registers its power class with the communications network, handoffs, internetwork thresholds, network resources and other network parameters can be adjusted to compensate for the changed power class resulting into improved service for a user of the wireless device.

Abstract: An electronic device includes a housing that has an opening to access a component inside the housing. The electronic device also includes a cover for the opening, a gasket to provide a seal between the cover and the opening, and a voltage source to supply voltage to the gasket. The gasket is configured to alter its shape, from a normal state that blocks opening of the cover to an activated state that permits opening of the cover, when voltage is applied to the gasket.

Abstract: A multifunctional protective case for a tablet computer includes a front plate (110) with a sandwich structure (111), a holding plate configured to hold a back of the tablet computer and a supporting plate (130) connecting the front plate (110) and the holding plate (120) via a bendable portion (140) to support the tablet computer. A printed circuit board (112) with wireless router functionality is installed in the sandwich structure (111) in the front plate (110), therefore enabling the protective case with wireless router functionality. The printed circuit board (112) can be connected with an external wireless network card, and the tablet computer can get access to a cellular network once placed in the multifunctional protective case and connected to the printed circuit board.

Abstract: A case for a portable electronic device includes a cavity and one or more studded surfaces. The cavity can receive at least a portion of the portable electronic device such that the portable electronic device is removable from the cavity through an opening in the cavity. The studded surfaces can be coupled with one or more building elements.

Abstract: The embodiment relates to a case apparatus including a mounting member, which includes a first mounting member and a second mounting member surrounding the first mounting member; a first antenna device mounted on a top surface of the first mounting member; and a second antenna device mounted on a bottom surface of the second mounting member. Thus, even when the case apparatus is mounted on a mobile communication terminal, short range communication may be smoothly performed between the mobile communication terminal and an external device.