Abstract: Systems and methods for selectively recording and bookmarking a portion of broadcast media content include receiving a video stream containing the broadcast media content, determining a video segment of the video stream to be output to a display device, and performing OCR on characters present within the video segment. The systems and methods may further include detecting a trigger event in the OCR of the video segment and creating a digital bookmark corresponding to the detected trigger event. The systems and methods may include generating a recording of a portion of the broadcast media content, whereby the recording begins prior to the trigger event and concludes after the trigger event, and storing the digital bookmark associated with the generated recording.

Abstract: In a model calculating apparatus (1) according to the invention it is provided, for the purpose of creating a detailed 3D model (20), by a recording device (3), to generate a first video data stream (4) and to generate a reduced video data stream (13) from frames (26) of the first video data stream (4) and to process further these reduced video data stream for the purpose of creating an approximated 3D model (30).

Abstract: A memory card and an electronic system including the memory card. The memory card includes: a substrate having two pairs of edges, in which the edges of each pair face each other; a plurality of first row terminals that are arranged adjacent to an edge at an insertion side of the substrate and include a first voltage power terminal; a plurality of second row terminals that are spaced farther apart from the edge at the insertion side than the plurality of first row terminals and include a power terminal of a second voltage. According to the memory card, efficient use of an area may be maximized and an electrically stable power supply may be provided.

Abstract: An erasing method and a memory device are provided. The memory device includes a plurality of memory blocks. Each of the memory blocks has n sub-blocks. The erasing method includes the following steps. A first erase region is selected from a first memory block of the memory blocks, and the first erase region includes at least one sub-block. A sub-block erase operation is performed on the first erase region of the first memory block.

Abstract: A disclosed example accesses a binary value latched by a sense amplifier in circuit with a memory cell, the binary value latched by the sense amplifier in response to a counter reaching a trigger count value, the trigger count value selected from a plurality of different trigger count values based on a characteristic of the memory cell; determines a programmed state of the memory cell based on the binary value; and performs a memory operation based on the programmed state of the memory cell.

Abstract: Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes an input node; a reference node supplied with a reference voltage; first, second, third and fourth nodes; a first transistor coupled between the first node and the second node, the first transistor having a gate coupled to the input node; a second transistor coupled between the first node and the third node, the second transistor having a gate coupled to the reference node; a third transistor coupled between the second node and the fourth node, the third transistor having a gate coupled to the third node; a fourth transistor coupled between the third node and the fourth node, the fourth transistor having a gate coupled to the third node; and a capacitor coupled between the input node and the third node.

Abstract: A semiconductor memory device includes a ZQ calibration unit configured to generate a pull-up VOH code according to a first target VOH proportional to a power supply voltage and an output driver configured to generate a data signal having a VOH proportional to the power supply voltage based on the pull-up VOH code, wherein VOH means “output high level voltage.

Abstract: A semiconductor system includes a first clock channel and a second clock channel. The first clock channel transmits a first clock signal from a controller to a memory. The second clock channel transmits a second clock signal with a phase difference of 90° from the first clock signal, from the controller to the memory.

Abstract: A method includes resetting an output timing adjustment circuit in each of a plurality of DRAM devices to a default output timing data value, measuring a default delay from read command to read data for each of the plurality of DRAM devices, identifying a slowest DRAM device having a maximum default delay from read command to read data among the plurality of DRAM devices, writing an output timing data value to the output timing adjustment circuit in each of the plurality of DRAM devices to set the delay from read command to read data for each respective DRAM device to an amount substantially equal to the maximum default delay, and reading data from any one of the plurality of DRAM devices with a delay from read command to read data substantially equal to the maximum default delay.

Abstract: Apparatuses included a single-ended main input/output line in a semiconductor device are described. An example apparatus includes: a pair of differential data lines coupled to a sense amplifier; a single-ended data line; a first transistor coupled between the one of the pair of differential data lines and the power line and coupled to the single-ended data line at a control node thereof; a second transistor coupled between the single-ended data line and the power line and coupled to the one of the pair of differential data lines at a control node thereof; and a third transistor coupled between the single-ended data line and the other of the pair of differential data lines.

Abstract: A memory circuit capable of being quickly written in data includes a plurality of banks, and each bank of the plurality of banks includes a plurality of segments. Each segment of the plurality of segments includes a plurality of bit line groups, and each bit line group of the plurality of bit line groups corresponds to a pre-charge line. When a predetermined signal is enabled, a potential is written into memory cells of the each segment corresponding to the each bit line group through the pre-charge line and the each bit line group.

Abstract: A semiconductor memory device includes a memory cell array and a first buffer. The memory cell array includes a plurality of bank arrays. Each of the plurality of bank arrays includes a plurality of memory cells. The memory cell array and the first buffer are configured for performing a first internal read operation, which represents operations of retrieving first data from a first region of the memory cell array and of storing the first data into the first buffer, based on a first read command and a first read address. The first internal read operation is performed based on a deterministic interface in which the first data is stored into the first buffer within a predetermined first duration after the first read command is received and a generation of a first acknowledgement signal is unnecessary after storing the first data into the first buffer is completed.

Abstract: The load on an arbiter that conducts arbitration among host devices is reduced in an information processing system that includes the host devices and a storage device. A memory management device includes detecting units and a command generating unit. Each of the detecting units detects a timing to execute a predetermined process for the storage device. The command generating unit generates a command common to the predetermined processes subjected to the detection in the detecting units, and a sideband signal unique to each of the predetermined signals having the execution timings detected.

Abstract: A dynamic random access memory circuit includes several memory cells, several word line drivers and a first voltage generator. The first voltage generator electrically coupled with the word line drivers, and the first voltage generator is configured to generate a first voltage signal to the word line drivers, in which during a self refresh period of the memory cells, the first voltage signal is decreased by the first voltage generator from a first level to a second level.

Abstract: In an embodiment, a dynamic random-access memory (DRAM) system configures an inactive portion of a DRAM die to operate in accordance with a self-refresh mode that is characterized by refreshes of the DRAM die being controlled by a local DRAM die controller integrated into the DRAM die. The DRAM system also configures an active portion of the DRAM die to operate in accordance with a controller-managed refresh mode while the inactive portion of the DRAM die operates in the self-refresh mode, the controller-managed refresh mode characterized by refreshes of the DRAM die being controlled by a controller that is external to the DRAM die.

Abstract: Provided are a semiconductor device. The semiconductor device includes an SRAM cell including a first pull-up transistor, a first pull-down transistor and a first pass transistor formed on a substrate, a first read buffer transistor connected to gate terminals of the first pull-up transistor and the first pull-down transistor, and a second read buffer transistor which shares a drain terminal with the first read buffer transistor, wherein the first read buffer transistor includes a first channel pattern extending in a first direction vertical to an upper surface of the substrate, a first gate electrode which covers a part of the first channel pattern, and a first drain pattern which does not contact the first gate electrode, and which extends in the first direction, and which is electrically connected to the first channel pattern.

Abstract: Embodiments include systems and methods for improving column selection functionality of memory circuits. Embodiments operate in context of memory bitcells having additional series pass gates (e.g., junction sharing transistors) coupled with a column select signal to form an integrated column select port. Such a column select port can provide each bitcell with column select functionality in a manner that has improved area and power performance over some conventional (added NOR or other logic) approaches. However, the added column select port can still tend to add area, add column select load, and degrade writability (e.g., due to certain charge-sharing effects). Some embodiments are described herein for addressing the area and column select load by sharing certain intermediate nodes among multiple, adjacent bitcells. Other embodiments can include additional ground-connected transistors in a manner that improves writability (e.g., and read noise margin) of the bitcell.

Abstract: A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch.

Abstract: A memory device comprises a tracking control circuit for controlling the write operation or the read operation of the memory device. The tracking control circuit comprises a plurality of tracking cells, wherein the timing characteristics of the tracking cells emulate the timing characteristics of a bit cell during a write operation or a read operation of the memory device. The memory device further comprises at least two reference word lines for configuring the number of tracking cells of the tracking control circuit; and a selection circuit configured to activate one or more of the at least two reference word lines.

Abstract: A static random access memory (SRAM) chip includes a first and second conductor, a set of SRAM cells and a set of first and second tracking cells. The first conductor extends in a first direction, is coupled to a first supply voltage, and on a first metal layer. The second conductor extends in a second direction, is coupled to a second supply voltage, and on a second metal layer. A first cell of the set of first tracking cells includes a first tracking bit line conductor, first and second CMOS, and a first and second pass gate device. A first cell of the set of second tracking cells includes a third pass gate device, a third PU device, and a third PD device having a source configured to be electrically floating. A gate of the first PD device or the first PU device is electrically coupled to the first conductor.

Abstract: A method performed in a data storage device includes reading first representations of data from a non-volatile memory according to multiple sets of read voltages. A first set of read voltages are selected based on the first representations. The method also include generating reliability information that is based on a first generated representation of the data and a second generated representation of the data. The first generated representation of the data corresponds to reading the data from the non-volatile memory according to the first set of read voltages, and the second generated representation of the data corresponds to reading the data from the non-volatile memory according to a second set of read voltages that are offset from the first set of read voltages.

Abstract: A memory access module for performing memory access management of a storage device including a plurality of storage cells includes: sensing means for performing a plurality of sensing operations respectively corresponding to a plurality of different sensing voltages in order to generate a first digital value and a second digital value of a storage cell; processing means for using the first digital value and the second digital value to obtain soft information of a same bit stored in the storage cell; decoding means for using the soft information to perform soft decoding; and controlling means for accessing the storage device. The controlling means includes: storage means for storing a program code; and processing means for executing a program code to control access to the storage device and manage the plurality of storage cells.

Abstract: Multi-bit ferroelectric memory devices and methods of forming the same are provided. One example method of forming a multi-bit ferroelectric memory device can include forming a first ferroelectric material on a first side of a via, removing a material to expose a second side of the via, and forming second ferroelectric material on the second side of the via at a different thickness compared to the first side of the via.

Abstract: Switched memristor analog tuning employs a switch-selectable programmed resistance to tune a resistance-tunable analog circuit. A plurality of switched memristors is to provide the switch-selectable programmed resistance. The resistance-tunable analog circuit is connected to the plurality of switched memristors. The switch-selectable programmed resistance is to tune an analog attribute of the resistance-tunable analog circuit.

Abstract: A nonvolatile memory module including a plurality of memory chips and a module controller on a printed circuit board (PCB) may be provided. Each of the plurality of memory chips may include a plurality of nonvolatile memory cell array layers stacked on a substrate in a three dimensional structure. The module controller may control operations of the plurality of memory chips. The module controller may operate each of the plurality of nonvolatile memory cell array layers included in each of the plurality of memory chips in one of a memory mode, in which a corresponding nonvolatile memory cell array layer is used as a working memory area that temporarily stores data for an operation of the nonvolatile memory module, and a storage mode, in which the corresponding nonvolatile memory cell array layer is used as a storage area that preserves data.

Abstract: Embodiments of the present disclosure generally relate to electronic devices, and more specifically, to multi-level phase change devices. In one embodiment, a memory cell device is provided. The memory cell device generally includes a top surface, a bottom surface and a cell body between the top surface and the bottom surface. The cell body may include a plurality of phase change material layers, which may be used to store data of the cell. In another embodiment, a method of programming a memory cell is provided. The method generally may include applying a sequence of different pulses to each phase change material layer of the cell as the voltage of each pulse in the sequence is ratcheted down from the start of a write cycle to the end of a write cycle.

Abstract: According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.

Abstract: A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction.

Abstract: According to one embodiment, a semiconductor memory device includes: first and second memory cell transistors; first and second bit lines; a first sense amplifier capable of coupling the first bit line to one of first and second power supply lines; and a second sense amplifier capable of coupling the second bit line to one of the first and second power supply lines. A write operation includes first and second steps. In the first step, when the second bit line is uncoupled from the first and second power supply line, the first sense amplifier applies a third voltage to the first bit line. In the second step, when the first bit line is uncoupled from the first and second power supply line, the second sense amplifier applies the second voltage to the second bit line.

Abstract: A programming method for a PMOS multi-time programmable (MTP) flash memory device biases the select gate transistor to a constant drain current level and sweeps the control gate bias voltage from a low voltage level to a high voltage level while maintaining the cell current around a predetermined cell current limit level. In this manner, the PMOS MTP flash memory device can achieve low power and high speed program using hot carrier injection (HCl).

Abstract: There are provided an operating method of a semiconductor memory device including a plurality of memory cells each having one of “n” number of program statuses as a target program status, the operating method comprising: setting a first group of the memory cells, which have a first group of the program statuses as the target program status, to a program permit mode; setting a second group of the memory cells, which have a second group of the program statuses as the target program status, to a program inhibit mode; performing a program operation and a program verification operation to an i-th one of the “n” program statuses in ascending order of level of the program statuses; and changing one or more of the memory cells of the first group of the memory cells having the i-th program status from the program permit mode to the program inhibit mode, and one or more of the memory cells of the second group of the memory cells having an (i+k)th program status to from the program inhibit mode to the program permit mod

Abstract: A read and write control circuit for a flash chip is disclosed which includes a timing control circuit for generating a read and write timing signal for the flash chip, and a first non-volatile memory for storing a plurality of flags corresponding to a plurality of blocks in the flash chip, each of the flags indicating whether a respective one of the blocks that corresponds thereto has been written to normally. Also disclosed is a read and write control method of a flash chip, as well as an AMOLED application circuit having the read and write control circuit for use in an electrical compensation mechanism.

Abstract: Technologies are generally provided for methods and circuitry to rank a large number of cells in a timeframe of about one sense cycle. In some examples, an architecture may be implemented to rank memory cells such as volatile memories, non-volatile memories, and other types of data storage devices, where there may not be an equivalent to threshold voltage. In other examples, an arbitrary group of circuits, such as in neural networks where there may not be an equivalent control gate to set the timing resolution, may be ranked. Relative sense timing may be used to rank the cells having different current carrying abilities. A ramped gate voltage may be used to control the timing resolution and to reduce contention between close separate cells. Digital logic may be used to latch and/or record the rank information.

Abstract: A nonvolatile memory device comprises a cell array including a memory cell. The nonvolatile memory device also includes a reference signal generator configured to generate a reference current for reading data stored in the memory cell. The reference signal generator includes a first circuit coupled to a current summation node and having a reference cell. The first circuit is configured to generate a first current that flows between drain and source terminals of a transistor in the reference cell. The reference signal generator also includes a second circuit coupled to the current summation node and configured to generate a second current that is a temperature-dependent current. The current summation node is configured to combine the first and second currents to generate the reference current that tracks a temperature trend of a current flowing through the memory cell.

Abstract: In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k?n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable adaptive verify voltage adjustment in memory devices. The method includes: (1) in conjunction with decoding data read from non-volatile memory in the non-volatile memory system, determining a plurality of error parameters, (2) determining, in accordance with the plurality of error parameters, a verify adjustment signal, (3) determining whether a verify trigger event has occurred, (4) in accordance with a determination that a verify trigger event has occurred, adjusting a verify voltage in accordance with the verify adjustment signal, and (5) performing data write operations to write data to non-volatile memory in the non-volatile memory system using the adjusted verify voltage to verify the data written using the data write operations.

Abstract: A method to operate a single bit per cell memory comprises erasing a group of memory cells establishing a first logical value by setting threshold voltages in a first range of threshold voltages. First writing, after said erasing, includes programming first selected memory cells to establish a second logical value by setting threshold voltages in a second range of threshold voltages, and saving a sensing state parameter to indicate a first read voltage. Second writing, after said first writing, includes programming second selected memory cells to establish the second logical value by setting threshold voltages in a third range of threshold voltages, and saving the sensing state parameter to indicate a second read voltage. After a number of writings including said first writing and said second writing reaches a threshold number for writing the group of memory cells, the group of memory cells can be erased.

Abstract: A method and circuit for implementing Electronic Fuse (eFuse) visual security of stored data using embedded dynamic random access memory (EDRAM), and a design structure on which the subject circuit resides are provided. The circuit includes EDRAM and eFuse circuitry having an initial state of a logical 0. The outputs of the eFuse and an EDRAM are connected through an exclusive OR (XOR) gate, enabling EDRAM random data to be known at wafer test and programming of the eFuse to provide any desired logical value out of the XORed data combination.

Abstract: A semiconductor device includes: a target block to be tested; a test control block suitable for testing the target block according to a predetermined test process that is based on a test program data; and a test result processing block suitable for generating a processing order data corresponding to a processing order of the test process where failure occurs, based on a test result of the test control block.

Abstract: A memory device that includes a memory cell array and control circuit in which the memory cell array includes a normal region including a first failed block and a redundant region including a first redundant block replacing the first failed block. The control circuit includes a mapping table storing replacement information. The control circuit refers to the mapping table for accessing the first redundant block. When testing the memory device, the control circuit writes “1” in the normal region and the first redundant block, writes “0” in the redundant region except the first redundant block, adds the replacement information regarding a second failed block and second redundant block in the redundant region to the mapping table and verifies the result of replacing the second failed block with the second redundant block based on entire data read from the memory cell array with respect to entire range assigned to the address signal.

Abstract: An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to a plurality of blocks of the memory that are not marked as bad on a block list, perform a code rate test that programs the plurality of blocks of the memory at three or more code rates of an error correction code scheme, and mark any of the plurality of blocks identified as bad during the code rate test on the block list.

Abstract: Disclosed embodiments include fuel assemblies, fuel element, cladding material, methods of making a fuel element, and methods of using same.

Abstract: The invention relates to nuclear technology, and specifically to systems for controlling and protecting nuclear reactors. A drive of an emergency safety rod of a nuclear reactor includes an electric drive, a reduction gear, and a rack-and-pinion gear. The electric drive contains a contactless electric motor based on permanent magnets, which is installed in the housing of the electric drive with a motor rotor position sensor, and a reduction gear for changing the rate of rotation of the electric drive. A toothed rack is installed along the axis of the rack-and-pinion gear in order o provide for the reciprocating motion of a system absorber rod connected thereto. A toothed electromagnetic clutch having a contactless current supply is installed on an inner shaft of the rack-and-pinion gear, enabling the rigid and simultaneous mechanical coupling of half-couplings and the drive contains a reverse-motion coupling, a rack-separation spring and toothed rack position sensors.

Abstract: The present invention relates to a passive heat removal system which circulates cooling fluid via a main water supply line, connected to the lower inlet of a steam generator, and a main steam pipe, connected to the top outlet of the steam generator, to the steam generator, in order to remove sensible heat of a reactor coolant system and residual heat of a core, the passive heat removal system comprising: supplementary equipment for receiving surplus cooling fluid or supplying supplementary cooling fluid in order to maintain the flow rate of the cooling fluid within a predetermined range, wherein the supplementary equipment comprises: a supplementary tank, installed at a predetermined height between the lower inlet and the top outlet of the steam generator, for receiving the surplus cooling fluid or supplying the supplementary cooling fluid, passively, depending on the flow rate of the cooling fluid; a first connection pipe, connected to the main steam pipe and the supplementary tank, for forming a flow path t

Abstract: A rotary device for a nuclear power facility, the rotary device being placed in a circuit for coolant containing radioactive nuclides in the nuclear power facility. The rotary device includes: a casing; and a rotary mechanism provided with, in the casing, a rotor and a rotor shaft that come into contact with the coolant containing the radioactive nuclides passing through the casing. Regarding the casing and the rotary mechanism, at least the rotor and the rotor shaft of the rotary mechanism comprise a low-effective diffusion coefficient alloy having a lower effective diffusion coefficient than a polycrystalline alloy.

Abstract: A method and an apparatus for the treatment of waste ion exchange resins containing radionuclides, and the present invention relates to a method for the treatment of waste ion exchange resins containing radionuclides by the stepwise heat treatment and an apparatus to accomplish the said method.

Abstract: A collimating system for collimating a radiation beam having a first multileaf collimator and a second multileaf collimator configured such that the radiation beam will pass through the first multileaf collimator before passing through the second multileaf collimator, and pass through the second multileaf collimator before hitting its target. The leaves of the first multileaf collimator and the leaves of the second multileaf collimator may be configured to move independently of one another.

Abstract: Electrical Apparatus (100) includes an end of a cable (500) being connected to a transmission optimizer (20), and the cable (500) conducts a current in the range of 0.01 mA to 800 A at a voltage ranges from 12V to 140 KV for the transmission of power, data and signal. The cable (500) includes at least one insulated conductor core formed with an innermost insulating layer (220) disposing around the outside of a conducting layer (210) having carbon fibre or graphite fibre as a conductor core (210). The cable (500) includes a single insulated conductor core to form a single-core cable (300). A reinforcement layer (250) and or a shielding layer (230), (232) being provided around the outside of the innermost insulating layer (220). An outer insulating layer (240) disposes around the outside of the reinforcement layer (250) and the shielding layer. The cable (500) includes multiple numbers of single insulated conductor core to form a multi-core cable (400).

Abstract: A carbon nanotube composite material (1) includes a metal base material (10) and carbon nanotube electrically-conductive path portions (20). The metal base material (10) is made from a polycrystalline substance in which a plurality of rod-shaped metal crystal grains (11) are oriented in a direction. The carbon nanotube electrically-conductive path portions (20) are made from doped carbon nanotubes having a dopant, existing in parts of grain boundaries (15) between the rod-shaped metal crystal grains (11) in a cross section of the metal base material (10), and forming an electrically-conductive path which is electrically conductive in a longitudinal direction of the metal base material (10), by existing along the longitudinal direction (L).

Abstract: Provided is a method of forming a conductive polymer composite. The method includes forming a mixture. The mixture includes a first thermoplastic polymer, a second thermoplastic polymer and a plurality of metal particles. The first thermoplastic polymer and the second thermoplastic polymer are immiscible with each other. The plurality of metal particles include at least one metal that is immiscible with both the first thermoplastic polymer and the second thermoplastic polymer. The method includes heating the mixture to a temperature greater than or equal to a melting point of the metal.