Abstract: Methods of etching silicon nitride faster than silicon oxide are described. Exposed portions of silicon nitride and silicon oxide may both be present on a patterned substrate. A self-assembled monolayer (SAM) is selectively deposited over the silicon oxide but not on the exposed silicon nitride. Molecules of the self-assembled monolayer include a head moiety and a tail moiety, the head moiety forming a bond with the OH group on the exposed silicon oxide portion and the tail moiety extending away from the patterned substrate. A subsequent gas-phase etch using anhydrous vapor-phase HF may then be used to selectively remove silicon nitride much faster than silicon oxide because the SAM has been found to delay the etch and reduce the etch rate.

Abstract: This method for processing a target object includes steps ST1 to ST4. The target object has an organic polymer layer and a resist mask on a substrate. In step ST1, the target object is electrostatically attached to an electrostatic chuck in a plasma processing apparatus. In step ST2, the organic polymer layer is etched through the resist mask by means of a plasma of a first gas. In step ST3, the target object is detached from the electrostatic chuck while a plasma of a second gas is generated. In step 4, the resist mask is peeled off. The second gas is either oxygen gas or a mixture of oxygen gas and a rare gas having an atomic weight lower than that of argon gas.

Abstract: Methods of etching silicon nitride faster than silicon or silicon oxide are described. Methods of selectively depositing additional material onto the silicon nitride are also described. Exposed portions of silicon nitride and silicon oxide may both be present on a patterned substrate. A self-assembled monolayer (SAM) is selectively deposited over the silicon oxide but not on the exposed silicon nitride. Molecules of the self-assembled monolayer include a head moiety and a tail moiety, the head moiety forming a bond with the OH group on the exposed silicon oxide portion and the tail moiety extending away from the patterned substrate. A subsequent exposure to an etchant or a deposition precursor may then be used to selectively remove silicon nitride or to selectively deposit additional material on the silicon nitride.

Abstract: A method of forming a pattern of a semiconductor device includes forming a mask and a sacrificial layer on a substrate, etching the sacrificial layer in a first area of the substrate to form first units, each having a first width and a first distance from an adjacent unit, etching the sacrificial layer in a second area of the substrate to form second units, each having a second width equal to the first distance and being spaced apart from an adjacent unit by a second distance equal to the first width, forming a spacer conformally covering the first and second units, the spacer having a first thickness and being merged between the second units, removing a portion of the spacer on upper surfaces of the first and second units, and etching the mask in a region from which first and second units have been removed.

Abstract: A power semiconductor module is produced by: providing an electrically conductive terminal block having a screw thread, a connecting conductor having first and second sections, a module housing, a circuit carrier having a dielectric insulation carrier and an upper metallization layer on an upper side of the insulation carrier, and a semiconductor component; fitting the semiconductor component on the circuit carrier; producing a firm and electrically conductive connection between the terminal block and the connecting conductor at the first section; producing a material-fit and electrically conductive connection between the circuit carrier or the semiconductor component and the connecting conductor at the second section; and arranging the terminal block and the circuit carrier fitted with the semiconductor component on the module housing so the semiconductor component is arranged in the module housing and the screw thread is accessible from an outer side of the module housing.

Abstract: A passivation method for a silicon carbide (SiC) surface may include steps of providing a silicon carbide surface, depositing a thin metal layer on the silicon carbide surface, forming a first passivation layer on the metal layer at low temperature, and generating a dielectric layer by a reaction between a gas/liquid ambient and the thin metal layer. In one embodiment, the thin metal layer is deposited on the silicon carbide surface by sputtering, e-beam evaporation, electroplating, etc. In another embodiment, the metal may include, but not limited to, aluminum, magnesium, etc. In a further embodiment, the passivation layer can be a low temperature oxide and/or nitride layer. In still a further embodiment, the dielectric layer can be aluminum oxide, titanium di-oxide etc. The passivation method for a silicon carbide (SiC) may further include a step of forming a second passivation layer on the first passivation layer.

Abstract: A method for fabricating an optical multi-chip module (MCM) includes temporarily curing an underfill material on a chip including an optical device to prevent flow of the underfill material. The chip is flip-chip mounted on a waveguide module having a minor for directing light to or from the chip, wherein the underfill material is disposed between the chip and the waveguide module. The underfill material is cured to adhere the chip to the waveguide module.

Abstract: The present disclosure is directed to fluid filtering systems and methods for use during semiconductor processing. One or more embodiments are directed to fluid filtering systems and methods for filtering ions and particles from a fluid as the fluid is being provided to a semiconductor wafer processing tool, such as to a semiconductor wafer cleaning tool.

Abstract: In a substrate processing apparatus, gas is supplied from above a shield plate to a lid internal space within a chamber so that pressure in the lid internal space becomes higher than pressure in a chamber-body internal space and the gas in the lid internal space is sent to the chamber-body internal space. The gas flowing from the lid internal space is discharged through a body discharge port provided below a substrate in the chamber-body internal space. This forms a generally cylindrical current of gas in the chamber. The supply of processing liquids to an upper surface of the substrate is conducted on the inner side of the generally cylindrical current. This suppresses mists and fumes of processing liquids passing through the generally cylindrical current and entering into the lid internal space from the gap between the shield plate and the lid bottom part.

Abstract: A substrate processing method in which processes with respect to substrates are performed comprises: stacking the substrates on a substrate holder disposed in a staking space formed within a lower chamber through a passage formed in a side of the lower chamber, exhausting the stacking space through an auxiliary exhaust port connected to the stacking space, moving the substrate holder into an external reaction tube closing an opened upper side of the lower chamber to provide a process space in which the processes are performed, and supplying a reaction gas into the process space using a supply nozzle connected to the process space and exhausting the process space using an exhaust nozzle connected to the process space and an exhaust port connected to the exhaust nozzle.

Abstract: An electric-programmable magnetic module comprising a micro electro mechanical system (MEMS) chip and a bonding equipment is provided. The MEMS chip comprises a plurality of electromagnetic coils and each of the electromagnetic coils is individually controlled. The MEMS chip is assembled with and carried by the bonding equipment.

Abstract: A semiconductor processing station is provided. The semiconductor processing station includes a first platform, a second platform and a vacuum tunnel, wherein the first platform has a first load lock and a first plurality of chambers, and the second platform has a second load lock and a second plurality of chambers, and the vacuum tunnel connects the first and the second load locks.

Abstract: A device for processing wafer-shaped articles comprises a rotary chuck mounted for rotation within a surrounding enclosure. The rotary chuck has mounted therein at least one sensor, a microprocessor connected to the at least one sensor so as to receive output signals therefrom, and a wireless transmitter connected to the microprocessor so as to receive output signals therefrom and transmit signals exteriorly of the device.

Abstract: There is provided a method of measuring a temperature of a gas in a line connected to a gas supply source and a decompressor, the line being divided by a first, a second and a third valve into a first line between the first valve and the second valve and a second line between the second valve and the third valve. A first pressure rise rate of a gas in the first line is measured when introducing a gas at a predetermined flow rate into the first and the second line. A second pressure rise rate of a gas in the first line is measured when introducing a gas at a predetermined flow rate only into the first line. A gas temperature in the first line is calculated based on known inner volume of the second line, the first pressure rise rate, and the second pressure rise rate.

Abstract: Implementations of the present disclosure generally relate to an improved factory interface that is coupled to an on-board metrology housing configured for measuring film properties of a substrate. In one implementation, an apparatus comprises a factory interface, and a metrology housing removably coupled to the factory interface through a load port, the metrology housing comprises an on-board metrology assembly for measuring properties of a substrate to be transferred into the metrology housing.

Abstract: A polishing method capable of obtaining a stable film thickness without being affected by a difference in measurement position is disclosed. The polishing method includes: rotating a polishing table that supports a polishing pad; pressing the surface of the wafer against the polishing pad; obtaining a plurality of film-thickness signals from a film thickness sensor during a latest predetermined number of revolutions of the polishing pad, the film thickness sensor being installed in the polishing table; determining a plurality of measured film thicknesses from the plurality of film-thickness signals; determining an estimated film thickness at a topmost portion of the raised portion based on the plurality of measured film thicknesses; and monitoring polishing of the wafer based on the estimated film thickness at the topmost portion of the raised portion.

Abstract: According to one embodiment, an alignment method includes calculating a position gap of a predetermined point in a device area of a wafer based on a stress applied to the device area, and correcting an exposure condition in a lithography process of the device area based on the position gap of the predetermined point.

Abstract: A substrate support for supporting a substrate in a substrate processing system includes a plurality of thermal elements. The thermal elements are arranged in one or more thermal zones, and each of the thermal zones includes at least one of the thermal elements. Each of the thermal elements includes a first resistive material having a positive thermal coefficient of resistance and a second resistive material having a negative thermal coefficient of resistance. The second resistive material is electrically connected to the first material. At least one of the first resistive material and the second resistive material of each of the thermal elements is electrically connected to a power supply to receive power, and each of the thermal elements heats a respective one of the thermal zones based on the received power. At least one ceramic layer is arranged adjacent to the thermal elements.

Abstract: In various aspects of the disclosure, a semiconductor substrate processing system may include an electrostatic chuck for holding a semiconductor substrate attached to an electrically insulating carrier; and an AC power supply electrically coupled to the electrostatic chuck.

Abstract: An adhesive composition for temporarily attaching a substrate to a support plate which supports the substrate, including a thermoplastic resin and a release agent.

Abstract: A substrate holding apparatus that can minimize a deflection amount of a substrate due to its own weight and can suppress vibration of the substrate at the time of rotation of the substrate even if a diameter of the substrate becomes large is disclosed. The substrate holding apparatus holds a periphery of a substrate and rotates the substrate. The substrate holding apparatus includes a plurality of support posts supported by a base and vertically movable relative to the base, a plurality of chucks respectively provided on the plurality of support posts and configured to hold the periphery of the substrate, and at least one support pin configured to support a lower surface of the substrate held by the plurality of chucks.

Abstract: A method of fabricating a semiconductor device can include the following steps: (i) providing an initial sub-assembly including a trench-defining layer having a top surface; (ii) refining the initial sub-assembly into a first trench-cut intermediate sub-assembly by removing material to form an upper tier of a trench extending downward from the top surface of the trench-defining layer, the upper tier of the trench including two lateral trench surfaces and a bottom trench surface; and (iii) refining the first trench-cut intermediate sub-assembly into a second trench-cut intermediate sub-assembly by selectively removing material in a downwards direction starting from the bottom surface of the trench to form a lower tier of the trench, with the selective removal of material leaving at least a first defect blocking member in the lower tier of the trench.

Abstract: A semiconductor structure including one or more semiconductor devices on a wafer. The one or more devices having source/drain junctions. The semiconductor structure further includes a recessed middle-of-line (MOL) oxide layer, and an air-gap oxide layer including one or more introduced air-gaps. The air-gap oxide layer is positioned over the one or more semiconductor devices and the MOL oxide layer. A nitride layer is positioned over the one or more semiconductor devices. Trenches are formed through the nitride layer down to the source/drain junctions. A silicide fills the trenches.

Abstract: A method of manufacturing a semiconductor device includes forming a frame trench extending from a first surface into a base substrate, forming, in the frame trench, an edge termination structure comprising a glass structure, forming a conductive layer on the semiconductor substrate and the edge termination structure, and removing a portion of the conductive layer above the edge termination structure. A remnant portion of the conductive layer forms a conductive structure that covers a portion of the edge termination structure directly adjoining a sidewall of the frame trench.

Abstract: According to various embodiments, a method may include: providing a substrate having a first side and a second side opposite the first side; forming a buried layer at least one of in or over the substrate by processing the first side of the substrate; thinning the substrate from the second side of the substrate, wherein the buried layer includes a solid state compound having a greater resistance to the thinning than the substrate and wherein the thinning stops at the buried layer.

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a metal gate stack formed over the semiconductor substrate. The semiconductor device also includes an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the metal gate stack includes a metal gate electrode. The semiconductor device further includes a metal oxide structure formed over the insulating layer and in direct contact with the insulating layer. The metal oxide structure includes an oxidized material of the metal gate electrode.

Abstract: Some embodiments of the present disclosure provide a semiconductive device. The semiconductive device includes a first conductive layer and a second conductive layer above the first conductive layer. The second conductive layer includes a first portion and a second portion protruding from the first portion. A via structure is under the second conductive layer and on top of the first conductive layer. The via structure is substantially aligned vertically with the second portion.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes receiving a substrate with two sections of conductors thereon that are adjacent to each other, and a valley between the two sections of the conductors, filling the valley with a first passivation material to form a passivation valley, applying a second passivation material overlying the two sections of conductors and the passivation valley and over the substrate, and removing the second passivation material overlying the two sections of conductors and the passivation valley, and the second passivation material over the substrate but not in contact with the two sections of conductors and the passivation valley.

Abstract: A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.

Abstract: Methods, apparatus, and systems for fabricating a semiconductor device comprising a semiconductor substrate; an oxide layer above the semiconductor substrate; a first metal component comprising tungsten disposed within the oxide layer; an interlayer dielectric (ILD) above the oxide layer, wherein the ILD comprises a trench and a bottom of the trench comprises at least a portion of the top of the first metal component; a barrier material disposed on sidewalls and the bottom of the trench; and a second metal component disposed in the trench.

Abstract: Methods for forming metal contacts having tungsten liner layers are provided herein. In some embodiments, a method of processing a substrate includes: exposing a substrate, within a first substrate process chamber, to a plasma formed from a first gas comprising a metal organic tungsten precursor gas or a fluorine-free tungsten halide precursor to deposit a tungsten liner layer, wherein the tungsten liner layer is deposited atop a dielectric layer and within a feature formed in a first surface of the dielectric layer of a substrate; transferring the substrate to a second substrate process chamber without exposing the substrate to atmosphere; and exposing the substrate to a second gas comprising a tungsten fluoride precursor to deposit a tungsten fill layer atop the tungsten liner layer.

Abstract: A metal first, via first process for forming interconnects within a metallization layer of a semiconductor device is provided. In an embodiment a conductive material is deposited and the conductive material is patterned into a conductive line and a via. A dielectric material is deposited over the conductive line and the via, and the dielectric material and the via are planarized.

Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

Abstract: A semiconductor device and method of making the same, wherein in accordance with an embodiment of the present invention, the device includes a first conductive line including a first conductive material, and a second conductive line including a second conductive material. A via connects the first conductive line to the second conductive line, wherein the via includes conductive via material, wherein the via material top surface is coated with a liner material, wherein the via is a bottomless via.

Abstract: Apparatuses and methods are disclosed herein for densification of through substrate insulating liners. An example method may include forming a through substrate via through at least a portion of a substrate, forming a first liner layer in the through substrate via, and densifying the first liner layer. The example method may further include forming a second liner layer on the first liner layer, and densifying the second liner layer.

Abstract: Structures and processes include a single metallization step for forming a metal nitride liner layer suitable for contact formation. The structure and processes generally includes forming a nitrogen-enriched surface in a deposited metal liner layer or forming a nitrogen-enriched surface in the dielectric material prior to deposition of the metal liner layer. In this manner, nitridization of the metal occurs upon deposition of nitrogen ions into the metal liner layer and/or as a function of additional conventional processing in fabricating the integrated circuit such that the deposited nitrogen ions diffuse into at least a portion of the metal liner layer. As a consequence, only a single metal layer deposition step is needed to form the metal liner layer.

Abstract: A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The porogen comprises an organic ring structure with fewer than fifteen carbons and a large percentage of single bonds. Additionally, the porogen may have a viscosity greater than 1.3 and a Reynolds numbers less than 0.5.

Abstract: A semiconductor memory device is disclosed. The semiconductor memory device includes a substrate including cell and peripheral regions, a stack on the cell region, vertical channel portions vertically penetrating the stack, a contact structure penetrating the stack, an insulating structure on the peripheral region, an impurity region in the peripheral region of the substrate, and a first contact penetrating the insulating structure and connected to the impurity region. The stack includes gate electrodes sequentially stacked on the substrate, and the contact structure is spaced apart from the vertical channel portions. A top surface of the first contact is positioned at a lower level than that of the contact structure.

Abstract: A wafer via solder filling device includes a solder bath comprising an accommodation space for accommodating a molten solder, with an open top, and an air outlet for exhausting air from the accommodation space; a fixing unit for fixing the wafer having a via formed in one surface in the accommodation space to seal the accommodation space airtight; and a pressing unit for pressing a bottom of the molten solder arranged in the solder bath and moving the molten solder upward, to fill the molten solder in the via.

Abstract: A semiconductor package is disclosed, which includes: a packaging substrate; a semiconductor element disposed on the packaging substrate in a flip-chip manner; a stopping portion formed at edges of the semiconductor element; an insulating layer formed on an active surface of the semiconductor element and the stopping portion; and an encapsulant formed between the packaging substrate and the insulating layer. The insulating layer has a recessed portion formed on the stopping portion and facing the packaging substrate such that during a reliability test, the recessed portion can prevent delamination occurring between the insulating layer and the stopping portion from extending to the active surface of the semiconductor element.

Abstract: In one example, a device includes a p-type field effect transistor region and n-type field effect transistor region. The p-type field effect transistor region includes at least one fin including strained germanium. The n-type field effect transistor region also includes at least one fin including strained germanium.

Abstract: A semiconductor device is provided that includes a first plurality of fin structures having a first width in a first region of a substrate, and a second plurality of fin structures having a second width in a second region of the substrate, the second width being less than the first width. A first gate structure is formed on the first plurality of fin structures including a first high-k gate dielectric that is in direct contact with a channel region of the first plurality of fin structures and a first gate conductor. A second gate structure is formed on the second plurality of fin structures including a high voltage gate dielectric that is in direct contact with a channel region of the second plurality of fin structures, a second high-k gate dielectric and a second gate conductor.

Abstract: In a FinFET device, the gate cut is performed post-RMG. This allows PC-past-RX to be scaled to the thickness of the gate stack, thus reducing PC end parasitic capacitance and improving device performance. Specifically, the gate stack integration is completed first, and then the gates are cut using a lithographically-defined CT mask and selective etching of the gate stack metals, and optically the gate dielectric. The selective etch allows the cut to be located as close as possible to the fins without adversely affecting source and drain epitaxial doping layers, even when the cut opening overlaps with the epitaxial layers.

Abstract: A semiconductor device a first epitaxially grown source/drain region comprising a first material arranged on a first fin, a second epitaxially grown source/drain region comprising the first material arranged on the second fin, the second epitaxially grown source/drain region arranged above the first epitaxially grown source/drain region, a third epitaxially grown source/drain region comprising the first material arranged on a second fin, a fourth epitaxially grown source/drain region comprising a second material arranged on the second fin, the fourth epitaxially grown source/drain region arranged above the third epitaxially grown source/drain region, and a gate stack arranged over a channel region of the first fin and a channel region of the second fin.

Abstract: In one example, a device includes a p-type field effect transistor region and n-type field effect transistor region. The p-type field effect transistor region includes at least one fin including strained germanium. The n-type field effect transistor region also includes at least one fin including strained germanium.

Abstract: Silicon fins are formed in a bulk silicon substrate and thereafter trench isolation regions are formed between each silicon fin. The silicon fins in nFET and pFET device regions are then recessed. A relaxed silicon germanium alloy fin portion is formed on a topmost surface of each recessed silicon fin portion or on exposed surface of the substrate. A compressively strained silicon germanium alloy fin portion is formed on each relaxed silicon germanium alloy fin portion within the pFET device region, and a strained silicon-containing fin portion is formed on each relaxed silicon germanium alloy fin portion within the nFET device region. Sidewall surfaces of each compressively strained silicon-containing germanium alloy fin portion and each tensile strained silicon-containing fin portion are then exposed. A functional gate structure is provided on the exposed sidewall surfaces of each compressively strained silicon-containing germanium alloy fin portion and each tensile strained silicon-containing fin portion.

Abstract: An approach to forming a semiconductor structure with improved negative bias temperature instability includes diffusing fluorine atoms into a semiconductor structure by an anneal in a fluorine containing gas. The approach includes removing a pFET work function metal layer from an area above an nFET wherein the area above the nFET includes at least the area over the nFET. Additionally, the approach includes depositing a layer of nFET work function metal on a remaining portion of the pFET work function metal and depositing a gate metal over the nFET work function metal layer. Furthermore, the method includes performing an anneal in a reducing environment followed by a high temperature anneal.

Abstract: A method of manufacturing a semiconductor device may include forming first trenches that define active patterns extending in a first direction on a substrate, forming first insulating layers filling the first trenches, forming first mask patterns extending in the first direction while having a first width along a second direction perpendicular to the first direction, forming a second mask pattern extending in the first direction while having a second width along the second direction, and forming a second trench that partly defines an active region by executing a first etching process that etches the active patterns and the first insulating layer using the first mask patterns and the second mask pattern.

Abstract: A method for preventing damage to the insulator layer of a semiconductor device during creation of fin field effect transistor (FinFET) includes obtaining a material stack having an active semiconductor layer, an insulator layer, and an etch stop layer between the active semiconductor layer and the insulator layer; forming a fin-array from the active semiconductor layer; patterning the fin-array; and fabricating a FinFET device from the patterned fin-array; where the etch stop layer is resistant to processes the etch stop layer is exposed to during the forming, patterning, and fabricating operations, such that the etch stop layer and the insulator layer are not damaged during the forming, patterning, and fabricating operations.

Abstract: The method includes classifying sample pattern data into a standard normal group and a standard weak group based on a first criterion. The method further includes extracting a normal group determination function by calculating an image parameter with respect to each piece of sample pattern data included in the standard normal group, and extracting a weak group determination function by calculating the image parameter with respect to each piece of sample pattern data included in the standard weak group. The method also includes classifying the object pattern data into a normal group and a weak group by calculating the image parameter with respect to object pattern data based on a first proximity between the normal group determination function and the object pattern data and a second proximity between the weak group determination function and the object pattern data.