Abstract: A system deposits a film on a substrate while determining mechanical stress experienced by the film. A substrate is provided in a deposition chamber. A support disposed in the chamber supports a circular portion of the substrate with a first surface of the substrate facing a deposition source and a second surface being reflective. An optical displacement sensor is positioned in the deposition chamber in a spaced-apart relationship with respect to a portion of the substrate's second surface located at approximately the center of the circular portion of the substrate. When the deposition source deposits a film on the first surface, a displacement of the substrate is measured using the optical displacement sensor. A processor is programmed to use the substrate displacement to determine a radius of curvature of the substrate, and to use the radius of curvature to determine mechanical stress experienced by the film during deposition.

Abstract: Methods and systems for imaging and cutting semiconductor wafers and other microelectronic device substrates are disclosed herein. In one embodiment, a system for singulating microelectronic devices from a substrate includes an X-ray imaging system having an X-ray source spaced apart from an X-ray detector. The X-ray source can emit a beam of X-rays through the substrate and onto the X-ray detector, and X-ray detector can generate an X-ray image of at least a portion of the substrate. A method in accordance with another embodiment includes detecting spacing information for irregularly spaced dies of a semiconductor workpiece. The method can further include automatically controlling a process for singulating the dies of the semiconductor workpiece, based at least in part on the spacing information. For example, individual dies can be singulated from a workpiece via non-straight line cuts and/or multiple cutter passes.

Abstract: A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.

Abstract: A container for housing an electronic component includes: a container body including a bottom plate and a polygonal side wall surrounding a central region of the bottom plate, the container body housing an electronic component inside a cavity defined by the bottom plate and the polygonal side wall; and an input-output terminal that penetrates through the polygonal side wall and is attached to two sides of the polygonal side wall, wherein a first side of the polygonal side wall is adjacent to a second side of the polygonal side wall, wherein the input-output terminal includes an insulator and a conductor, and wherein the conductor penetrates through the insulator and provides electrical continuity between an interior portion of the polygonal side wall and an exterior portion of the polygonal side wall.

Abstract: A chip package includes a chip, a first adhesive layer, a second adhesive layer, and a protection cap. The chip has a sensing area, a first surface, a second surface that is opposite to the first surface, and a side surface adjacent to the first and second surfaces. The sensing area is located on the first surface. The first adhesive layer covers the first surface of the chip. The second adhesive layer is located on the first adhesive layer, such that the first adhesive layer is between the first surface and the second adhesive layer. The protection cap has a bottom board and a sidewall that surrounds the bottom board. The bottom board covers the second adhesive layer, and the sidewall covers the side surface of the chip.

Abstract: A surface defined by a wafer level package (WLP) region and an external region, and A system and method for forming a wafer level package. In one example, a substrate used in the wafer level package includes a layer of getter material is disposed on at least a portion of the external region. According to one embodiment, the external region comprises a saw-to-reveal (STR) region of the wafer.

Abstract: A method for simultaneously making a plurality of microelectronic packages by forming an electrically conductive redistribution structure along with a plurality of microelectronic element attachment regions on a carrier. The attachment regions being spaced apart from one another and overlying the carrier. The method also including the formation of conductive connector elements between adjacent attachment regions. Each connector element having the first or second end adjacent the carrier and the remaining end at a height of the microelectronic element. The method also includes forming an encapsulation over portions of the connector elements and subsequently singulating the assembly. into microelectronic units, each including a microelectronic element.

Abstract: A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, a backside and side surfaces extending between the major surface and the backside. The semiconductor device also includes at least one metal layer extending across the backside of the substrate. A peripheral part of the at least one metal layer located at the edge of the substrate between the backside and at least one of the side surfaces extends towards a plane containing the major surface. This can prevent burrs located at the peripheral part of the at least one metal layer interfering with the mounting of the backside of the substrate on the surface of a carrier.

Abstract: Conductive paths through a dielectric are described that have a high aspect ratio for semiconductor devices. In one example, a semiconductor device package has a semiconductor substrate having circuitry formed on the substrate. A plurality of conductive connection pads are on the semiconductor substrate to connect to the circuitry. A post is on each of a subset of the connection pads, the posts being formed of a conductive material. A dielectric layer is over the semiconductor substrate including over the connection pads and the posts.

Abstract: A fan-out semiconductor package and an electronic device including the same are provided. The fan-out semiconductor package includes a semiconductor chip; an interconnection member electrically connected to the semiconductor chip and having a connection terminal pad; and a passivation layer disposed at one side of the interconnection member and having an opening part opening a portion of the connection terminal pad. Distances from a center of the connection terminal pad to at least two points of an edge thereof are different from each other.

Abstract: A manufacturing method of a semiconductor device includes: forming a mark on a surface of a semiconductor wafer, at least a part of the mark being disposed in a planned-peripheral region, the planned-peripheral region being located around a respective planned-element region where a semiconductor element is to be formed; forming the semiconductor element in the planned-element region using the mark; forming a film that extends across a range including the planned-element region or the planned-peripheral region in the surface so as to cover at least a part of the mark with the film, after forming the semiconductor element; and after forming the film, cutting the semiconductor wafer along a dicing region, the dicing region located around the planned-peripheral region.

Abstract: A semiconductor device includes a substrate; a semiconductor layer; a first protective film; a first adhesive layer disposed on the first protective film; an electrode pad disposed on the first protective film; a second protective film disposed to cover and be in contact with the electrode pad and the first adhesive layer; and a first opening formed in part of the second protective film such that the upper surface of the electrode pad is exposed, wherein in a plan view, the first adhesive layer includes a first projection projecting from the electrode pad radially in a direction of the periphery of the electrode pad and continuously surrounding the periphery of the electrode pad; and the second protective film is continuously to cover and contact part of the upper and side surfaces of the electrode pad, the upper and side surfaces of first projection, and the first protective film.

Abstract: According to one embodiment, a display device includes a first substrate including a display area containing a plurality of pixels and a non-display area, a drive circuitry on the non-display area of the first substrate and connected to the plurality of pixels, a second substrate opposed to the first substrate, a touch sensor including detection electrodes on the second substrate, and a third substrate including first wiring lines connected to the detection electrodes and a heat radiation layer thermally connected to the drive circuitry.

Abstract: A semiconductor device includes: a processor having a heat sink mounted thereon; and an optical module having a heat transfer interposer, wherein the heat sink and the optical module are coupled to each other via the heat transfer interposer. And a semiconductor device includes: a semiconductor chip mounted on a substrate; a lead that covers the semiconductor chip; a heat sink installed on the lead; and an optical module coupled to the heat sink via a heat transfer interposer.

Abstract: Electrical package including bimetal lid. The electrical package includes: an organic substrate; a semiconductor chip electrically connected to electrical pads on a surface of the organic substrate via a plurality of solder balls; and a lid for encapsulating the semiconductor chip on the organic substrate, wherein (i) an inner surface of a central part of the lid is connected to a surface of the semiconductor chip via a first TIM, (ii) an inner surface of an outer part of the lid is hermetically connected to the surface of the organic substrate, and (iii) the lid has a bimetal structure including at least two different metals. A circuit module is also provided.

Abstract: A semiconductor package includes a semiconductor die comprising a control transistor and a sync transistor, an integrated output inductor comprising a winding around a core, and coupled to the semiconductor die. The winding comprises a plurality of conductive clips situated above a printed circuit board (PCB) and connected to a plurality of conductive segments in the PCB. The control transistor and the sync transistor are configured as a half-bridge. The integrated output inductor is coupled to a switched node of the half-bridge. At least one of the plurality of conductive clips includes a partially etched portion and a non-etched portion. The semiconductor die is attached to the integrated output inductor by a die attach material. The semiconductor die and the integrated output inductor are encapsulated in a molding compound.

Abstract: In an example, a silicone-based thermal interface material includes a thermally conductive material and a silicone-based polymeric material having a solubility parameter that is not less than 9.09 cal1/2 cm?3/2.

Abstract: An ESD protection device including a Si substrate with an ESD protection circuit formed at the surface of the substrate; pads formed on the Si substrate; a rewiring layer opposed to the surface of the Si substrate, which includes terminal electrodes electrically connected to the pads. The rewiring layer includes a SiN protection film formed on the surface of the Si substrate to cover parts of the pads except regions in contact with openings (contact holes) formed in a resin layer, and the resin layer that is lower in dielectric constant than the SiN protection film, and formed between the SiN protection film and the terminal electrodes. Thus, provided is a semiconductor device which can reduce the generation of parasitic capacitance, and eliminates variation in parasitic capacitance generated.

Abstract: A semiconductor package includes an extendible molding member, a chip embedded in the molding member to have a warped shape, and connectors disposed in the molding member. First surfaces of the connectors are exposed at a surface of the molding member, and second surfaces of the connectors are coupled to the chip.

Abstract: A first lead terminal, a second lead terminal provided parallel to the first lead terminal, and a tie bar connecting the first lead terminal and the second lead terminal are provided. The tie bar includes a first narrow-width section touching the first lead terminal, a second narrow-width section touching the second lead terminal, and a wide-width section having a larger width than the first narrow-width section and the second narrow-width section and connecting the first narrow-width section and the second narrow-width section. The wide-width section has a through-hole formed between the first narrow-width section and the second narrow-width section.

Abstract: A power electronic switching device having plurality of potential surfaces. At least two different potentials are respectively assigned to at least one of the potential surfaces. A plurality of semiconductor components are arranged in an n×m matrix, oriented in the x-y-direction, on a first conductor track, formed by at least one potential surface of the first potential. The semiconductor components are connected in parallel with one another and form a current valve. In this case, the semiconductor components can be distributed among a plurality of potential surfaces of the first potential which form the first conductor track.

Abstract: Provided is a semiconductor package. The semiconductor package includes: a first die that is a monolithic type die, a driver circuit and a low-side output power device formed in the first die; a second die disposed above the first die, the second die comprising a high-side output power device; and a first connection unit disposed between the first die and the second die.

Abstract: Methods and systems for improved matching of on-chip capacitors may comprise a semiconductor die with an on-chip capacitor comprising one or more metal layers. The on-chip capacitor may comprise interdigitated electrically coupled metal fingers. The electrically coupled metal fingers may be arranged symmetrically in the semiconductor die to compensate for non-uniformities in the one or more metal layers. The metal fingers may be arranged with radial symmetry. Metal fingers in a first metal layer may be electrically coupled to metal fingers in a second metal layer. An orientation of metal fingers may be alternated when coupling metal fingers in a plurality of metal layers. The metal fingers may be coupled at the center or the outer edge of the on-chip capacitor. The on-chip capacitor may be configured in a plurality of symmetric sections wherein a boundary between each of the plurality of sections is configured in a zig-zag pattern.

Abstract: A connection member according to an embodiment includes a dielectric material, a penetrating via penetrating through the dielectric material, a first metal plane provided in the dielectric material, the first metal plane being perpendicular to an extension direction of the penetrating via, the first metal plane crossing the penetrating via, and a second metal plane provided n or on the dielectric material in parallel with the extension direction of the penetrating via, the second metal plane connected to the first metal plane.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

Abstract: A package system comprising a first interconnect structure arranged over a first surface of a first substrate; a plurality of first through silicon via (TSV) structures in and extending through the first substrate; a molding compound material surrounding the first substrate; at least one through via in the molding compound material with the through via being offset from the first substrate in a direction parallel to the first surface; a second interconnect structure over a second surface of the first substrate; and a first integrated circuit mounted over the first surface of the substrate, with the first integrated circuit being electrically coupled to at least one of the first TSV structures through the first interconnect structure and a connecting bump while the first interconnection structure is electrically coupled to the through via.

Abstract: A met of fabricating an electronic package is provided, g: providing a carrier body haying a first surface formed with a plurality of recessed portions, and a second surface opposing the first surface and interconnecting with the recessed portions; forming on the first surface of the carrier body an electronic structure that has a plurality of conductive elements received in the recessed portions correspondingly; and removing a portion of the carrier body, with the conductive elements exposed from the second surface of the carrier body. Therefore, the carrier body is retained, and the fabrication cost is reduced since no temporary material is required. The present invention further provides the electronic package thus fabricated.

Abstract: To provide a technique capable of easily forming a resin opening of a desired shape. As a solution, a base is prepared which has a first surface region and a second surface region around the first surface region, and which has a wiring formed thereon. Subsequently, a resist which covers the first surface region is formed. Then, the first surface region and the second surface region are covered with a resin body such that the resist is included therein, and the resist is exposed from the resin body. After that, the exposed resist is removed, so that a resin opening that exposes the base in the first surface region is formed in the resin body.

Abstract: A wiring board according to the present invention includes: an insulating base including a main face, a side face, and a notch portion opened in the main face and the side face; and an inner-face electrode disposed on the inner face of the notch portion and to be connected to an external circuit board with solder therebetween. In such a wiring board, the inner-face electrode contains nickel and gold at a surface portion thereof, more nickel than gold at a surface in an outer periphery section, and more gold than nickel at a surface in an inner region.

Abstract: A through-electrode substrate includes a base including a first surface and a second surface mutually opposing each other, and a through-electrode arranged in a through-hole passing through the second surface from the first surface of the base, wherein the through-electrode includes an first end surface of the first surface side and an second end surface of the second surface side exposed from the base in the first surface and the second surface, and a periphery edge of one or both of the first end surface of the first surface side and the second end surface of the second surface side is covered by a part of the base.

Abstract: A circuit substrate for a chip bonding thereon includes a core substrate having a chip-side surface and a bump-side surface opposite to the chip-side surface, a first through via plug passing through the core substrate, a pad disposed on the bump-side surface, in contact with the first through via plug, and a first thickness enhancing conductive pattern disposed on a surface of the pad, which is away from the bump-side surface.

Abstract: A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over a portion of the encapsulant within an interconnect site outside a footprint of the semiconductor die. An opening is formed through the first insulating layer within the interconnect site to expose the encapsulant. The opening can be ring-shaped or vias around the interconnect site and within a central region of the interconnect site to expose the encapsulant. A first conductive layer is formed over the first insulating layer to follow a contour of the first insulating layer. A second conductive layer is formed over the first conductive layer and exposed encapsulant. A second insulating layer is formed over the second conductive layer. A bump is formed over the second conductive layer in the interconnect site.

Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.

Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts).

Abstract: This disclosure provides a package substrate which includes a rigid dielectric material layer, a first wiring layer having at least one first metal wire formed on the rigid dielectric material layer, and a first flexible dielectric material layer formed on the first wiring layer.

Abstract: A screen control module of a mobile electronic device has at least one controller formed on a circuit board. The circuit board has multiple solder pads formed on the circuit board and respectively aligning along a first direction and a second direction. An amount of the solder pads along the first direction is greater than that along the second direction. The controller is formed by an integrated circuit with a package, and the aspect ratio of the package is not less than 2. The package has multiple electrical contacts respectively aligning along a length direction and a width direction. Each electrical contact aligns with and is electrically connected to a corresponding solder pad. Accordingly, the screen control module mounted within a side frame of a display of the mobile electronic device can increase the aspect ratio to meet the demand for narrowing the side frame of the display.

Abstract: A semiconductor processing method and semiconductor device are described. The processing method includes forming a p-doped germanium structure on a substrate, annealing the p-doped germanium structure using pulses of laser radiation, and forming a titanium structure in direct contact with the p-doped germanium structure.

Abstract: A semiconductor device including: a conductor disposed on a substrate; a first contact disposed on the conductor; a second contact having a first portion disposed on the first contact and a second portion protruded away from the first portion in a direction parallel to the substrate, wherein the first and second contacts are disposed in an insulating layer; a via disposed on the insulating layer and the second portion of the second contact; and a metal line disposed on the via.

Abstract: Various embodiments of transistor assemblies, integrated circuit devices, and related methods are disclosed herein. In some embodiments, a transistor assembly may include a base layer in which a transistor is disposed, a first metal layer, and a second metal layer disposed between the base layer and the first metal layer. The transistor assembly may also include a capacitor, including a sheet of conductive material with a channel therein, disposed in the base layer or the second metal layer and coupled to a supply line of the transistor. Other embodiments may be disclosed and/or claimed.

Abstract: An electrical contact structure for an integrated circuit device is described. A first patterned dielectric layer comprising at least one contact hole, the contact hole including a bottom surface, and sidewalls extending from the bottom surface to a top surface is provided. The bottom surface of the dielectric layer is in contact with a lower layer of the integrated circuit device. A tungsten via is disposed within the at least one contact hole, the tungsten via having a bottom surface in contact with the lower layer and a top surface. A tungsten nitride layer is disposed on the top surface of the tungsten via to repair etch damage done to the tungsten via.

Abstract: A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask includes first and second insulating layers and a metal layer in between the insulating layers; defining a trench pattern through the first insulating layer and metal layer, the trench pattern having a first width; defining a first via pattern in a lithographic mask over the trench pattern, the first via pattern having a second width that is larger than the first width; growing a metal capping layer on an exposed sidewall of the trench pattern to decrease the first width to a third width that defines a second via pattern; transferring the trench pattern into the ILD layer to form a trench; and transferring the second via pattern through the ILD layer and into the metal wiring layer to form a via.

Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.

Abstract: An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a semiconductor substrate, a wiring structure formed over the semiconductor substrate and including a plurality of wiring layers, and a first coil, a second coil, and a third coil which are formed above the semiconductor substrate. In a region located under the first coil and overlapping the first coil in plan view, the second and third coils CL2a and CL2b are disposed. The second and third coils are foamed in the same layer and electrically coupled in series to each other. Each of the second and third coils and the first coil are not coupled to each other via a conductor, but are magnetically coupled to each other.

Abstract: A method includes depositing a first hard mask layer on a first substrate; lithographically patterning and etching the first substrate to form a semiconductor link connected to an anode semiconductor region and a cathode semiconductor region; removing the first hard mask layer from the first substrate; depositing a second hard mask layer on the first substrate; patterning a photoresist on the first substrate and etching to form an opening in the semiconductor link; etching to remove portions of the second hard mask layer to expose a portion of a sidewall of the semiconductor link; removing the photoresist from the first substrate and the semiconductor link; and recessing the sidewalls of the semiconductor link forming first anti-fuse tip and second anti-fuse tip to form an anti-fuse with an opening between the first and second anti-fuse tips.

Abstract: A method includes depositing a first hard mask layer on a first substrate; lithographically patterning and etching the first substrate to form a semiconductor link connected to an anode semiconductor region and a cathode semiconductor region; removing the first hard mask layer from the first substrate; depositing a second hard mask layer on the first substrate; patterning a photoresist on the first substrate and etching to form an opening in the semiconductor link; etching to remove portions of the second hard mask layer to expose a portion of a sidewall of the semiconductor link; removing the photoresist from the first substrate and the semiconductor link; and recessing the sidewalls of the semiconductor link forming first anti-fuse tip and second anti-fuse tip to form an anti-fuse with an opening between the first and second anti-fuse tips.

Abstract: An interconnect and a method of forming an interconnect for a semiconductor device is provided. Conductive lines having different widths are formed. Wider conductive lines are used where the design includes an overlying via, and narrower lines are used in which an overlying via is not included. An overlying dielectric layer is formed and trenches and vias are formed extending through the overlying dielectric layer to the wider conductive lines. Voids or air gaps may be formed adjacent select conductive lines, such as the narrower lines.

Abstract: Structures and processes include a single metallization step for forming a metal nitride liner layer suitable for contact formation. The structure and processes generally includes forming a nitrogen-enriched surface in a deposited metal liner layer or forming a nitrogen-enriched surface in the dielectric material prior to deposition of the metal liner layer. In this manner, nitridization of the metal occurs upon deposition of nitrogen ions into the metal liner layer and/or as a function of additional conventional processing in fabricating the integrated circuit such that the deposited nitrogen ions diffuse into at least a portion of the metal liner layer. As a consequence, only a single metal layer deposition step is needed to form the metal liner layer.

Abstract: An interposer structure and a method of interconnecting first and second semiconductor dies are provided. A splice interposer is attached to a top surface of a substrate through a first plurality of pillars formed on a bottom surface of the splice interposer. The first semiconductor die is attached to the top surface of a substrate through a second plurality of pillars formed on a bottom surface of the first semiconductor die. The first semiconductor die is attached to a top surface of the splice interposer through a third plurality of pillars formed on the bottom surface of the first semiconductor. The height of the second plurality of pillars is greater than the height of the third plurality of pillars. The second semiconductor die is attached to the top surface of the splice interposer through a fourth plurality of pillars formed on a bottom surface of the second semiconductor die.

Abstract: A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.

Abstract: Embodiments of the present disclosure describe a selective diffusion barrier between metals of an integrated circuit (IC) device and associated techniques and configurations. In one embodiment, an apparatus includes a dielectric material, a first interconnect structure comprising a first metal disposed in the dielectric material, a second interconnect structure comprising a second metal disposed in the dielectric material and electrically coupled with the first interconnect structure and a diffusion barrier disposed at an interface between the first interconnect structure and the second interconnect structure, wherein the first metal and the second metal have a different chemical composition, material of the diffusion barrier and the second metal have a different chemical composition and material of the diffusion barrier is not disposed directly between the second metal and the dielectric material. Other embodiments may be described and/or claimed.