Abstract: In some embodiments, a semiconductor device includes a transistor, an isolation component, and a conductive layer. The transistor includes a source region and a drain region. The isolation component surrounds the source region. The conductive layer is configured for interconnection of the drain region. The conductive component is between the conductive layer and the isolation component, configured to shield the isolation component from an electric field over the isolation component.

Abstract: A high voltage device includes a substrate, a first LDMOS transistor and a second LDMOS transistor disposed on the substrate. The first LDMOS transistor includes a first gate electrode disposed on the substrate. A first STI is embedded in the substrate and disposed at an edge of the first gate electrode and two first doping regions respectively disposed at one side of the first STI and one side of the first gate electrode. The second LDMOS transistor includes a second gate electrode disposed on the substrate. A second STI is embedded in the substrate and disposed at an edge of the second gate electrode. Two second doping regions are respectively disposed at one side of the second STI and one side of the second gate electrode, wherein the second STI is deeper than the first STI.

Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate to isolate the device, a drain region disposed in the semiconductor substrate and to which a voltage is applied during operation, and a depleted well region disposed in the semiconductor substrate, and having a conductivity type in common with the doped isolation barrier and the drain region. The depleted well region is positioned between the doped isolation barrier and the drain region to electrically couple the doped isolation barrier and the drain region such that the doped isolation barrier is biased at a voltage level lower than the voltage applied to the drain region.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a top surface. The semiconductor device structure includes a first pillar structure over the substrate. The first pillar structure includes a first heavily n-doped layer, a first p-doped layer, an n-doped layer, and a first heavily p-doped layer, which are sequentially stacked together. The first pillar structure extends in a direction away from the substrate.

Abstract: A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.

Abstract: A p-type semiconductor Fin FET device includes a fin structure disposed over a substrate. The fin structure includes a channel layer. The Fin FET device also includes a gate structure including a gate electrode layer and a gate dielectric layer, covering a portion of the fin structure. Side-wall insulating layers are disposed over both main sides of the gate electrode layer. The Fin FET device includes a source and a drain, each including a stressor layer disposed in a recess formed by removing the fin structure not covered by the gate structure. The stressor layer includes a first stressor layer and a second stressor layer formed in this order. In the source, an interface between the first stressor layer and the channel layer is located under one of the side-wall insulating layers closer to the source or the gate electrode.

Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device structure includes forming a spacer layer material over a substrate and over gate structures defined in a first polarity type region and a second polarity type region; selectively etching the spacer layer material in the first polarity type region to form first gate sidewall spacers; forming first epitaxially grown source/drain (SD) regions in the first polarity type region; selectively forming a protection layer only on exposed surfaces of the first SD regions, so as not to increase a thickness of the spacer layer material in the second polarity type region; forming a masking layer over the first polarity type region, and etching the spacer layer material in the second polarity type region to form second gate sidewall spacers; and removing the masking layer and forming second epitaxially grown SD regions in the second polarity type region.

Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

Abstract: A semiconductor device includes a fin structure for a fin field effect transistor (FET). The fin structure includes a base layer protruding from a substrate, an intermediate layer disposed over the base layer and an upper layer disposed over the intermediate layer. The fin structure further includes a first protective layer and a second protective layer made of a different material than the first protective layer. The intermediate layer includes a first semiconductor layer disposed over the base layer, the first protective layer covers at least side walls of the first semiconductor layer and the second protective layer covers at least side walls of the first protective layer.

Abstract: A method of forming high germanium content silicon germanium alloy fins with controlled insulator layer recessing is provided. A silicon germanium alloy (SiGe) layer having a first germanium content is provided on a surface of an insulator layer using a first condensation process. Following the formation of a hard mask layer portion on the SiGe layer, a second condensation process is performed to convert a portion of the SiGe layer into a SiGe fin of a second germanium content that is greater than the first germanium content and other portions of the SiGe layer into a shell oxide structure located on sidewalls of the SiGe fin. After forming a fin placeholder material, a portion of each shell oxide structure is removed, while maintaining a lower portion of each shell oxide structure at the footprint of the SiGe fin.

Abstract: Device structures for a fin-type field-effect transistor (FinFET) and methods for fabricating a device structure for a FinFET. A fin comprised of a semiconductor material having a first crystal structure is formed. A dielectric layer is formed that includes an opening aligned with the fin. A dummy gate structure is removed from the opening in the dielectric layer. After the dummy gate structure is removed, a section of the fin aligned with the opening is implanted with non-dopant ions to amorphize the first crystal structure of the semiconductor material of the fin. After the section of the fin is implanted, the section of the fin is annealed such that the semiconductor material in the section of the fin recrystallizes with a second crystal structure incorporating internal strain.

Abstract: A method for forming fin field effect transistors includes epitaxially growing source and drain (S/D) regions on fins, the S/D regions including a diamond-shaped cross section and forming a dielectric liner over the S/D regions. A dielectric fill is etched over the S/D regions to expose a top portion of the diamond-shaped cross section. The fins are recessed into the diamond-shaped cross section. A top portion of the diamond-shaped cross section of the S/D regions is exposed. A contact liner is formed on the top portion of the diamond-shaped cross section of the S/D regions and in a recess where the fins were recessed. Contacts are formed over surfaces of the top portion and in the recess.

Abstract: A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.

Abstract: A semiconductor device is provided, including a substrate with an isolation layer formed thereon, wherein the substrate has a fin protruding up through the isolation layer to form a top surface and a pair of lateral sidewalls of the fin above the isolation layer; a silicon-germanium (SiGe) layer epitaxially grown on the top surface and the lateral sidewalls of the fin; and a gate stack formed on the isolation layer and across the fin, wherein the fin and the gate stack respectively extend along a first direction and a second direction. The SiGe layer formed on the top surface has a first thickness, the SiGe layer formed on said lateral sidewall has a second thickness, and a ratio of the first thickness to the second thickness is in a range of 1:10 to 1:30.

Abstract: A method of manufacturing a dual-gate FinFET is provided. The method includes: forming a fin structure on the semiconductor substrate, depositing an oxide layer and planarizing until the top of the fin structure is exposed, depositing a hard mask layer and patterning, preforming a first etch back process to one side of the oxide layer, and then removing the rest of the hard mask layer, preforming a second etch back process to the oxide layers at both sides of the fin structure simultaneously, forming a gate dielectric layer on surface of the fin structure, then depositing gate material on the gate dielectric layer and patterning, removing gate material on top of the fin structure, forming a drive gate and a control gate at two sides of the fin structure respectively; wherein height of the control gate is higher than height of the drive gate.

Abstract: To provide a semiconductor device that includes an oxide semiconductor and is miniaturized while keeping good electrical properties. In the semiconductor device, an oxide semiconductor layer filling a groove is surrounded by insulating layers including an aluminum oxide film containing excess oxygen. Excess oxygen contained in the aluminum oxide film is supplied to the oxide semiconductor layer, in which a channel is formed, by heat treatment in a manufacturing process of the semiconductor device. Moreover, the aluminum oxide film forms a barrier against oxygen and hydrogen, which inhibits the removal of oxygen from the oxide semiconductor layer surrounded by the insulating layers including an aluminum oxide film and the entry of impurities such as hydrogen in the oxide semiconductor layer. Thus, a highly purified intrinsic oxide semiconductor layer can be obtained. The threshold voltage is controlled effectively by gate electrode layers formed over and under the oxide semiconductor layer.

Abstract: The present invention proposes a TFT switch and a method for manufacturing the same. The TFT switch includes a gate, a drain, a source, a semiconductor layer and a fourth electrode. The drain is connected to a first signal, the gate is connected to a control signal to control the switch on or off. The source outputs the first signal when the switch turns on. The fourth electrode and the gate are respectively located at two sides of the semiconductor layer. The fourth electrode is conductive and is selectively coupled to different voltage levels, thereby reducing leakage current in a channel to improve switch characteristic when the switch turns off.

Abstract: A semiconductor device that can operate at high speed or having high strength against stress is provided. One embodiment of the present invention is a semiconductor device including a semiconductor film including a channel formation region and a pair of impurity regions between which the channel formation region is positioned; a gate electrode overlapping side and top portions of the channel formation region with an insulating film positioned between the gate electrode and the side and top portions; and a source electrode and a drain electrode in contact with side and top portions of the pair of impurity regions.

Abstract: A nickelide material with reduced resistivity is provided as source/drain contact surfaces in both NMOS and PMOS technology. The nickelide material layer may be a ternary material such as NiInAs, and may be formed from a binary material previously formed in the source/drain regions. The binary material may be the channel material or it may be an epitaxial layer formed over the channel material. The same ternary nickelide material may be used as the source/drain contact surface in both NMOS and PMOS transistors. Various binary or ternary channel materials may be used for the NMOS transistors and for the PMOS transistors.

Abstract: The concentration of impurity elements included in an oxide semiconductor film in the vicinity of a gate insulating film is reduced. Further, crystallinity of the oxide semiconductor film in the vicinity of the gate insulating film is improved. A semiconductor device includes an oxide semiconductor film over a substrate, a source electrode and a drain electrode over the oxide semiconductor film, a gate insulating film which includes an oxide containing silicon and is formed over the oxide semiconductor film, and a gate electrode over the gate insulating film. The oxide semiconductor film includes a region in which the concentration of silicon is lower than or equal to 1.0 at. %, and at least the region includes a crystal portion.

Abstract: A semiconductor memory device includes a bit line; two or more word lines; and a memory cell including two or more sub memory cells that each include a transistor and a capacitor. One of a source and a drain of the transistor is connected to the bit line, the other of the source and the drain of the transistor is connected to the capacitor, a gate of the transistor is connected to one of the word lines, and each of the sub memory cells has a different capacitance of the capacitor.

Abstract: An enhancement-mode n-type field effect transistor is disclosed to have a metal oxide channel layer, a gate dielectric layer, a gate electrode, a source electrode, and a drain electrode. The metal oxide channel layer has a material selected from SnO2, ITO, ZnO, SnO2 and In2O3. The metal oxide channel layer has a thickness less than a threshold value to exhibit pinch-off behavior in transfer characteristics and has a mobility trend without saturation under positive operational voltage.

Abstract: Provided is an in-wiring-layer active element (component) which allows for electrical isolation between a gate electrode and a channel in a top gate structure. A semiconductor device includes a first wiring layer, a second wiring layer, and a semiconductor element. The first wiring layer has a first interlayer insulating layer, and a first wire embedded in the first interlayer insulating layer. The second wiring layer has a second interlayer insulating layer, and second wires embedded in the second interlayer insulating layer. The semiconductor element is provided at least in the second wiring layer. The semiconductor element includes a semiconductor layer provided in the second wiring layer, a gate insulating film provided in contact with the semiconductor layer, a gate electrode provided on the opposite side of the semiconductor layer via the first gate insulating film, and a first side wall film provided over a side surface of the semiconductor layer.

Abstract: In a cross section in a channel width direction, a semiconductor layer includes a first region of which one end portion is in contact with an insulating layer and which is positioned at one side portion of the semiconductor layer; a second region of which one end portion is in contact with the other end portion of the first region and which is positioned at an upper portion of the semiconductor layer; and a third region of which one end portion is in contact with the other end portion of the second region and the other end portion is in contact with the insulating layer and which is positioned at the other side portion of the semiconductor layer. In the second region, an interface with a gate insulating film is convex and has three regions respectively having curvature radii R1, R2, and R3 that are connected in this order from the one end portion side toward the other. R2 is larger than R1 and R3.

Abstract: A semiconductor device and a manufacturing method thereof is disclosed in which the semiconductor device includes a p-type anode layer formed by a transition metal acceptor transition, and the manufacturing process is significantly simplified without the breakdown voltage characteristics deteriorating. An inversion advancement region inverted to a p-type by a transition metal acceptor transition, and in which the acceptor transition is advanced by point defect layers, is formed on the upper surface of an n-type drift layer. The inversion advancement region configures a p-type anode layer of a semiconductor device of the invention. The transition metal is, for example, platinum or gold. An n-type semiconductor substrate with a concentration higher than that of the n-type drift layer is adjacent to the lower surface of the n-type drift layer.

Abstract: A simplified manufacturing process stably produces a semiconductor device with high electrical characteristics, wherein platinum acts as an acceptor. Plasma treatment damages the surface of an oxide film formed on a n? type drift layer deposited on an n+ type semiconductor substrate. The oxide film is patterned to have tapered ends. Two proton irradiations are carried out on the n? type drift layer with the oxide film as a mask to form a point defect region in the vicinity of the surface of the n? type drift layer. Silica paste containing 1% by weight platinum is applied to an exposed region of the n? type drift layer surface not covered with the oxide film. Heat treatment inverts the vicinity of the surface of the n? type drift layer to p-type by platinum atoms which are acceptors. A p-type inversion enhancement region forms a p-type anode region.

Abstract: Photovoltaic cells, methods for fabricating surface mount multijunction photovoltaic cells, methods for assembling solar panels, and solar panels comprising photovoltaic cells are disclosed. The surface mount multijunction photovoltaic cells include through-wafer-vias for interconnecting the front surface epitaxial layer to a contact pad on the back surface. The through-wafer-vias are formed using a wet etch process that removes semiconductor materials non-selectively without major differences in etch rates between heteroepitaxial III-V semiconductor layers.

Abstract: A method of reducing bow and/or improving the electrical performance of an aluminum back contacted silicon solar cell includes applying to a silicon wafer substrate a paste including aluminum and an organometallic compound, and firing the substrate. The organometallic compound is a C1 to C30 organometallic compound of a metal selected from the group consisting of Ag, Al, Ba, Bi, Ca, Co, Cr, Cu, Fe, K, Li, Mg, Mn, Mo, Na, Nd, Ni, Sb, Si, Sn, Sr, Ta, V, Zn, Zr. A paste is formed having an exothermic reaction peak at a temperature of at least 300° C. to less than 660° C.

Abstract: A solar cell of the present invention includes a collecting electrode on one main surface of a photoelectric conversion section. The collecting electrode includes first and second electroconductive layers in this order from the photoelectric conversion section side, and an insulating layer between the first and second electroconductive layers, the insulating layer having an opening section formed therein. The first electroconductive layer is covered with the insulating layer, contains a low-melting-point material, and is conductively connected with a part of the second electroconductive layer via the opening section. The surface roughness of the second electroconductive layer is preferably 1.0 ?m to 10.0 ?m. The second electroconductive layer is preferably formed by a plating method. In order to conductively connect the first and second electroconductive layers, annealing of the first electroconductive layer by heating is preferably performed prior to forming the second electroconductive layer.

Abstract: A photodetector is provided with a thin film double layer heterostructure. The photodetector is comprised of: a substrate; a channel layer of a transistor deposited onto a top surface of the substrate; a source layer of the transistor deposited on the top surface of the substrate; a drain layer of the transistor deposited on the top surface of the substrate, the source layer and the drain layer disposed on opposing sides of the channel layer; a barrier layer deposited onto the channel layer; and a light absorbing layer deposited on the barrier layer. The light absorbing layer is configured to absorb light and, in response to light incident on the light absorbing layer, electrical conductance of the channel layer is changed through hot carrier tunneling from the light absorbing layer to the channel layer.

Abstract: A resonant tunneling diode, and other one dimensional electronic, photonic structures, and electromechanical MEMS devices, are formed as a heterostructure in a nanowhisker by forming length segments of the whisker with different materials having different band gaps.

Abstract: A semiconductor device and the like having high quantum efficiency or high sensitivity in a near-infrared to infrared region is provided. The semiconductor device includes: a substrate; a multiple quantum well structure disposed on the substrate, and including a plurality of pairs of a layer a and a layer b; and a crystal-adjusting layer disposed between the substrate and the multiple quantum well structure. The crystal-adjusting layer includes a first adjusting layer which is made of the same material as the substrate and is in contact with the substrate, and a second adjusting layer which is made of the same material as the layer a or the layer b of the multiple quantum well structure and is in contact with the multiple quantum well structure.

Abstract: A three-dimensional thin-film semiconductor substrate with selective through-holes is provided. The substrate having an inverted pyramidal structure comprising selectively formed through-holes positioned between the front and back lateral surface planes of the semiconductor substrate to form a partially transparent three-dimensional thin-film semiconductor substrate.

Abstract: The present invention concerns a plating method for manufacturing of electrical contacts on a solar module wherein the wiring between silicon solar cells in a solar module is deposited by electroplating onto a conductive seed. The wiring between individual silicon solar cells comprises wiring reinforcement pillars which improve the reliability of said wiring.

Abstract: The invention relates to a photovoltaic concentrator module comprising at least one lens and at least one photovoltaic cell, further comprising a distance adjustment means configured to adjust the distance between the at least one lens and the at least one photovoltaic cell. Using the distance adjustment means, the cell and the lens can be kept at a desired distance, e.g., the focal distance. The distance adjustment means can be a pressure varying means. The invention further relates to a photovoltaic concentrator array comprising a plurality of photovoltaic concentrator modules and to a method for improving the energy conversion efficiency of a photovoltaic concentrator module.

Abstract: An energy conversion device comprises at least two thin film photovoltaic cells fabricated separately and joined by wafer bonding. The cells are arranged in a hierarchical stack of decreasing order of their energy bandgap from top to bottom. Each of the thin film cells has a thickness in the range from about 0.5 ?m to about 10 ?m. The photovoltaic cell stack is mounted upon a thick substrate composed of a material selected from silicon, glass, quartz, silica, alumina, ceramic, metal, graphite, and plastic. Each of the interfaces between the cells comprises a structure selected from a tunnel junction, a heterojunction, a transparent conducting oxide, and an alloying metal grid; and the top surface and/or the lower surface of the energy conversion device may contain light-trapping means.

Abstract: Photovoltaic devices including direct gap III-V absorber materials and operatively associated back structures enhance efficiency by enabling photon recycling. The back structures of the photovoltaic devices include wide bandgap III-V layers, highly doped (In)GaAs layers, patterned oxide layers and metal reflectors that directly contact the highly doped (In)GaAs layers through vias formed in the back structures. Localized ohmic contacts are formed in the back structures of the devices.

Abstract: A sensing device able to do concurrent real time detection of different kinds of chemical, biomolecule agents, or biological cells and their respective concentrations using optical principles. The sensing system can be produced at a low cost (below $1.00) and in a small size (˜1 cm3). The novel sensing system may be of great value to many industries, for example, medical, forensics, and military. The fundamental principles of this novel invention may be implemented in many variations and combinations of techniques.

Abstract: One embodiment of the present invention relates to a method of manufacturing polycrystalline silicon thin-film solar cell by a method of crystallizing a large-area amorphous silicon thin film using a linear electron beam, and the technical problem to be solved is to crystallize an amorphous silicon thin film, which is formed on a low-priced substrate, by means of an electron beam so as for same to easily be of high quality by having high crystallization yield and to be processed at a low temperature.

Abstract: A method for producing a radiation-emitting semiconductor component is provided, comprising the following steps: —providing a growth substrate (1), —depositing a nucleation layer (2) on the growth substrate (1), —applying a structured dielectric layer (3) to the nucleation layer (2), —applying an epitaxial layer (4) by means of a FACELO process to the structured dielectric layer (3), —epitaxial growth of an epitaxial layer sequence (5) on the epitaxial layer (4), wherein the epitaxial layer sequence (5) comprises an active zone (6) that is suitable for producing electromagnetic radiation.

Abstract: In at least one embodiment, a method is designed to produce optoelectronic semiconductor chips. A carrier assembly, which is a sapphire wafer, is produced. A semiconductor layer sequence is applied to the carrier assembly. The carrier assembly and the semiconductor layer sequence are divided into the individual semiconductor chips. The dividing is implemented by producing a multiplicity of selectively etchable material modifications in the carrier assembly in separation region(s) by focused, pulsed laser radiation. The laser radiation has a wavelength at which the carrier assembly is transparent. The dividing includes wet chemically etching the material modifications, such that the carrier assembly is singulated into individual carriers for the semiconductor chips solely by the wet chemical etching or in combination with a further material removal method.

Abstract: There is provided a semiconductor light emitting device including a conductive substrate, a first electrode layer, an insulating layer, a second electrode layer, a second semiconductor layer, an active layer, and a first semiconductor layer that are sequentially stacked. The contact area between the first electrode layer and the first semiconductor layer is 3% to 13% of the total area of the semiconductor light emitting device, and thus high luminous efficiency is achieved.

Abstract: A light emitting diode including a substrate, a p-type and n-type semiconductor layers, an active layer, an interlayer, an electron barrier layer, a first and a second electrodes are provided. The n-type semiconductor layer is disposed on the sapphire substrate. The active layer has an active region with a defect density greater than or equal to 2×107/cm2. The active layer is disposed between the n-type and p-type semiconductor layers. The wavelength of light emitted by the active layer is ?, and 222 nm???405 nm. The active layer includes i quantum barrier layers and (i?1) quantum wells, each quantum well is disposed between any two quantum barrier layers, and i?2. N-type dopant is doped in at least k layers of the i quantum barrier layers, wherein k is a natural number and k?1, when i even, k?i/2, and when i is odd, k?(i?1)/2.

Abstract: An optoelectronic component includes a semiconductor layer structure having a quantum film structure, and a p-doped layer arranged above the quantum film structure, wherein the p-doped layer includes at least one first partial layer and a second partial layer, and the second partial layer has a higher degree of doping than the first partial layer.

Abstract: A nitride semiconductor device includes a transistor having a semiconductor stacked body formed on a substrate, and a pn light-emitting body formed on the semiconductor stacked body. The semiconductor stacked body includes a first nitride semiconductor layer, and a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a bandgap wider than that of the first nitride semiconductor layer. The transistor includes: the semiconductor stacked body; a source electrode and a drain electrode formed away from each other on the semiconductor stacked body; and a gate electrode provided between the source electrode and the drain electrode and formed away from the source electrode and the drain electrode.

Abstract: A component including a substrate, at least one layer including a color conversion material including quantum dots disposed over the substrate, and a layer including a conductive material (e.g., indium-tin-oxide) disposed over the at least one layer. (Embodiments of such component are also referred to herein as a QD light-enhancement substrate (QD-LES).) In certain preferred embodiments, the substrate is transparent to light, for example, visible light, ultraviolet light, and/or infrared radiation. In certain embodiments, the substrate is flexible. In certain embodiments, the substrate includes an outcoupling element (e.g., a microlens array). A film including a color conversion material including quantum dots and a conductive material is also provided. In certain embodiments, a component includes a film described herein. Lighting devices are also provided. In certain embodiments, a lighting device includes a film described herein.

Abstract: A hetero-substrate, a nitride-based semiconductor light emitting device, and a method of manufacturing the same are provided. The hetero-substrate may include a substrate including a silicon semiconductor, a buffer layer disposed on the substrate, a first semiconductor layer disposed on the buffer layer and including a nitride semiconductor, a second semiconductor layer disposed on the first semiconductor layer and including a first conductive type nitride semiconductor having a first doping concentration, and a stress control structure disposed between the first semiconductor layer and the second semiconductor layer and including at least one stress compensation layer and at least one third semiconductor layer including a first conductive type nitride semiconductor having a second doping concentration that is the same or lower than the first doping concentration.

Abstract: A heteroepitaxy strain-management structure for a light emitting device includes: a substrate or template; an epitaxial layer to be epitaxially formed over the substrate or template, wherein a calculated in-plane compressive strain to be exerted by the substrate or template to the epitaxial layer is equal to or larger than 1%; and a heavily doped interlayer inserted in-between the epitaxial layer and the substrate or template; wherein the heavily doped interlayer is of substantially the same material composition as that of the epitaxial layer, with a thickness of 40-400 nm, and doped at a doping level in the range of 5×1019 to 5×1020 cm?3. Also provided is an ultraviolet light emitting device having a heteroepitaxy strain-management structure.

Abstract: In various embodiments, light-emitting devices incorporate graded layers with compositional offsets at one or both end points of the graded layer to promote formation of two-dimensional carrier gases and polarization doping, thereby enhancing device performance.

Abstract: A group-III nitride structure includes a substrate 102 and a fine wall-shaped structure 110 disposed to stand on the substrate 102 in a vertical direction relative to a surface of the substrate 102 and extending in an in-plane direction of the substrate 102. The fine wall-shaped structure 110 contains a group-III nitride semiconductor crystal, and h is larger than d assuming that the height of the fine wall-shaped structure 110 is h and the width of the fine wall-shaped structure 110 in a direction perpendicular to the height direction and the extending direction is d.