Abstract: A method for forming a split-gate flash memory cell, and the resulting integrated circuit, are provided. A semiconductor substrate having memory cell and capacitor regions are provided. The capacitor region includes one or more sacrificial shallow trench isolation (STI) regions. A first etch is performed into the one or more sacrificial STI regions to remove the one or more sacrificial STI regions and to expose one or more trenches corresponding to the one or more sacrificial STI regions. Dopants are implanted into regions of the semiconductor substrate lining the one or more trenches. A conductive layer is formed filling the one or more trenches. A second etch is performed into the conductive layer to form one of a control gate and a select gate of a memory cell over the memory cell region, and to form an upper electrode of a finger trench capacitor over the capacitor region.

Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a first stacked body; a semiconductor film; a charge storage film; and a second stacked body. The first stacked body includes: a plurality of first insulating layers; and a plurality of electrode layers. The second stacked body includes: a plurality of second insulating layers; a first insulating film provided between the plurality of second insulating layers and including a material different from that of the plurality of first insulating layers, the plurality of second insulating layers, and the plurality of electrode layers; and a second insulating film provided between the first insulating film and the substrate via the plurality of second insulating layers, including a same material as the first insulating film, and having lower film density than the first insulating film.

Abstract: A semiconductor memory device according to an embodiment includes a memory cell array which has: a first conductive layer which is arranged in a first direction on a first semiconductor layer; a second conductive layer which is arranged in the first direction above the first conductive layer; a columnar second semiconductor layer which extends in the first direction; and a contact unit which electrically connects the first semiconductor layer and the second conductive layer. The contact unit has a first film which contains silicide as a first metal, and is in contact with the first semiconductor layer; and a second film which contains the first metal, is in contact with the first film, and is in contact with the first semiconductor layer with the first film interposed therebetween.

Abstract: According to one embodiment, a semiconductor device includes: a substrate; a stacked body; a columnar portion; and a plate portion. The substrate has a major surface. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The columnar portion includes a semiconductor body and a memory film. The memory film includes a charge storage portion. The plate portion is provided in the stacked body. The plate portion extends along the stacking direction of the stacked body and a major surface direction of the substrate. The plate portion includes a plate conductor and a sidewall insulating film. The sidewall insulating film provided between the plate conductor and the stacked body. The stacked body includes an air gap. The air gap is provided between the sidewall insulating film and the electrode layer.

Abstract: A memory structure includes a 3D array of memory cells, a plurality of first conductive lines disposed on the 3D array, a plurality of second conductive lines disposed on the first conductive lines, a top metal plate disposed on the second conductive lines, and at least one strapping structure. The second conductive lines and the first conductive lines extend on different directions. The at least one strapping structure is configured for the first conductive lines and correspondingly disposed on at least one dummy region of the 3D array. Each strapping structure includes a connecting structure and a jumping line. The jumping line is disposed on and coupled to the connecting structure, and coupled to the top metal plate. The jumping line and the second conductive lines extend on the same direction.

Abstract: A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array.

Abstract: An integrated circuit comprises standard cells arranged in rows and columns. The integrated circuit also comprises tap cells arranged in rows and columns. The tap cells each comprise a substrate having a first dopant type and a thickness from a first surface of the substrate to a second surface of the substrate. The integrated circuit further comprises a well region in the substrate having a second dopant type different from the first dopant type and a depth from the first surface of the substrate less than the thickness of the substrate. The integrated circuit additionally comprises a first quantity of rows of tap cells and a second quantity of rows of tap cells less than the first quantity. Each row of the first quantity of rows of tap cells comprises at least one well contact, and each row of tap cells of the second quantity of tap cells comprises at least one substrate contact.

Abstract: Provided is a semiconductor integrated circuit including: a plurality of first input/output cells arranged on a semiconductor integrated circuit substrate; a plurality of second input/output cells arranged on the semiconductor integrated circuit substrate along the plurality of first input/output cells; and a potential supply portion formed on a semiconductor package substrate, a portion of the potential supply portion protruding in a surface of the semiconductor package substrate, and configured to supply a predetermined potential to a target cell which is one of the plurality of first input/output cells and a cell neighboring the target cell among the plurality of second input/output cells through a region including the protruding portion.

Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are provided. The method includes forming deep trench capacitor structures in a silicon on insulator (SOI) wafer. The method further includes forming a plurality of composite fin structures from a semiconductor material of the SOI wafer and conductive material of the deep trench capacitor structures. The method further includes forming a liner over the deep trench capacitor structures including the conductive material of the deep trench capacitor structures. The method further includes forming replacement gate structures with the liner over the deep trench capacitor structures protecting the conductive material during deposition and etching processes.

Abstract: An object of the present invention is to apply an insulating film of cure and high quality that is suitably applicable as gate insulating film and protective film to a technique that the insulating film is formed on the glass substrate under a temperature of strain point or lower, and to a semiconductor device realizing high efficiency and high reliability by using it. In a semiconductor device of the present invention, a gate insulating film of a field effect type transistor with channel length of from 0.35 to 2.5 ?m in which a silicon nitride film is formed over a crystalline semiconductor film through a silicon oxide film, wherein the silicon nitride film contains hydrogen with the concentration of 1×1021/cm3 or less and has characteristic of an etching rate of 10 nm/min or less with respect to mixed solution containing an ammonium hydrogen fluoride (NH4HF2) of 7.13% and an ammonium fluoride (NH4F) of 15.4%.

Abstract: A display device includes a first substrate having an active area, a circuit area extending outwardly from the active area, and a cell seal area extending outwardly from the circuit area, a second substrate covering the first substrate, a sealing part between the first substrate and the second substrate, the sealing part covering at least a portion of the circuit area, a wiring part in the circuit area of the first substrate and electrically connected to elements in the active area of the first substrate, the wiring part including at least one level-difference compensation part, and a stepped part between the sealing part and at least a portion of the wiring part, the at least one level-difference compensation part of the wiring part being adjacent to the stepped part.

Abstract: A liquid crystal display includes a first substrate, a gate line and a data line disposed on the first substrate, a first insulating layer disposed on the gate line and the data line, a first electrode disposed on the first insulating layer and having a flat form in a planar shape, a second insulating layer disposed on the first electrode, and a second electrode disposed on the second insulating layer and including a plurality of branch electrodes, where a width of a branch electrode of the plurality of branch electrodes is equal to or less than about 2 micrometers.

Abstract: Disclosed are a display substrate, of which productivity is improved by decreasing five mask (M) processes utilized for fabricating the display substrate used in a liquid crystal display device in a horizontal field (Plane to Line Switching (PLS)) mode to four mask processes, and a method of fabricating the same.

Abstract: A display device includes a substrate, a first insulating layer having a first side wall, an oxide semiconductor layer on the first side wall, a gate electrode facing the oxide semiconductor layer, a gate insulating layer between the oxide semiconductor layer and the gate electrode, a first transparent conductive layer between the oxide semiconductor layer and the substrate, the first transparent conductive layer being connected with a first portion of the oxide semiconductor layer, a first electrode on the first insulating layer on the side opposite to the substrate, the first electrode being connected with a second portion of the oxide semiconductor layer, and a second transparent conductive layer connected with the first transparent conductive layer, the second transparent conductive layer forming the same layer with the first transparent conductive layer.

Abstract: An array substrate includes a base substrate, a gate electrode, a gate insulating layer and an active layer arranged on the base substrate in a laminated way. The array substrate further includes a passivation layer, a source electrode, a drain electrode, a first electrode and a second electrode. A first via hole arranged in the passivation layer may include two sloped lateral faces arranged opposite to each other. The first electrode may at least partially cover one lateral face of the first via hole. The second electrode electrically connected to a common electrode lead may at least partially cover the other lateral face of the first via hole. The source electrode and the drain electrode may be connected to the active layer through a second via hole which is arranged in the passivation layer. The first electrode is electrically connected to the source electrode or the drain electrode.

Abstract: An array substrate and manufacturing method thereof, a display device are provided. The array substrate includes a display region and a non-display region; the non-display region includes a first laminated structure and a second laminated structure that are separately disposed on a base substrate, a gap between the first laminated structure and the second laminated structure constitutes a connecting hole; the first laminated structure includes a first via hole provided for exposing a first metal layer, the second laminated structure includes a second via hole provided for exposing a second metal layer, the first via hole and the second via hole are connected to a connecting hole via breaches on corresponding walls, and the first metal layer and the second metal are electrically connected with a conductive film.

Abstract: An active matrix substrate (10) includes a first line (101), a second line (102), a third line (103), a fourth line (104) and a fifth line (105) provided in a non-display region F. The first line crosses a non-input-side end portion of at least one bus line of a first bus line group with an insulating layer interposed therebetween. The second line crosses a non-input-side end portion of at least one bus line of a second bus line group with an insulating layer interposed therebetween. The third line crosses an input-side end portion of the first bus line group with an insulating layer interposed therebetween, and does not cross the second bus line group. The fourth line crosses an input-side end portion of the second bus line group with an insulating layer interposed therebetween, and does not cross the first bus line group. The fifth line is routed so as to cross the first, second, third and fourth lines with an insulating layer interposed therebetween.

Abstract: A method of manufacturing a pixel structure includes: forming a source, a drain and a first capacitor electrode; forming a semiconductor layer in contact with a portion of the source and a portion of the drain; forming a gate and a second capacitor electrode, and the second capacitor electrode substantially aligned with the first capacitor electrode; forming a gate insulating layer between the semiconductor layer, the source, the drain and the first capacitor electrode, and the gate and the second capacitor electrode; forming a passivation layer over the source, the drain, the first capacitor electrode, the semiconductor layer, the gate and the second capacitor electrode; and forming a pixel electrode over the passivation layer, and the pixel electrode substantially aligned with the first capacitor electrode.

Abstract: A liquid crystal display includes a first pixel and a second pixel that extend in a data line direction. The first and second pixels are connected to a same data line, and the first pixel is closer to a data driver than the second pixel. A channel width of a thin film transistor of the first pixel is less than a channel width of a thin film transistor of the second pixel.

Abstract: A solid-state imaging device includes a substrate and a photoelectric conversion region. The substrate has a charge accumulation region. The photoelectric conversion region is provided on the substrate. The photoelectric conversion region is configured to generate signal charges to be accumulated in the charge accumulation region. The photoelectric conversion region comprises a material that is not transparent.

Abstract: A binary image sensor includes a plurality of unit pixels on a substrate having a surface on which light is incident. At least one quantum dot is disposed on the surface of a substrate. A column sense amplifier circuit is configured to detect binary information of a selected unit pixel among the plurality of unit pixels from a voltage or a current detected from the selected unit pixel, and a processing unit is configured to process binary information of the respective unit pixels to generate pixel image information. Related devices and methods of operation are also discussed.

Abstract: An imaging apparatus includes: an interposer on which an image sensor including a light reception section is disposed; a translucent member that is provided on the light reception section; and a mold that is formed in sides of the interposer having a rectangular shape and bonded to the translucent member to support the translucent member, the mold including a seal surface that is bonded to the translucent member, the seal surface being provided with a protrusion.

Abstract: A curved image sensor system includes (a) an image sensor substrate having a concave light-receiving surface, a pixel array located along the concave light-receiving surface, and a planar external surface facing away from the concave light-receiving surface, (b) a light-transmitting substrate bonded to the image sensor substrate by a bonding layer, and (c) a hermetically sealed cavity, bounded at least by the concave light-receiving surface, the light-transmitting substrate, and the bonding layer.

Abstract: Provided is a solid-state imaging device including a lamination-type backside illumination CMOS (Complementary Metal Oxide Semiconductor) image sensor having a global shutter function. The solid-state imaging device includes a separation film including one of a light blocking film and a light absorbing film between a memory and a photo diode.

Abstract: An image sensor is provided. The image sensor includes a red (R) pixel, a green (G) pixel, a blue (B) pixel and an infrared (IR) pixel, and R, G and B filters respectively disposed at the R, G and B pixels. The image sensor also includes an IR pass filter disposed at the IR pixel and an IR filter stacked with the R, G and B filters, wherein the IR filter cuts off at least IR light with a specific wavelength. Furthermore, a method of forming an image sensor is also provided.

Abstract: A semiconductor device including a substrate, at least one sensor, a dielectric layer, at least one light pipe structure, at least one pad, a shielding layer, and a protection layer is provided. The sensor is located in the substrate of a first region. The dielectric layer is located on the substrate. The light pipe structure is located in the dielectric layer of the first region. The light pipe structure corresponds to the sensor. The pad is located in the dielectric layer of a second region. The shielding layer is located on the dielectric layer, wherein the light pipe structure is surrounded by the shielding layer. The protection layer is located on the shielding layer. At least one pad opening is disposed in the dielectric layer, the shielding layer, and the protection layer above the pad. The pad opening exposes a top surface of the corresponding pad.

Abstract: An image sensor may include a device isolation structure defining a plurality of pixel regions in a substrate and a photoelectric conversion element formed in each of the pixel regions. The device isolation structure may include an insulating gapfill layer extending from an upper portion to a lower portion of the device isolation structure, a spacer provided at the upper portion of the device isolation structure and interposed between the insulating gapfill layer and the substrate, and a lower impurity region provided at the lower portion of the device isolation structure and interposed between the insulating gapfill layer and the substrate.

Abstract: An imaging system may include an image sensor package with through-oxide via connections between the image sensor die and the digital signal processing die in the image sensor package. The image sensor die and the digital signal processing die may be attached to each other. The through-oxide via may connect a bond pad on the image sensor die with metal routing paths in the image sensor and digital signal processing dies. The through-oxide via may simultaneously couple the image sensor die to the digital signal processing die. The through-oxide via may be formed through a shallow trench isolation structure in the image sensor die. The through-oxide via may be formed through selective etching of the image sensor and digital signal processing dies.

Abstract: A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.

Abstract: A semiconductor device having a first semiconductor section including a first wiring layer at one side thereof; a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other; a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication; and an opening, other than the opening for the conductive material, which extends through the first semiconductor section to the second wiring layer.

Abstract: A backside illuminated (BSI) image sensor device includes a device layer, a doped isolation region and a doped radiation sensing region. The device layer has a front side and a backside, in which the device layer has a thickness greater than or equal to 4 ?m. The doped isolation region having a first dopant of a first conductivity is through the device layer to define a plurality of pixel regions of the device layer, in which the doped isolation region includes a first upper region adjacent to the front side and a first lower region between the first upper region and the backside, and the first upper region has a width less than a width of the first lower region. The doped radiation sensing region having a second dopant of a second conductivity opposite to the first conductivity is in one of the pixel regions of the device layer.

Abstract: A fractal-edge thin film includes a material layer having a perimeter with a fractal dimension exceeding one, the material layer having greater peel resistance as compared to a thin-film material layer with fractal dimension equaling one. A method of manufacturing a fractal-edge thin film includes determining an area shape to be covered by the fractal-edge thin film. The method also includes generating a thin-film perimeter based upon the area shape, the thin-film perimeter having a fractal dimension exceeding one. The method also includes determining a photomask perimeter such that a photomask with the photomask perimeter, when used in a photolithography process, yields a fractal-edge thin film with the thin-film perimeter. The method may also include photolithographically etching a thin-film, the thin film having a photoresist layer disposed thereon, the photoresist layer having been exposed through the photomask, wherein the etching results in the fractal-edge thin film.

Abstract: An image-sensor structure is provided. The image-sensor structure includes a substrate having a first surface and a second surface and including a sensing area, a first metal layer formed above the first surface of the substrate and surrounding the sensing area, and a protection layer formed above the first surface of the substrate and overlying the sensing area and a part of the first metal layer to expose an exposed area of the first metal layer. The exposed area includes a first portion having a first width, a second portion having a second width, a third portion having a third width and a fourth portion having a fourth width.

Abstract: A light emitting device includes: a ceramic substrate; a plurality of LED chips; a printed resistor(s) connected in parallel with the plurality of LED chips; a dam resin made of a resin having a low optical transmittance; a fluorescent-material-containing resin layer; and an anode-side electrode and a cathode-side electrode, (a) which are provided on a primary surface of the ceramic substrate so as to face each other along a first direction on the primary surface and (b) which are disposed below at least one of the dam resin and the fluorescent-material-containing resin layer. With the configuration in which a plurality of LEDs, which are connected in a series-parallel connection, are provided on a substrate, it is possible to provide a light emitting device which can achieve restraining of luminance unevenness and an improvement in luminous efficiency.

Abstract: A semiconductor device may include a first magnetic layer including a plurality of first regions configuring a plurality of memory cells and spaced apart from each other on a substrate, and a second region encompassing the plurality of first regions and electrically isolated from the first regions, a tunnel barrier layer disposed on the first magnetic layer, and a second magnetic layer disposed on the tunnel barrier layer.

Abstract: An electronic device is provided. An electronic device according to an example of the disclosed technology includes a semiconductor memory, the semiconductor memory including: a substrate including a recess formed in the substrate; a gate including at least a portion that is buried in the substrate; a junction formed at both sides of the gate in the substrate; and a memory element electrically connected to the junction at one side of the gate, wherein the junction includes: a barrier layer formed over the recess such that a thickness of the barrier layer formed over a bottom surface of the recess is different from that of the barrier layer formed over a side surface of the recess; a contact pad formed over the barrier layer so as to fill the recess; and an impurity region formed in the substrate and located under the contact pad.

Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer separated from the first conductive layer in a first direction, a resistance change layer provided between the first and second conductive layers, a third conductive layer, a fourth conductive layer and a first intermediate layer. The third conductive layer is arranged with the first conductive layer in a second direction crossing the first direction. The fourth conductive layer is arranged with the second conductive layer in a direction crossing the first direction. The fourth conductive layer is arranged with the third conductive layer in the first direction. The fourth conductive layer is electrically connected with the third conductive layer. The first intermediate layer is provided between a portion of the third conductive layer and a portion of the fourth conductive layer.

Abstract: The present invention is a means and a method for manufacturing large three dimensional memory arrays. The present invention is a means and a method for addressing the WL and BL resistance by creating arrays having not only large plane conductors for each of the memory layers (WLs) but also for the opposite polarity common layer (BL). The present invention is also a means and a method to form via interconnections between the substrate logic and the respective layers of a multidimensional array. The present invention is also a way to operate an array in which the select device is unipolar but the array is above to be operated in a bipolar way. This facilitates a bipolar operation for memory cell technologies such as Resistive RAM (e.g., RRAM, ReRAM and Memresistors).

Abstract: A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position.

Abstract: Image sensors include a color photo-sensing photoelectric conversion device, a first color filter and a second color filter disposed under the color photo-sensing photoelectric conversion device, a first photodiode and a second photodiode disposed under the first color filter and the second color filter, respectively, a first light guide member disposed between the first color filter and the first photodiode, and a second light guide member disposed between the second color filter and the second photodiode.

Abstract: An organic light emitting display device is disclosed. The organic light emitting display device includes a first sub-pixel that includes a first emission region which makes a first color, a second sub-pixel that is disposed adjacent to the first sub-pixel, and includes a second emission region which makes a second color, a third sub-pixel that is disposed adjacent to the first sub-pixel, and includes a third emission region which makes a third color, and a fourth sub-pixel that is disposed adjacent to the second sub-pixel and the third sub-pixel, and includes a fourth emission region which makes a fourth color. At least one of the first to fourth sub-pixels includes a transmission region which cannot emit light and through which external light is transmitted. The transmission region is surrounded by at least one of the first to fourth emission regions.

Abstract: An organic EL display device includes a lower electrode that is provided at each pixel, a bank that surrounds an outer circumference of the lower electrode and overlaps an outer circumferential edge of the lower electrode, an organic layer that is formed on the lower electrode and the bank, and an upper electrode that is formed on the organic layer. The bank contains a hygroscopic material. According to this display device, it is possible to confine an influence of moisture which has permeated thereinto to a more restricted area.

Abstract: The present invention relates to the field of display technology, particularly to a pixel defining layer, an organic electroluminescent device and a display device. The pixel defining layer comprises a first defining layer on an array substrate and a second defining layer on the first defining layer, wherein the first defining layer is made of a lyophilic inorganic material, and the second defining layer is made of a lyophobic organic material. The present invention provides a pixel defining layer, an organic electroluminescent device and a display device, wherein ink-jet printing technology is used to patternize pixels of an organic material, which serves as not only a protective layer on the first inorganic material layer during dry etching, but also a lyophobic layer on the second layer; the making of the double-layered pixel defining layer omits the process of using two masks, which can effectively reduce costs and improve production efficiency.

Abstract: An organic electroluminescence display device including pixels, a first bank provided between the pixels and covering a periphery edge part of a pixel electrode, a second bank provided on a first upper surface of the first bank and including a second upper surface and a first side surface, an auxiliary wiring provided on the second upper surface and including a third upper surface and a second side surface, an organic electroluminescence layer in contact with the pixel electrode, the first and second banks, and the auxiliary wiring, a common pixel electrode bridging the pixels, the organic electroluminescence layer includes a first region in contact with the pixel electrode, the first upper surface and the first side surface, and a second region in contact with the auxiliary wiring and separated from the first region, and the common pixel electrode is in contact with the second side surface.

Abstract: The present invention discloses a WOLED back panel and a method of manufacturing the same. The method comprises: forming a pattern of a color filter layer on a substrate; exposing the pattern of the color filter layer by halftone exposure so as to form a groove structure in the pattern of the color filter layer; forming a pattern of a resin material layer on a surface of the substrate formed with the groove structure, and heavily doping a partial region of the resin material layer so as to form a heavily doped part having a conductivity; the heavily doped partial region of the resin material layer corresponding to a pixel electrode region, a via region, and a connection region between the pixel electrode region and the via region; and forming an organic light-emitting layer and a cathode in order on a surface of the substrate after heavily doping the partial region of the resin material layer.

Abstract: The EL substrate includes semiconductor layers of TFTs, a pixel electrode, and an upper part electrode of a Cs section which are provided on a gate insulating film. The semiconductor layers are covered with a protective film which has openings via which the pixel electrode and the upper part electrode are exposed. The semiconductor layers are an oxide semiconductor layer, and the pixel electrode and the upper part electrode are reduction electrodes of the oxide semiconductor layer.

Abstract: A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture ratio from lowering. A capacitor storage is formed from a connection wiring line, an insulating film, and a capacitance wiring line. The connection wiring line is formed over a gate electrode and an active layer of a TFT of a pixel, and is connected to the active layer. The insulating film is formed on the connection wiring line. The capacitance wiring line is formed on the insulating film. This structure enables the capacitor storage to overlap the TFT, thereby increasing the capacity of the capacitor storage while keeping the aperture ratio from lowering. Accordingly, a change in gate voltage due to leakage or other causes can be avoided to prevent a change in luminance of an OLED and flickering of screen in analog driving.

Abstract: A display may have an array of organic light-emitting diode display pixels. Each display pixel may have a light-emitting diode that emits light under control of a drive transistor. Each display pixel may also have control transistors for compensating and programming operations. The array of display pixels may have rows and columns. Row lines may be used to apply row control signals to rows of the display pixels. Column lines (data lines) may be used to apply display data and other signals to respective columns of display pixels. A bottom conductive shielding structure may be formed below each drive transistor. The bottom conductive shielding structure may serve to shield the drive transistor from any electric field generated from the adjacent row and column lines. The bottom conductive shielding structure may be electrically floating or coupled to a power supply line.

Abstract: An organic light-emitting display apparatus includes a substrate including a display area and a non-display area disposed on one side of the display area, a line unit including a plurality of lines extending in one direction and disposed on the substrate in the non-display area, an insulating film disposed on the line unit and exposing one end of the line unit, and a metal layer disposed between the line unit and the insulating film.

Abstract: Methods of manufacture of integrated multi-layer magnetic films for use in passive devices in microelectronic applications. Soft ferromagnetic materials exhibiting high permeability and low coercivity are laminated together with insulating layers interposed. Electrical conductors coupled to interconnects are magnetically coupled to magnetic film layers to engender an inductor (self and mutual). Soft ferromagnetic materials are provided in an alternating array of parallel plate capacitors. Each alternating magnetic film is electrically coupled to either a primary or secondary electrical conductor interconnects and separated by an electrically insulating dielectric material. Alternatively, each alternating magnetic layer comprises an induced anisotropy material, which can also be combined with coiled conductor giving rise to a hybrid inductive/capacitive device. Also, soft ferromagnetic material are also selected and tuned to provide for FMR notch filtering.