Patents Issued in July 4, 2017
-
Patent number: 9697866Abstract: Embodiments of the invention provide a device for measuring pitch and roll torques. The device comprises a sensor plate having a horizontal cross member, a vertical cross member and a surrounding member connecting ends of the horizontal and vertical cross members, wherein the horizontal cross member and the vertical cross member intersect each other at a centre region of the sensor plate; a VCM coil attached to the sensor plate and configured to generate a pitch and a roll torque when an electrical current is applied to the VCM coil; a first strain gauge attached to a surface of the horizontal cross member and configured to detect a horizontal strain caused by the pitch and roll torques; and a second strain gauge attached to a surface of the vertical cross member and configured to detect a vertical strain caused by the pitch and roll torques.Type: GrantFiled: June 1, 2016Date of Patent: July 4, 2017Assignee: MMI HOLDINGS LIMITEDInventors: Steven Su, Cheng Le Wei
-
Patent number: 9697867Abstract: A narrative presentation system may include at least one optical sensor capable of detecting objects added to the field-of-view of the at least one optical sensor. Using data contained in signals received from the at least one optical sensor, an adaptive narrative presentation circuit identifies an object added to the field-of-view and identifies an aspect of a narrative presentation logically associated with the identified object. The adaptive narrative presentation circuit modifies the aspect of the narrative presentation identified as logically associated with the identified object.Type: GrantFiled: September 25, 2015Date of Patent: July 4, 2017Assignee: INTEL CORPORATIONInventors: Gila Kamhi, Nadav Zamir, Kobi Nistel, Ron Ferens, Amit Moran, Barak Hurwitz, Vladimir Kouperman
-
Patent number: 9697868Abstract: A recording apparatus, a reproduction apparatus and a file management method are disclosed wherein, even if one of files recorded on a recording medium cannot be reproduced regularly, another file selected by the user can be reproduced normally. A file having a hierarchical structure formed from video data and audio data both in the form of compressed data together with information necessary for processing of the video data and audio data is produced and recorded on a predetermined recording medium. Upon production of the file, information regarding decoding of the video data and audio data is disposed collectively on the top side of the file.Type: GrantFiled: March 7, 2012Date of Patent: July 4, 2017Assignee: SONY CORPORATIONInventors: Fumitaka Kawate, Makoto Yamada, Mitsuhiro Hirabayashi, Toshihiro Ishizaka
-
Patent number: 9697869Abstract: The disclosure is generally directed to methods, systems and apparatuses for multi-directional still pictures and/or multi-directional motion pictures and their applications on mobile, embedded, and other computing devices and applications.Type: GrantFiled: December 13, 2015Date of Patent: July 4, 2017Inventor: Jasmin Cosic
-
Patent number: 9697870Abstract: A first video preview corresponding to a first video program is played back. When it is time to transition from playing back the first video preview to playing back a second video preview corresponding to a second video program, the transition is made from playing back the first video preview to playing back the second video preview. The transition can be made by sliding the first video preview off a display while sliding the second video preview onto the display. Additionally, metadata associated with the first video program can be displayed for an amount of time before playback of the first video preview ceases, and metadata associated with the second video program can be displayed for an amount of time after playback of the second video preview begins.Type: GrantFiled: August 18, 2015Date of Patent: July 4, 2017Assignee: Microsoft Technology Licensing, LLCInventors: Mark D. Schwesinger, John Elsbree, David R. Fulmer, Evan J. Lerer, Stephane Joseph Comeau, Spencer I. A. N. Hurd
-
Patent number: 9697871Abstract: Aspects of the present disclosure relate to synchronously presenting companion content, such as text content of an electronic book, while recording or presenting narration audio content spoken by a narrator. For example, recorded audio content may be received that corresponds to words of the companion content as spoken by a narrator. The recorded audio content may be received at least substantially in real time as the words are spoken. Content synchronization information for the recorded audio content and the text content may be generated, where the content synchronization information maps portions of the recorded audio content to corresponding portions of the text content. The audio content and the text content may be synchronously presented to a user based at least in part on the content synchronization information.Type: GrantFiled: August 8, 2012Date of Patent: July 4, 2017Assignee: Audible, Inc.Inventors: Douglas C. Hwang, Guy A. Story, Jr.
-
Patent number: 9697872Abstract: A memory subsystem is disclosed. The memory subsystem includes a serial peripheral interface (SPI) double data rate (DDR) volatile memory component, a serial peripheral interface (SPI) double data rate (DDR) non-volatile memory component coupled to the serial peripheral interface (SPI) double data rate (DDR) volatile memory component and a serial peripheral interface (SPI) double data rate (DDR) interface. The serial peripheral interface (SPI) double data rate (DDR) interface accesses the serial peripheral interface (SPI) double data rate (DDR) volatile memory component and the serial peripheral interface (SPI) double data rate (DDR) non-volatile memory component where data is accessed on leading and falling edges of a clock signal.Type: GrantFiled: December 7, 2011Date of Patent: July 4, 2017Assignee: Cypress Semiconductor CorporationInventors: Kevin Widmer, Anthony Le, Cliff Zitlaw
-
Patent number: 9697873Abstract: Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F2.Type: GrantFiled: July 26, 2016Date of Patent: July 4, 2017Assignee: Micron Technology, Inc.Inventor: Zengtao T. Liu
-
Patent number: 9697874Abstract: Providing for a monolithic memory device comprising a combination of a one-transistor, one-resistor (1T1R) memory array, and a one-transistor, multiple-resistor (1TnR, where n is a suitable integer greater than 1) memory array is described herein. By way of example, the monolithic memory device can be a stand-alone device, configured to perform functions in response to predetermined conditions and generate an output(s), or can be a removable device that can be connected to and operable with another device. In various embodiments, the 1TnR array having high memory density can serve as storage class memory (SCM) for the monolithic memory device, and the 1T1R array having high performance and efficacy can serve as code memory. In addition to the foregoing, the 1T1R array and the 1TnR array can be fabricated from at least one common layer or a common processing step, to simplify and lower cost of fabricating disclosed memory devices.Type: GrantFiled: June 9, 2016Date of Patent: July 4, 2017Assignee: CROSSBAR, INC.Inventors: Mehdi Asnaashari, Sundar Narayanan
-
Patent number: 9697875Abstract: A data reception chip coupled to an external memory including a first input-output pin configured to output first data and including a comparison module and a voltage generation module is provided. The comparison module is coupled to the first input-output pin to receive the first data and to compare the first data with a first reference voltage to identify the value of the first data. The voltage generation module is configured to generate the first reference voltage. The voltage generation module includes a first resistor and a second resistor. The second resistor is connected to the first resistor in series. The first and second resistors divide a first operation voltage to generate the first reference voltage.Type: GrantFiled: December 15, 2015Date of Patent: July 4, 2017Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.Inventors: Hongquan Sun, Minglu Xu, Jiajia Xia
-
Patent number: 9697876Abstract: Examples of the present disclosure provide apparatuses and methods for vertical bit vector shift in a memory. An example method comprises storing a vertical bit vector of data in a memory array, wherein the vertical bit vector is stored in memory cells coupled to a sense line and a plurality of access lines and the vertical bit vector is separated by at least one sense line from a neighboring vertical bit vector; and performing, using sensing circuitry, a vertical bit vector shift of a number of elements of the vertical bit vector.Type: GrantFiled: March 1, 2016Date of Patent: July 4, 2017Assignee: Micron Technology, Inc.Inventors: Sanjay Tiwari, Kyle B. Wheeler
-
Patent number: 9697877Abstract: A compute memory system can include a memory array and a controller that generates N-ary weighted (e.g., binary weighted) access pulses for a set of word lines during a single read operation. This multi-row read generates a charge on a bit line representing a word stored in a column of the memory array. The compute memory system further includes an embedded analog signal processor stage through which voltages from bit lines can be processed in the analog domain. Data is written into the memory array in a manner that stores words in columns instead of the traditional row configuration.Type: GrantFiled: February 5, 2015Date of Patent: July 4, 2017Assignee: THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOISInventors: Naresh Shanbhag, Mingu Kang, Min-Sun Keel
-
Patent number: 9697878Abstract: A word line divider which has a simplified circuit structure and can operate stably is provided. A storage device which has a simplified circuit structure and can operate stably is provided. A transistor whose leakage current is extremely low is connected in series with a portion between a word line and a sub word line so that the word line divider is constituted. The transistor can include an oxide semiconductor for a semiconductor layer in which a channel is formed. Such a word line divider whose circuit structure is simplified is used in the storage device.Type: GrantFiled: May 16, 2012Date of Patent: July 4, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shuhei Nagatsuka, Takanori Matsuzaki, Hiroki Inoue
-
Patent number: 9697879Abstract: In some examples, a memory device may be configured to use shared read circuitry to sample a voltage drop across both a bit cell and a resistive circuit in order to perform a comparison that produces an output corresponding to the bit stored in the bit cell. The shared read circuitry can include a shared sense amplifier as well as shared N-MOS and P-MOS followers used to apply read voltages across the bit cell and resistive circuit.Type: GrantFiled: December 1, 2016Date of Patent: July 4, 2017Assignee: EVERSPIN TECHNOLOGIES, INC.Inventors: Syed M. Alam, Chitra K. Subramanian
-
Patent number: 9697880Abstract: Self-referenced reading of a memory cell in a memory includes first applying a read voltage across the memory cell to produce a sample voltage. After applying the read voltage, a write current is applied to the memory cell to write a first state to the memory cell. After applying the write current, the read voltage is reapplied across the memory cell. An offset current is also applied while the read voltage is reapplied, and the resulting evaluation voltage from reapplying the read voltage with the offset current is compared with the sample voltage to determine the state of the memory cell.Type: GrantFiled: June 25, 2016Date of Patent: July 4, 2017Assignee: Everspin Technologies, Inc.Inventors: Thomas Andre, Syed M. Alam, Chitra Subramanian
-
Patent number: 9697881Abstract: Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. The method further comprises applying another of the positive bias voltage and the negative bias voltage to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Ferroelectric memory cells are also described.Type: GrantFiled: August 19, 2016Date of Patent: July 4, 2017Assignee: Micron Technology, Inc.Inventors: Steven C. Nicholes, Ashonita A. Chavan, Matthew N. Rocklein
-
Patent number: 9697882Abstract: A ferroelectric memory and a method for operating a ferroelectric memory are disclosed. The ferroelectric memory includes a ferroelectric memory cell having a ferroelectric capacitor characterized by a maximum remanent charge, Qmax. A write circuit receives a data value having more than two states for storage in the ferroelectric capacitor. The write circuit measures Qmax for the ferroelectric capacitor, determines a charge that is a fraction of the measured Qmax to be stored in the ferroelectric capacitor, the fraction being determined by the data value. The write circuit causes a charge equal to the fraction times Qmax to be stored in the ferroelectric capacitor. A read circuit determines a value stored in the ferroelectric capacitor by measuring a charge stored in the ferroelectric capacitor, measuring Qmax for the ferroelectric capacitor, and determining the data value from the measured charge and the measured Qmax.Type: GrantFiled: August 30, 2016Date of Patent: July 4, 2017Assignee: Radiant Technologies, Inc.Inventors: Joseph T. Evans, Jr., Calvin B. Ward
-
Patent number: 9697883Abstract: A optical link for achieving electrical isolation between a controller and a memory device is disclosed. The optical link increases the noise immunity of electrical interconnections, and allows the memory device to be placed a greater distance from the processor than is conventional without power-consuming I/O buffers.Type: GrantFiled: February 24, 2016Date of Patent: July 4, 2017Assignee: Micron Technology, Inc.Inventors: Jacob Baker, Brent Keeth
-
Patent number: 9697884Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable, and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.Type: GrantFiled: September 12, 2016Date of Patent: July 4, 2017Assignee: Rambus Inc.Inventors: Frederick A. Ware, John Eric Linstadt, Kenneth L. Wright
-
Patent number: 9697885Abstract: A semiconductor memory device includes: a weak cell controller for programming weak cell information, outputting the weak cell information in response to an initialization signal or a write end signal, and outputting a read end signal whenever the weak cell information is outputted; a memory cell array region that includes memory cells for storing data in response to a row active signal and a column selection signal, and includes a first cell region for storing the weak cell information; an information transfer control circuit for generating a column address based on a column counting signal generated by using the read end signal, and generating a row address whenever the column counting signal reaches a predetermined value in response to the initialization signal; a row circuit for enabling the row active signal; and a column circuit for outputting the column selection signal by decoding the column address.Type: GrantFiled: October 19, 2016Date of Patent: July 4, 2017Assignee: SK Hynix Inc.Inventor: Youk-Hee Kim
-
Patent number: 9697886Abstract: A semiconductor storage device having a plurality of low power consumption modes is provided. The semiconductor storage device includes a plurality of memory modules where a plurality of low power consumption modes can be set and cancelled based on a first and a second control signals. At least a part of memory modules of the plurality of memory modules have a propagation path that propagates an inputted first control signal to a post stage memory module. The second control signal is inputted into each of the plurality of memory modules in parallel. Setting and cancelling of the first low power consumption mode of each memory module are performed based on a combination of the first control signal that is propagated through the propagation path and the second control signal.Type: GrantFiled: July 15, 2016Date of Patent: July 4, 2017Assignee: Renesas Electronics CorporationInventors: Makoto Yabuuchi, Shinji Tanaka
-
Patent number: 9697887Abstract: Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would be when global write assist logic units and the read/write global column multiplexers are used. Described is a dual input level-shifter with integrated latch. Described is an apparatus which comprises: a write assist pulse generator operating on a first power supply; one or more pull-up devices coupled to the write assist pulse generator, the one or more pull-up devices operating on a second power supply different from the first power supply; and an output node to provide power supply to a memory cell.Type: GrantFiled: October 15, 2015Date of Patent: July 4, 2017Assignee: Intel CorporationInventors: Hieu T. Ngo, Daniel J. Cummings
-
Patent number: 9697888Abstract: The present patent application describes 9T, 8T, and 7T versions of bitcells used with 1R1W memories. It also describes 9T, 8T, and 7T versions of bitcells used with single port SRAM memories. Different circuits are discussed to support different bitcells and architectures mentioned above. Our 1R1W and single port bitcells and architectures give significant advantages over the conventional bitcells and architectures.Type: GrantFiled: April 12, 2016Date of Patent: July 4, 2017Assignee: SKAN TECHNOLOGIES CORPORATIONInventor: Sudhir S. Moharir
-
Patent number: 9697889Abstract: According to one general aspect, an apparatus may include a bit cell configured to store a bit of information. The apparatus may include a first voltage configured to supply the bit cell with power. The apparatus may include a wordline driver configured to cause the bit to be read from the bit cell. The wordline driver may be configured to operate during a read operation at a second voltage that is lower than the first voltage, wherein the second voltage is determined by charge sharing between a plurality of capacitances. The wordline driver may include a switch configured to disconnect the wordline driver from the first voltage before an input word line signal is applied to the wordline driver, and wherein the switch is responsive to a clock signal.Type: GrantFiled: April 29, 2016Date of Patent: July 4, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kevin E. Klein, Prashant U. Kenkare
-
Patent number: 9697890Abstract: An interface circuit is provided. A NMOS transistor is coupled between a first bit line and a ground. A logic gate is coupled between a gate of the NMOS transistor and a second bit line. A keeper controls a voltage level of the second bit line according to a reference voltage. A tracking circuit includes a plurality of reference bit cells and a pull-up device coupled to a reference bit line. Each reference bit cell is coupled to a read word line. When a bit cell coupled to the second bit line is accessed by a specific read word line, the reference bit cell coupled to the specific read word line drains a current from the pull-up device. The tracking circuit provides the reference voltage according to the current.Type: GrantFiled: June 1, 2016Date of Patent: July 4, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Bing Wang
-
Patent number: 9697891Abstract: A sense amplifier circuit includes a power node having a power node voltage at a power voltage level, a bit line having a bit line voltage, a sense amplifier output, an NMOS transistor and a PMOS transistor coupled in series between the power node and the bit line, and a logic gate configured to generate a sense amplifier output voltage at the sense amplifier output based on the bit line voltage. The NMOS transistor is configured to operate in a sub-threshold region to maintain the bit line voltage at a first level and operate in a region above the sub-threshold region to maintain the bit line voltage at a second level, and the first level is between the second level and the power voltage level.Type: GrantFiled: November 2, 2016Date of Patent: July 4, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Bharath Upputuri
-
Patent number: 9697892Abstract: The present disclosure includes apparatuses, methods, and non-transitory computer-readable storage mediums for generation and application of gray codes. One example method comprises: selecting a particular N-bit member as a root member for a plurality of N-bit gray codes each comprising X members such that each of the plurality of N-bit gray codes comprise a same root member; and generating X?1 remaining members of the respective plurality of N-bit gray codes by performing X?1 member generation iterations, wherein each ith iteration of the X?1 member generation iterations generates respective ith members of the plurality of N-bit gray codes based on ith?1 members, with each one of the respective ith members comprising only those eligible neighbor members of a respective one of the ith?1 members, and with “i” being a whole number index from 1 to X?1.Type: GrantFiled: October 4, 2016Date of Patent: July 4, 2017Assignee: Micron Technology, Inc.Inventors: Chandra C. Varanasi, Bruce A. Liikanen
-
Patent number: 9697893Abstract: An embodiment of a driving circuit is provided. The driving circuit is coupled to an I/O pad. The driving circuit includes an output driver, a first termination resistor, a second termination resistor and a monitoring circuit. The output driver outputs an output data via the I/O pad. The first termination resistor and the second termination resistor are coupled to a node between the output driver and the I/O pad. The monitoring circuit monitors a first current passing through the first termination resistor and adjusts resistance of the first termination resistor and the second termination resistor according to the first current.Type: GrantFiled: May 17, 2016Date of Patent: July 4, 2017Assignee: NUVOTON TECHNOLOGY CORPORATIONInventor: Chia-Ching Lu
-
Patent number: 9697894Abstract: A method may include applying a first current through the memory element and a first selection component. The memory element and the first selection component may be located along a memory line. The method may also include measuring a first potential difference across the memory line. The method may further include applying a second current through a second selection component, wherein the second selection component is located along a dummy line, and measuring a second potential difference across the dummy line. The method may additionally include determining the resistance of the memory element based on the first potential difference and the second potential difference. The first selection component may be activated and the second selection component may be deactivated to apply the first current. The first selection component may be deactivated and the second selection component may be activated to apply the second current.Type: GrantFiled: March 25, 2014Date of Patent: July 4, 2017Assignee: Agency for Science, Technology and ResearchInventors: Fei Li, Kit Ho Melvin Chow
-
Patent number: 9697895Abstract: An integrated circuit according to an embodiment includes: a plurality of first wiring lines; a plurality of second wiring lines intersecting with the plurality of first wiring lines; a plurality of resistive change memory elements provided in cross regions of the plurality of first and second wiring lines, each of which includes a first electrode connected to a corresponding first wiring line, a second electrode connected to a corresponding second wiring line, and a resistive change layer provided between the first and second electrodes, and in each of which a resistive state between the first electrode and the second electrode can be programmed from one of a first resistive state and a second resistive state, which has a larger resistance value than the first resistive state, to the other; and a driver driving the plurality of first and second wiring lines.Type: GrantFiled: September 14, 2016Date of Patent: July 4, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Koichiro Zaitsu
-
Patent number: 9697896Abstract: A phase change non-volatile memory device has a memory array with a plurality of memory cells arranged in rows and columns, a column decoder and a row decoder designed to select columns, and, respectively, rows of the memory array during operations of programming of corresponding memory cells. A control logic, coupled to the column decoder and the row decoder, is designed to execute a sequential programming command, to control the column decoder and row decoder to select one column of the memory array and execute sequential programming operations on a desired block of memory cells belonging to contiguous selected rows of the selected column.Type: GrantFiled: February 16, 2015Date of Patent: July 4, 2017Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS PTE LTD.Inventors: Antonino Conte, Alberto Jose′ Di Martino, Kailash Khairnar
-
Patent number: 9697897Abstract: A memory device includes a volatile memory cell, a non-volatile memory cell, and a transfer system connected between the volatile memory cell and the non-volatile memory cell. The transfer circuit allows data transfer from the volatile memory cell to the non-volatile memory cell when the memory device is operating in a first mode, and from the non-volatile memory cell to the volatile memory cell when the memory device is operating in a second mode.Type: GrantFiled: July 15, 2014Date of Patent: July 4, 2017Assignee: NXP USA, Inc.Inventors: Michael A Sadd, Anirban Roy
-
Patent number: 9697898Abstract: A content addressable memory system, method and computer program product is described. The memory system comprises a location addressable store having data identified by location and multiple levels of content addressable stores each holding ternary content words. The content words are associated with references to data in the location addressable store and the content words containing at least one next entry bit for sorting content words in a physical ordered sequence to create content ordered memory. The content store levels might be implemented using different technologies that have different performance, capacity, and cost attributes. The memory system includes a content based cache for improved performance and a content addressable memory management unit for managing memory access operations and virtual memory addressing.Type: GrantFiled: September 24, 2015Date of Patent: July 4, 2017Assignee: International Business Machines CorporationInventors: Samuel Scott Adams, Suparna Bhattacharya, Robert R. Friedlander, James R. Kraemer
-
Patent number: 9697899Abstract: Described are apparatuses, methods and storage media associated with performing deflate decompression using multiple parallel content addressable memory cells.Type: GrantFiled: December 21, 2015Date of Patent: July 4, 2017Assignee: Intel CorporationInventors: Lokpraveen B. Mosur, Sailesh Bissessur, Pradnyesh S. Gudadhe, Quinn W. Merrell
-
Patent number: 9697901Abstract: A three-dimensional (3D) flash memory includes a first dummy word line disposed between a ground select line and a lowermost main word line, and a second dummy word line of different word line configuration disposed between a string select line and an upper most main word line.Type: GrantFiled: July 14, 2016Date of Patent: July 4, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Wan Nam, Kitae Park
-
Patent number: 9697902Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes memory cell units, bit lines, word lines, and a controller. Each of the memory cell units includes a plurality of memory cells connected in series. Bit lines are connected respectively to the corresponding memory cell units. Each of the word lines is commonly connected to control gates of the corresponding memory cells of the memory cell units. The controller is configured to control a programming operation of data to the memory cells. The controller is configured to execute a first procedure including programming the data to the memory cell connected to the (4n?3)th (n being a natural number) bit line and the memory cell connected to the (4n?2)th bit line, and a second procedure including programming the data to the memory cell connected to the (4n?1)th bit line and the memory cell connected to the 4nth bit line.Type: GrantFiled: March 6, 2014Date of Patent: July 4, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Yusuke Umezawa, Shigeru Kinoshita
-
Patent number: 9697903Abstract: A data storage device includes a nonvolatile memory device; and a controller suitable for providing a normal erase command or a fine erase command to the nonvolatile memory device, wherein the nonvolatile memory device performs a first normal erase loop in which a first normal erase voltage and an erase verify voltage are applied to erase target memory cells, according to the normal erase command, and performs a first fine erase loop in which a first fine erase voltage and the erase verify voltage are applied to the erase target memory cells, according to the fine erase command.Type: GrantFiled: March 25, 2016Date of Patent: July 4, 2017Assignee: SK Hynix Inc.Inventor: Gi Pyo Um
-
Patent number: 9697904Abstract: An integrated circuit includes a mirroring/amplifying unit suitable for mirroring and amplifying a sensing current that flows on a signal transmission line coupled to an internal circuit, and outputting an amplified current; a reference current generating unit suitable for generating a reference current; and a state determination unit suitable for comparing the reference current with the amplified current and determining a state of the internal circuit based on a comparison result.Type: GrantFiled: October 25, 2013Date of Patent: July 4, 2017Assignee: SK Hynix Inc.Inventor: Sung-Hoon Ahn
-
Patent number: 9697905Abstract: A method performed at a data storage device includes adjusting a first read voltage and a second read voltage to form sets of read voltages. First representations of data are read from a logical page in the non-volatile memory according to the sets of read voltages. The first representations of the data correspond to multiple values of the first read voltage and the second read voltage. The first representations of the data are stored in a memory and second representations of the data are generated based on the first representations. A value of the first read voltage is selected based on syndrome weights corresponding to the second representations.Type: GrantFiled: December 4, 2014Date of Patent: July 4, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Eran Sharon, Ariel Navon, Alexander Bazarsky
-
Patent number: 9697906Abstract: A controlling block for a non-volatile memory device including a switching element coupling a bit-line with the corresponding page buffer, includes: a look-up table configured to store a plurality of address zones; and a matching logic configured to match one address zone among the plurality of address zones based on an inputted row address and generate a bias voltage, based on the address zone, to the switching element for reading operation of the non-volatile memory, wherein the plurality of address zones are defined by grouping word-lines having a I-V characteristic which differs for a current value different from a prefixed value.Type: GrantFiled: July 19, 2016Date of Patent: July 4, 2017Assignee: SK Hynix Inc.Inventor: Alessandro Sanasi
-
Patent number: 9697907Abstract: Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory cells, a second memory string including third and fourth dummy memory cells, and a control unit configured to provide first and second control signals to activate the first and second dummy memory cells of the first memory string and to further deactivate at least one of the third and fourth dummy memory cell of the second memory string.Type: GrantFiled: August 3, 2016Date of Patent: July 4, 2017Assignee: Micron Technology, Inc.Inventors: Toru Tanzawa, Aaron Yip
-
Patent number: 9697908Abstract: Various implementations described herein may refer to and may be directed to non-discharging read-only memory cells. For instance, in one implementation, an integrated circuit may include a read-only memory (ROM) array including a plurality of ROM cells arranged into a column, where the column is disposed proximate to a bit line and to a reference voltage line. The plurality of ROM cells arranged into the column may include a plurality of non-discharging ROM cells positioned adjacently to one another, where each non-discharging ROM cell has a source terminal, a drain terminal, or both coupled to at least one adjacent non-discharging ROM cell. In addition, the plurality of non-discharging ROM cells may be coupled to the bit line using two or fewer connections.Type: GrantFiled: June 10, 2016Date of Patent: July 4, 2017Assignee: ARM LimitedInventors: Kapil Rathi, Abhishek Kumar Shrivastava, Vikash
-
Patent number: 9697909Abstract: A shift register comprises a first switch, a second switch, a third switch, and a fourth switch. The first switch selectively conducts a first clock signal to a first output terminal as a first output signal based on a voltage level over the control terminal. The second switch selectively forces a voltage level of the first output signal to be equal to a voltage level of a second clock signal based on both of the second clock signal and a third clock signal inverted to the second clock signal. The third switch selectively defines a voltage over the control terminal to be a first voltage based on a first input signal. The fourth switch selectively forces the voltage level over the control terminal to be equal to the voltage level of the second clock signal based on both of the second clock signal and the third clock signal.Type: GrantFiled: July 21, 2015Date of Patent: July 4, 2017Assignee: AU OPTRONICS CORP.Inventors: Ya-Ling Chen, Ching-Kai Lo, Chien-Chung Huang, Hua-Gang Chang
-
Patent number: 9697910Abstract: An aspect includes a method of multi-match error detection in content addressable memory (CAM) testing. The method includes loading a content addressing row of a CAM section with a row test address word. Data value rows of a random access memory (RAM) section are loaded with unique test patterns in each of the data value rows having a same number of on-state bits per data value row. A row test is initiated to search for a matching content addressing row in the CAM section corresponding to the row test address word. A row test result is received as one or more data value rows from the RAM section identified as having a content addressing row in the CAM section that matches the row test. The row test result is compared to an aspect of one or more of the unique test patterns to determine whether the row test has failed.Type: GrantFiled: March 30, 2016Date of Patent: July 4, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William V. Huott, Pradip Patel, Daniel Rodko
-
Patent number: 9697911Abstract: Provided is a semiconductor storage device including: first memory cells; first word lines; first bit lines; a first common bit line; second memory cells; second word lines; second bit lines; a second common bit line; a first selection circuit that connects the first common bit line to a first bit line selected from the first bit lines; a second selection circuit that connects the second common bit line to a second bit line selected from the second bit lines; a word line driver that activates any one of the first and second word lines; a reference current supply unit that supplies a reference current to a common bit line among the first and second common bit lines, the common bit line not being electrically connected to a data read target memory cell; and a sense amplifier that amplifies a potential difference between the first and second common bit lines.Type: GrantFiled: October 28, 2016Date of Patent: July 4, 2017Assignee: Renesas Electronics CorporationInventor: Makoto Yabuuchi
-
Patent number: 9697912Abstract: A first switch is closed to initialize a circuit by charging a capacitance of the circuit. A second switch is closed to initialize an amplifier in unity-gain configuration. The amplifier is capacitively coupled to the circuit. The first switch and the second switch are then opened to detect a leakage current of the circuit by detecting a change in an output voltage of the amplifier.Type: GrantFiled: May 26, 2016Date of Patent: July 4, 2017Assignee: Micron Technology, Inc.Inventors: Feng Pan, Shigekazu Yamada
-
Patent number: 9697913Abstract: Methods, systems, and devices for recovering fatigued ferroelectric memory cells are described. Recovery voltages may be applied to a ferroelectric memory cell that is fatigued due to repeated access (read or write) operations. The recovery voltage may have a greater amplitude than the access voltage and may include multiple voltage pulses or a constant voltage. The recovery operation may be performed in the background as the memory array operates, or it may be performed when a host device is not actively using the memory array. The recovery operations may be performed periodically or may include discrete series of pulses distributed among several instances.Type: GrantFiled: June 10, 2016Date of Patent: July 4, 2017Assignee: MICRON TECHNOLOGY, INC.Inventors: Marcello Mariani, Giorgio Servalli, Andrea Locatelli
-
Patent number: 9697914Abstract: According to an embodiment, a nuclear power plant has a core; a reactor pressure vessel; a dry well; a wet well; a vacuum breaker; a containment vessel including the dry well, the LOCA vent pipe, the wet well, and the vacuum breaker; a cooling water pool placed outside the containment vessel; a heat exchanger at least partially submerged in cooling water; a gas supply pipe connected to the inlet plenum of the heat exchanger and the dry well; a condensate return pipe connected to the outlet plenum of the heat exchanger and the containment vessel; and a gas vent pipe connected to the outlet plenum of the heat exchanger and an outside of the wet well so that non-condensable gas inside the heat exchanger is released out of the wet well. The gas vent pipe is not connected to the wet well.Type: GrantFiled: June 19, 2013Date of Patent: July 4, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Sato, Keiji Matsumoto
-
Patent number: 9697915Abstract: A pit gate 15 that is accommodated in a slot 14 and that seals service water retained in a first pit and a second pit in a watertight manner includes a gate main body 21; a sealing member 22 that is provided on a surface opposite to the slot 14 in a gate main body 21 and that seals between the gate main body 21 and the slot 14 in a watertight manner; and an upper pressing clamp 23, an intermediate pressing clamp 24, and a lower pressing clamp 25 that are provided in the gate main body 21 and that moves gate main body 21 toward the sealing member 22 side due to the weight of the gate main body 21 itself.Type: GrantFiled: June 26, 2015Date of Patent: July 4, 2017Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.Inventors: Takafumi Tsuge, Takao Ito, Yuki Matsushima
-
Patent number: 9697916Abstract: An automated system for on-line monitoring and coil diagnostics of rod position indicator (RPI) coils coil diagnostic, or RPI coil diagnostic system. The RPI coil diagnostic system performs coil diagnostics for a RPI system in a nuclear power plant. The RPI coil diagnostic system is in electrical communication with and monitors the outputs of the detector coils. The RPI coil diagnostic system measures characteristics of the detector coils that are indicative of the health of the detector coils and/or the connections between the detector coils and the RPI electronics.Type: GrantFiled: January 9, 2009Date of Patent: July 4, 2017Assignee: Analysis And Measurement CorporationInventors: Brent D. Shumaker, Hashem M. Hashemian, Gregory W. Morton, Danny D. Beverly, Casey D. Sexton