Patents Issued in August 1, 2017
  • Patent number: 9722552
    Abstract: A circuit that includes a Darlington transistor pair having an input transistor and an output transistor configured to generate an output signal at an output node in response to an input signal received through an input node is disclosed. The circuit has a feedback coupling network coupled between the output node and the input node for feeding back to the input node a portion of an amplified version of the input signal that passes through the input transistor. The circuit further includes a bias feedback network that includes a bias transistor and a resistive network that consists of only resistive elements such that no inductors and no capacitors are provided within the bias feedback network.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: August 1, 2017
    Assignee: Qorvo US, Inc.
    Inventor: Kevin Wesley Kobayashi
  • Patent number: 9722553
    Abstract: A high-frequency amplifier circuit comprising a first and a second amplification units connected in cascade structure and so on. The first amplification unit includes an FET of a first conductivity type having a source terminal supplied with a first potential, and a first inductor connected to an intermediate potential line, and the second amplification unit includes an FET of a second conductivity type having a source terminal supplied with a second potential, and a second inductor connected to the intermediate potential line. The intermediate potential line is supplied with an intermediate potential between the first and second potentials. The first and second amplification units are supplied with bias voltages by a first and a second bias units, respectively. An operating current for the second bias unit is controlled on the basis of the intermediate potential.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: August 1, 2017
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Tetsuaki Yotsuji
  • Patent number: 9722554
    Abstract: When the offsets of the first and second differential units have polarities different from each other, the first and second differential units are both set to a normal connection state, i.e., a state in which the input voltage is supplied to the first input terminal of each of the first and second differential units and the output voltage is supplied to the second input terminal of each of the first and second differential units. When the offsets of the first and second differential units have the same polarity, on the other hand, the first differential unit is set to the above normal connection state and the second differential unit is set to a chopping connection state in which the output voltage is supplied to the first input terminal and the input voltage is supplied to the second input terminal.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: August 1, 2017
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Koji Higuchi
  • Patent number: 9722555
    Abstract: The present invention is directed to electrical circuits and techniques thereof. More specifically, embodiments of the present invention provide a differential amplifier that has a differential amplifier section, a current source, and a feedback section. The differential amplifier section comprises NMOS transistors that receives two voltage inputs and generate a differential output. The current source provides a long tail for the differential amplifier section. The feedback section generates a feedback voltage based on a reference bias voltage. The feedback voltage is used by an amplifier to control the current source and to keep the biasing and gain of the differential amplifier substantially constant. There are other embodiments as well.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: August 1, 2017
    Assignee: INPHI CORPORATION
    Inventors: Rajasekhar Nagulapalli, Simon Forey, Parmanand Mishra
  • Patent number: 9722556
    Abstract: The present invention relates to a high frequency transformer for a differential amplifier. An exemplary embodiment of the present invention provides a high frequency transformer for a differential amplifier, including: a first metal line that is integrated and formed in an IC chip through a CMOS process and that is connected to a differential signal line of a transistor included in the IC chip; and a second metal line that is formed in an MEMS chip through an MEMS process and that is inductively coupled with the first metal line in a state spaced apart from an upper portion of the first metal line, wherein the MEMS chip may be stacked on an upper portion of the IC chip.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: August 1, 2017
    Assignee: SOONGSIL UNIVERSITY RESEARCH CONSORTIUM TECHNO-PARK
    Inventors: Mi Lim Lee, Chang Kun Park
  • Patent number: 9722558
    Abstract: A sound volume is adjusted in accordance with a volume adjustment coefficient ka calculated in accordance with a coefficient map with respect to an accelerator opening angle APO and another volume adjustment coefficient kv calculated in accordance with the coefficient map with respect to a vehicle speed V. The coefficient map with respect to vehicle speed V is set such that, as accelerator opening angle APO becomes higher, volume adjustment coefficient ka becomes larger in a sigmoid configuration. In addition, the coefficient map with respect to accelerator opening angle APO is set such that, as vehicle speed V becomes higher, volume adjustment coefficient kv becomes smaller in the sigmoid configuration.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: August 1, 2017
    Assignee: NISSAN MOTOR CO., LTD.
    Inventors: Shunichi Kanehara, Koji Shionome
  • Patent number: 9722559
    Abstract: A hybrid fiber amplifier and method of adjusting gain and gain slope of thereof. The hybrid fiber amplifier comprises: RFA and EDFA that does not comprise variable optical attenuator. The RFA comprises pump signal combiner, pump laser group, out-of-band narrow-band filter, and photodetector. The EDFA comprises input coupler, erbium-doped fiber, output coupler, input photodetector, and output photodetector that are connected in sequence. The hybrid fiber amplifier also comprises control module that coordinates and controls EDFA and/or RFA to adjust gain and/or the gain slope based on desired amplification requirements. The EDFA and/or RFA can be coordinated and controlled by using the control module to achieve desired amplification effect. In addition, the EDFA does not comprise the variable optical attenuator, which avoids problems caused by the variable optical attenuator.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: August 1, 2017
    Assignee: Accelink Technologies Co., Ltd.
    Inventors: Chengpeng Fu, Cuihong Zhang, Tao Xiong, Menghui Le, Jintao Tao, Zhenyu Yu, Yunyu Jing, Qinlian Bu, Chunping Yu
  • Patent number: 9722560
    Abstract: A filter for equalizing the frequency response of loudspeaker systems includes at least one band filter section (11) comprised an n-order high boost or cut shelving fitter (13) having a break point frequency, ?1, and an n-order low boost or cut shelving filter (15) having a break point frequency, ?2, wherein ?1<?2. The order, n, of at least one, and preferably both of the shelving filters of the band filter sections can be selected for adjusting the slope of the shelving filter at one or both of its break point frequencies. The high and low n-order shelving filters forming the band filter sections have substantially the same gain and produce a resultant band gain for the band filter section. Gain correction is provided for the selectable n-order high shelving filter and n-order low shelving filter for correcting the resultant band gain to a base gain level.
    Type: Grant
    Filed: May 31, 2014
    Date of Patent: August 1, 2017
    Assignee: Meyer Sound Laboratories, Incorporated
    Inventors: David Lorente, Todd Meier, Perrin Meyer, Luke Jenks
  • Patent number: 9722561
    Abstract: A device is provided. The device includes: a sensor adapted to receive an acoustic wave and generate an electrical signal in response to receipt of the acoustic wave; clock frequency detection circuitry adapted to receive a clock signal, detect a frequency of the clock signal and generate information representative of the frequency; and digital filter circuitry coupled to the clock frequency detection circuitry. The digital filter circuitry is adapted to: receive the clock signal and the information representative of the frequency; access a first set of one or more digital filter coefficient values; and selectively change the first set of the one or more digital filter coefficient values to a second set of one or more digital filter coefficient values based on the information representative of the frequency, wherein the one or more digital filter coefficient values are included within a plurality of digital filter coefficient values.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: August 1, 2017
    Assignee: INVENSENSE, INC.
    Inventor: Olafur Mar Josefsson
  • Patent number: 9722562
    Abstract: The present application describes signal enhancements to reduce bone conduction sensations of a wearable computing device and applications thereof. An example apparatus includes a wearable computing device comprising a bone conduction transducer (BCT) configured to receive and be driven by an audio signal, a processor, and a data storage comprising instructions executable by the processor to: (1) determine an input gain level of the audio signal at a frequency range; (2) compare the determined input gain level at the frequency range to a threshold gain level at the frequency range; (3) based on the comparison, apply a multi-band compressor (MBC) configured to process the audio signal to reduce gain in at least a portion of a mid-band frequency range of the audio signal; and (4) drive the BCT with the processed audio signal.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: August 1, 2017
    Assignee: Google Inc.
    Inventor: Chad Seguin
  • Patent number: 9722563
    Abstract: In accordance with an embodiment, a method includes determining an amplitude of an input signal provided by a capacitive signal source, compressing the input signal in an analog domain to form a compressed analog signal based on the determined amplitude, converting the compressed analog signal to a compressed digital signal, and decompressing the digital signal in a digital domain to form a decompressed digital signal. In an embodiment, compressing the analog signal includes adjusting a first gain of an amplifier coupled to the capacitive signal source, and decompressing the digital signal comprises adjusting a second gain of a digital processing block.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: August 1, 2017
    Assignee: Infineon Technologies AG
    Inventors: Michael Kropfitsch, Jose Luis Ceballos
  • Patent number: 9722564
    Abstract: An EMI filter network may be used to provide interference filtering for multiple loads (referred to collectively as a dynamic load). In one aspect, the EMI filter network includes electrical switches that establish different configurations or arrangements of passive circuit elements (e.g., inductors and capacitors) where each configuration generates a different filter value. The EMI filter network may be communicatively coupled to a controller which changes the configuration of the EMI filter network using the switches in response to the dynamic load changing operational states. For example, each configuration of the EMI filter network may correspond to one of the operational states of the dynamic load. Thus, as the operational state of the dynamic load changes—e.g., different motors become operational—the controller alters the configuration of the EMI filter network to provide a filter value that corresponds to the current operational state of the dynamic load.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: August 1, 2017
    Assignee: THE BOEING COMPANY
    Inventors: Yujie Song, Shengyi Liu, Eugene Solodovnik, Kamiar J. Karimi
  • Patent number: 9722565
    Abstract: A filter component includes a housing body. A first and at least one second busbar each have a first end section, and a second end section, between which in each case a center section is arranged. The end sections of the busbars each have connections for connecting electrical conductors to the filter component. The first and second end section and the center section of the first busbar are arranged in a first plane and the first and second end section and the center section of the at least one second busbar are arranged in a second plane, which is different from the first plane.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: August 1, 2017
    Assignee: EPCOS AG
    Inventor: Fabian Beck
  • Patent number: 9722566
    Abstract: A high-Q factor resonator includes a solenoid having an embedded capacitor assembled in a machinable high-frequency dielectric printed circuit board (“PCB”), or other substrate. The solenoid comprises a plurality of surface conductors positioned on upper and lower surfaces of the PCB. The solenoid further comprises a plurality of conductive vias extending through the PCB between the surface conductors, and at least two aligned vias are separated by a capacitive gap. A liquid crystal dielectric is embedded within the capacitive gap in order to control the capacitance. Accordingly, a tunable capacitive filter is achieved by changing the dielectric permittivity of the liquid crystal. In one example, a nematic liquid crystal is sealed in the capacitive gap and has its permittivity changed with a low frequency bias to tune the capacitor.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: August 1, 2017
    Assignee: Board of Trustees of the University of Alabama, for and on behalf of the University of Alabama in Huntsville
    Inventors: John D. Williams, Robert Lindquist
  • Patent number: 9722567
    Abstract: A variable-frequency resonance circuit includes first and second input/output terminals and a resonance circuit portion. The resonance circuit portion includes a first inductor and first and second LC series circuits. The resonance circuit portion is connected between a ground and a transmission line that connects the first and second input/output terminals. The first LC series circuit includes a second inductor and a variable capacitor connected in series with each other. The second LC series circuit includes a third inductor and a fixed capacitor connected in series with each other. The first and second LC series circuits are connected in parallel between the first inductor and a ground. The first and second inductors are configured such that positive-coupling mutual inductance is produced therebetween.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: August 1, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasushi Yunoki, Tetsuo Taniguchi, Keisuke Katabuchi
  • Patent number: 9722568
    Abstract: Surface mount components and related methods involve thin film circuits between first and second insulating substrates. The thin film circuits may include passive components, including resistors, capacitors, inductors, arrays of such components, networks, or filters of multiple passive components. Such thin film circuit(s) can be sandwiched between first and second insulating substrates with internal conductive pads which are exposed to the outside of the surface mount component and electrically connected to external terminations. External terminations may include at least one layer of conductive polymer. Optional shield layers may protect the surface mount components from signal interference. A cover substrate may be formed with a plurality of conductive elements that are designed to generally align with the conductive pads such that conductive element portions are exposed in groups along surfaces of a device.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: August 1, 2017
    Assignee: AVX Corporation
    Inventors: Gheorghe Korony, Andrew P. Ritter
  • Patent number: 9722569
    Abstract: A multi-band, electro-mechanical programmable impedance tuner for the frequency range between 10 and 200 MHz uses cascades of three or more continuously variable mechanical capacitors interconnected with sets of low loss flexible or semi-rigid cables; for each frequency band a different set of cables and capacitors are used. The cables and/or variable capacitors inside each tuning block are switchable manually or remotely. Multi-section variable capacitors are also used. Instantaneous impedance tuning is effectuated by changing the state of the capacitors using electrical stepper motors. The tuner is calibrated using a vector network analyzer and the data are saved in the memory of the control computer, which then allows tuning to any user defined impedance within the tuning range. Reflection factor values between 0 and higher than 0.9 can be obtained using this tuner at all frequency bands.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: August 1, 2017
    Inventor: Christos Tsironis
  • Patent number: 9722570
    Abstract: PROBLEM: To provide a high-performance complex circuit, circuit device, circuit board, and communication device that support a wider band of frequencies. SOLUTION: A complex circuit includes a first diplexer that passes through the normal-phase signals of balanced signals and a second diplexer that passes through the reverse-phase signals of the balanced signals. A balun includes a low frequency band first balun element and a high frequency band second balun element. The first balun element and the second balun element respectively include a plurality of lines that are connected to the first diplexer and that carry signals occupying two different frequency bands and also respectively include a plurality of lines that are connected to the second diplexer and that carry signals occupying two different frequency bands. The lines form one pair of balanced lines, and the lines form another pair of balanced lines. Furthermore, the first balun element and the second balun element each include an unbalanced line.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: August 1, 2017
    Assignee: TAIYO YUDEN CO., LTD.
    Inventor: Toshiyuki Saito
  • Patent number: 9722571
    Abstract: A power combiner includes a planar figure-8 shaped primary winding and a planar figure-8 shaped secondary winding; wherein, the planar figure-8 shaped primary winding is substantially overlaid with the planar figure-8 shaped secondary winding. In addition, there is provided a radio frequency (RF) transmitter having a power combiner, where the power combiner includes a planar figure-8 shaped primary winding and a planar figure-8 shaped secondary winding, wherein the planar figure-8 shaped primary winding is substantially overlaid with the planar figure-8 shaped secondary winding.
    Type: Grant
    Filed: December 25, 2013
    Date of Patent: August 1, 2017
    Assignee: MediaTek, Inc.
    Inventor: Ming-Da Tsai
  • Patent number: 9722572
    Abstract: Embodiments of the invention provide a quartz vibrator, including a long side in a Y? axis direction, a side in the Y? axis direction including a first crystal face and a second crystal face formed thereon, and another side including an AT-cut quartz piece including a first crystal face and a second crystal face formed thereon and electrode layers formed on the AT-cut quartz piece.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: August 1, 2017
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Seung Mo Lim, Ho Phil Jung, Won Han, Dong Joon Oh, Sung Wook Kim, Tae Joon Park
  • Patent number: 9722573
    Abstract: A high-frequency filter including first and second signal terminals, a filter circuit having a passband and a stopband and being connected between the first signal terminal and the second signal terminal, and an additional circuit connected in parallel with the filter circuit between the first signal terminal and the second signal terminal. The filter circuit is configured to provide a first output signal responsive to receipt of an input signal. The additional circuit has an attenuation band within the stopband, and is configured to provide a second output signal responsive to receiving the input signal, the first and second output signals having phase components opposite to each other in the attenuation band.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: August 1, 2017
    Assignee: SKYWORKS FILTER SOLUTIONS JAPAN CO., LTD.
    Inventors: Joji Fujiwara, Toru Jibu, Tomoya Komatsu, Hiroyuki Nakamura, Tetsuya Tsurunari, Kazunori Nishimura
  • Patent number: 9722574
    Abstract: An acoustic wave device is provided with a low-frequency side filter having a low-frequency side passband, a high-frequency side filter having a high-frequency side passband, and first and second balanced terminals. The low-frequency side filter is connected to a first unbalanced terminal. The low-frequency side passband is a frequency band from a first minimum frequency to a first maximum frequency. The high-frequency side filter is connected to a second unbalanced terminal. The high-frequency side passband is a frequency band from a second minimum frequency to a second maximum frequency. The low-frequency side filter includes a first longitudinally-coupled acoustic wave resonator and a first one-terminal pair acoustic wave resonator connected in series to the first longitudinally-coupled acoustic wave resonator. An antiresonant frequency of the first one-terminal pair acoustic wave resonator is set to be higher than the first maximum frequency and lower than the second minimum frequency.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: August 1, 2017
    Assignee: SKYWORKS FILTER SOLUTIONS JAPAN CO., LTD.
    Inventor: Satoru Ikeuchi
  • Patent number: 9722575
    Abstract: A duplexer includes: a transmit filter connected between a transmit terminal and an antenna terminal and including series resonators and parallel resonators connected in a ladder form; and a receive filter connected between a receive terminal and the antenna terminal, wherein at least one of resonators, which are resonators other than a first series resonator and a first parallel resonator located at a first stage as viewed from a side of the transmit terminal and a second series resonator and a second parallel resonator located at a first stage as viewed from a side of the antenna terminal and have electrostatic capacitances less than an electrostatic capacitance of at least one of the first series resonator, the first parallel resonator, the second series resonator, and the second parallel resonator in the series resonators and the parallel resonators, is divided in series.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: August 1, 2017
    Assignee: TAIYO YUDEN CO., LTD.
    Inventor: Noriaki Taniguchi
  • Patent number: 9722576
    Abstract: An elastic wave filter has an unbalanced signal terminal, first and second balanced signal terminals, and first through fifth IDT electrodes arranged in ordinal order between a pair of grating reflectors. Wiring electrodes of the third and fifth IDT electrodes are disposed adjacent a ground electrode of the fourth IDT electrode, wiring electrodes of the second and third IDT electrodes are disposed adjacent one another, and ground electrodes of the first and second IDT electrodes are disposed adjacent one another. The unbalanced signal terminal is connected to the wiring electrodes of the first, third, and fifth IDT electrodes, and the first and second balanced signal terminals are connected to the wiring electrodes of the second and fourth IDT electrodes, respectively.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: August 1, 2017
    Assignee: SKYWORKS FILTER SOLUTIONS JAPAN CO., LTD.
    Inventors: Joji Fujiwara, Tetsuya Tsurunari, Hiroyuki Nakamura, Rei Goto
  • Patent number: 9722577
    Abstract: A system that incorporates teachings of the present disclosure may include, for example, an adaptive impedance matching network having an RF matching network coupled to at least one RF input port and at least one RF output port and comprising one or more controllable variable reactive elements. The RF matching network can be adapted to reduce a level of reflected power transferred from said at least one input port by varying signals applied to said controllable variable reactive elements. The one or more controllable variable reactive elements can be coupled to a circuit adapted to map one or more control signals that are output from a controller to a signal range that is compatible with said one or more controllable variable reactive elements. Additional embodiments are disclosed.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: August 1, 2017
    Assignee: BlackBerry Limited
    Inventor: William E. McKinzie, III
  • Patent number: 9722578
    Abstract: The document relates to modulated sub-sampled digital filter banks, as well as to methods and systems for the design of such filter banks. In particular, the present document proposes a method and apparatus for the improvement of low delay modulated digital filter banks. The method employs modulation of an asymmetric low-pass prototype filter and a new method for optimizing the coefficients of this filter. Further, a specific design for a 64 channel filter bank using a prototype filter length of 640 coefficients and a system delay of 319 samples is given. The method substantially reduces artifacts due to aliasing emerging from independent modifications of subband signals, for example when using a filter bank as a spectral equalizer. The method is preferably implemented in software, running on a standard PC or a digital signal processor (DSP), but can also be hardcoded on a custom chip.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: August 1, 2017
    Assignee: Dolby International AB
    Inventor: Per Ekstrand
  • Patent number: 9722579
    Abstract: A semiconductor device may include: a pre-driving unit suitable for transmitting input data to a first node in response to a first control signal; a main driving unit suitable for outputting the input data transmitted to the first node, using a first voltage as a driving voltage; and a bias control unit suitable for supplying a second voltage to the first node in response to a second control signal, the second voltage having a different level from the first voltage.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: August 1, 2017
    Assignee: SK Hynix Inc.
    Inventor: Jae-Heon Kim
  • Patent number: 9722580
    Abstract: A process information extractor circuit includes: a transistor array including a plurality of transistors, and configured such that, among the plurality of transistors, the number of transistors electrically coupled in series is adjusted depending on a code; a current source suitable for adjusting the amount of current flowing through the transistor array to a predetermined value; a comparator suitable for comparing a gate voltage of the transistors electrically coupled in series in the transistor array, with a reference voltage; and a code generator suitable for generating the code according to a comparison result of the comparator.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: August 1, 2017
    Assignee: SK Hynix Inc.
    Inventor: Jae-Heon Kim
  • Patent number: 9722581
    Abstract: An integrated circuit is provided with an MCU, which is configured to generate a PWM control signal that is free of switching pattern information therein. A current-estimating gate driver is provided, which is responsive to the PWM signal. This gate driver is configured to drive first and second gate terminals of first and second parallel switching devices (within a hybrid switch) with gate signals that establish a second switching pattern within the hybrid switch. These gate driving operations are performed in response to measuring a first voltage associated with a terminal of the hybrid switch when being driven by gate signals that establish a first switching pattern within the hybrid switch that is different from the second switching pattern. The duty cycles of the gate signals associated with the second switching pattern are unequal and the duty cycles of the gate signals associated with the first switching pattern are unequal.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: August 1, 2017
    Assignee: Eaton Corporation
    Inventors: Tiefu Zhao, Jiangbiao He, Yakov Lvovich Familiant, Mengbin Ben Yang
  • Patent number: 9722582
    Abstract: A semiconductor device includes: a pre-emphasis control signal generation block suitable for generating first and second pre-emphasis control signals for controlling a pre-emphasis operation; at least one first output driver suitable for being selectively enabled in response to a selection code signal and driving a pad in response to a first output signal; and at least one second output driver suitable for being selectively enabled in response to the selection code signal and the first pre-emphasis control signal, performing the pre-emphasis operation with a driving force corresponding to a calibration code signal, and performing the pre-emphasis operation with a maximum driving force in response to the second pre-emphasis control signal.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: August 1, 2017
    Assignee: SK Hynix Inc.
    Inventor: Hae-Kang Jung
  • Patent number: 9722583
    Abstract: A semiconductor system may include a first semiconductor device configured to output a command and receive data. The semiconductor system may include a second semiconductor device configured to generate a periodic signal, the periodic signals periodically toggled in response to the command, output the data in response to the periodic signal, and discharge the charges of an internal node if the periodic signal is not toggled during a predetermined section.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: August 1, 2017
    Assignee: SK hynix Inc.
    Inventors: Myeong Jae Park, Kyung Hoon Kim, Woo Yeol Shin, Han Kyu Chi
  • Patent number: 9722584
    Abstract: Provided is a non-volatile latch, which includes a latch circuit, a first switch circuit, a non-volatile memory device, a second switch circuit and a third switch circuit. A first terminal of the first switch circuit is coupled to a first output terminal of the latch circuit. The first switch circuit is turned off in a normal operation period. A first terminal of the non-volatile memory device is coupled to a second terminal of the first switch circuit. A second terminal of the non-volatile memory device is coupled to a programming voltage via the second switch circuit. In a store period, according to latched data of the latch circuit and a state transformation condition of the non-volatile memory device, the third switch circuit can dynamically determine whether to couple the first terminal of the non-volatile memory device to a reference voltage.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: August 1, 2017
    Assignee: National Tsing Hua University
    Inventors: Meng-Fan Chang, Albert Lee, Chieh-Pu Lo, Chien-Chen Lin
  • Patent number: 9722585
    Abstract: A circuit to a extend signal comparison voltage range includes a latching circuit and a comparator responsive to common-mode input signals. The comparator is coupled to the latching circuit and to a dynamic node. The circuit also includes a clocked boost circuit coupled to the dynamic node. The clocked boost circuit is configured to extend a supply voltage range of the comparator via biasing the dynamic node. A method to extend a signal comparison voltage range includes selectively shifting a voltage level of one of a ground reference of a dynamic circuit or a supply reference of the dynamic circuit in response to a clock signal.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: August 1, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Jeremy Goldblatt
  • Patent number: 9722587
    Abstract: A power supply circuit has, for example, an overshoot suppressor 100, a control circuit 10, a first transistor M1, a second transistor M2, an inductor L, a capacitor C1, resistors R1 and R2, and an error amplifier ERR. As the load becomes light, the ON-period of the second transistor M2 increases. When the load RL turns from a heavy load to a light or no load, the overshoot suppressor 100 detects an increase in the ON-period of the second transistor M2, and then forcibly turns OFF the second transistor M2. Thus, an overshoot in the output voltage Vo is suppressed. Detecting an increase in the period for which the driving signal S2remains at high level H helps reduce malfunctioning due to noise.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: August 1, 2017
    Assignee: Rohm Co., Ltd.
    Inventor: Keisuke Tsutsumi
  • Patent number: 9722588
    Abstract: Apparatuses for monitoring a signal on a conductive via are described. An example apparatus includes: a controller, a first conductive via, a second conductive via and an evaluation circuit. The controller provides a clock signal as a first signal. The first conductive via provides a second signal responsive to the first signal. The second conductive via provides a third signal responsive to the second signal. Responsive to the third signal, the evaluation circuit provides an evaluation result signal. The evaluation result signal is indicative of a frequency of the clock signal, based on a delay of the third signal relative to the clock signal. The first conductive via, the second conductive via and the evaluation circuit may be included in an interface die. The evaluation circuit may detect whether a frequency of the first signal is below a first threshold frequency and may further provide the evaluation result signal.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: August 1, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Tomoyuki Shibata, Minehiko Uehara
  • Patent number: 9722589
    Abstract: A superconducting integrated circuit including a clock distribution network for distributing a clock signal in the superconducting integrated circuit is provided. The clock distribution network may include a clock structure having unit cells, where each of the unit cells may include at least one spine and at least one stub. The clock structure may further include at least one spine connected to the at least one stub, where the at least one stub may further be inductively coupled to at least one superconducting element. The clock signal may have a wavelength. Each of the unit cells may be spaced apart from each other along the clock structure by a distance, where the distance may be less than one tenth of the wavelength.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: August 1, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Vladimir V. Talanov, Joshua A. Strong
  • Patent number: 9722590
    Abstract: A skew adjustment circuit includes: flip flop circuits for taking in an input signal in response to first clock signals; a clock phase adjustment circuit for adjusting phases of second clock signals, based on the second clock signals generated based on a reference clock signal and an output signal from the flip flop circuits; a phase interval detection circuit for detecting a phase interval between the first clock signals, based on a reference value; and a phase interval adjustment circuit for performing adjustment such that phase intervals become equal to each other between the second clock signals adjusted by the clock phase adjustment circuit, based on a skew adjustment signal from the phase interval detection circuit. The reference value is obtained by calibration, and the second clock signals adjusted by the phase interval adjustment circuit are provided as the first clock signals to the flip flop circuits.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: August 1, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Tatsunori Usugi, Kouzaburou Kurita, Takemasa Komori, Junya Nasu
  • Patent number: 9722591
    Abstract: A phase adjustment device includes: a detection signal generator configured to generate a pair of first and second detection signals for detecting a phase difference between two signals whose phases have been adjusted by two phase adjusters, respectively, a maximum sensitivity phase difference of one of the first and second detection signals being not overlap with that of the other, and detection sensitivity of the phase difference becoming maximum at the maximum sensitivity phase difference; a detection signal selector configured to select one of the first and second detection signals whose predetermined range around the maximum sensitivity phase difference covers a preset phase difference; and a phase controller configured to control an amount of phase-adjusting by at least one of the two phase adjusters based on a difference between the phase difference detected within the predetermined range using the selected detection signal and the preset phase difference.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: August 1, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Toshihiro Shimura
  • Patent number: 9722592
    Abstract: A semiconductor integrated circuit device includes a first voltage terminal, a second voltage terminal, an output terminal, a high-side MOSFET connected between the first voltage terminal and the output terminal, a low-side MOSFET connected between the output terminal and the second voltage terminal and having first and second gate electrodes, a drive circuit that complementally switches on and off the high-side MOSFET and low-side MOSFET, and a second gate electrode control circuit that generates a second gate control signal supplied to the second gate electrode of the low-side MOSFET. The second gate electrode control circuit has a voltage generating circuit that supplies a negative voltage negative in polarity relative to a voltage at the source of the low-side MOSFET, to the second gate electrode of the low-side MOSFET.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: August 1, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Daisuke Kondo, Koji Tateno, Yumi Kishita, Tomoaki Uno
  • Patent number: 9722593
    Abstract: In High Voltage CMOS technologies the supply voltage is typically higher than the maximum allowed gate voltage. In a switching output stage of amplifiers such class-D amplifiers and DC-DC converters the gates of the power field effect transistors need to be charged quickly. This requires a gate driver that is capable of delivering large currents without exceeding the maximum allowed voltage on the gate of the power field effect transistors.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: August 1, 2017
    Assignee: NXP B.V.
    Inventors: Marco Berkhout, Paulus Petrus Franciscus Maria Bruin
  • Patent number: 9722594
    Abstract: A drive device includes an off-side circuit controlling a gate current of a power switching element to perform an off operation. The off-side circuit includes: a main MOS transistor; a sense MOS transistor defining a drain current of the main MOS transistor; and a sense current control circuit controlling a drain current of the sense MOS transistor to be constant. The sense current control circuit includes: a reference power supply; a reference resistor; and an operational amplifier generating an output at the gate of the sense MOS transistor so that a potential between the reference resistor and the sense MOS transistor approaches the reference potential. The sense current control circuit flows a current, determined by a resistance value of the reference resistor and the reference potential, as the drain current of the sense MOS transistor.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: August 1, 2017
    Assignee: DENSO CORPORATION
    Inventor: Takuo Nagase
  • Patent number: 9722595
    Abstract: A system includes a SiC semiconductor power device; a power supply board that is configured to provide power to a first gate driver board via a connector; the first gate driver board that is coupled and configured to provide current to the SiC semiconductor power device, wherein the first gate driver board is coupled to the power supply board via the connector, and wherein the first gate driver board is separated from the power supply board; and an interconnect board that is coupled to the first gate driver board, wherein the interconnect board is configured to couple the first gate driver board a second gate driver board.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: August 1, 2017
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Fengfeng Tao, Michael Joseph Schutten, Jeffrey Joseph Nasadoski, Maja Harfman-Todorovic, John Stanley Glaser
  • Patent number: 9722596
    Abstract: A high-voltage electronic switch includes first and second transistors defining a current flow path between an input and output of the switch. The transistors have a common point of the current flow path and a common control terminal. A control circuit includes a voltage line receiving a limit operating voltage and first and second branches coupled between the voltage line and the common point and common control terminal, respectively. Further transistors are activated, upon turning-off of the first and second transistors, for coupling the branches to the voltage line. The branches include a parallel connected resistor, diode, and string of diodes with opposite polarities. The diode of the first branch plus string of diodes of the second branch and diode of the second branch plus string of diodes of the first branch provide coupling paths between the voltage line and, respectively, the common point and common control terminal.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: August 1, 2017
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Marco Terenzi, Davide Ugo Ghisu
  • Patent number: 9722597
    Abstract: An initialization signal generation device may be provided. The initialization signal generation device may include a power supply circuit configured to provide one of an external voltage and an internal voltage in response to an initialization signal. The initialization signal generation device may include an initialization signal generator configured to sense the level of the voltage outputted from the power supply circuit and generate the initialization signal.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: August 1, 2017
    Assignee: SK hynix Inc.
    Inventor: Hyun Chul Lee
  • Patent number: 9722598
    Abstract: A semiconductor device, according to one possible configuration, includes switching circuits, each switching circuit comprising IGBT chips connected in series and clamping diodes. The semiconductor device also includes a first and a second wiring line and auxiliary emitter lines. The first wiring line and a first auxiliary emitter line connect the emitter terminals of IGBT chips of the first and second switching circuits. The second wiring line and another auxiliary emitter line connect the emitter terminals of the third IGBT chips of the first and second switching circuits. The wiring lines have a large current carrying capacity and a lower resistance value than their respectively connected auxiliary emitter line.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: August 1, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hiroaki Ichikawa
  • Patent number: 9722599
    Abstract: In accordance with an embodiment, a circuit includes a first and a second switching transistors configured to be coupled in series between a first reference voltage terminal and a transformer. The circuit also includes a first diode coupled between a first drain of the first switching transistor and a first input terminal. The first diode is configured to clamp a voltage of the first drain to a voltage of the first input terminal. The circuit further includes a switching circuit coupled between the second switching transistor and the first input terminal. The switching circuit is configured to connect a second source of the second switching transistor to a second gate of the second switching transistor when a voltage of the second source exceeds the voltage of the first input terminal.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: August 1, 2017
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Mladen Ivankovic, Fred Sawyer
  • Patent number: 9722600
    Abstract: In some embodiments, a driving circuit of a switching device for an electric power control capable of improving reliability of an ON/OFF driving and a monitoring operation of a switching device by configuring a configuration for the ON/OFF driving and the monitoring operation of the switching device in plural numbers is presented. A driving circuit of a switching device for an electric power control may include a driver circuit unit, a first logic device, a second logic device, and a controller.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: August 1, 2017
    Assignee: LSIS CO., LTD.
    Inventors: Sung-Hee Kang, Kyoung-Hun Nam
  • Patent number: 9722601
    Abstract: A gate driving circuit for turning on a high-side transistor when an input set pulse is asserted and turning off the high-side transistor when an input reset pulse is asserted is provided. The gate driving circuit includes first and second inverters to receive the intermediate set pulse from a level shift circuit to generate first and second set pulses; third and fourth inverters to receive the intermediate reset pulse from the level shift circuit to generate first and second reset pulses; a logic circuit to mask the first set pulse and the first reset pulse by using the second reset pulse and the second set pulse to generate an output set pulse and an output reset pulse, respectively; a flip-flop configured to receive the output set pulse and the output reset pulse to output a driving pulse; and a driver to drive the high-side transistor according to the driving pulse.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: August 1, 2017
    Assignee: ROHM CO., LTD.
    Inventors: Hiroki Niikura, Takafumi Morinaka
  • Patent number: 9722602
    Abstract: A transmitter includes: a main pull-up driver suitable for pull-up driving an output node; and an auxiliary pull-up driver suitable for pull-up driving the output node based on a voltage of the output node, wherein the auxiliary pull-up driver compensates for non-linear driving current characteristics of the main pull-up driver.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: August 1, 2017
    Assignee: SK Hynix Inc.
    Inventor: Jae-Heon Kim
  • Patent number: 9722603
    Abstract: The switch housing for capacitive switches has an outer contact surface and flat electrode structures which are arranged on the inside and in a position opposite the contact surface and which are placed by two-component injection molding in recessed regions of the housing body injected from a first, electrically non-conductive plastic component by a second, electrically conductive plastic component. Preferably, both plastic components are a polycarbonate, the second plastic component containing carbon fibers.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: August 1, 2017
    Assignee: TRW Automotive Electronics & Components GmbH
    Inventor: Udo Koberstein