Abstract: In one example, a current-mode logic (CML) circuit includes a differential transistor pair having a differential input port configured to receive a differential input voltage, a bias port configured for coupling to a current source, and a differential output port. The CML circuit further includes a load circuit coupled to the differential output port. The load circuit includes an active inductive load, a cross-coupled transistor pair, and a switch coupled between the cross-coupled transistor pair and the differential output.

Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

Abstract: Described is an apparatus which comprises: a clamp coupled between a first power supply and a second power supply, the clamp including a plurality of transistors, a circuit to operate with the second power supply; and a control unit to turn on and off the plurality of transistors to adjust the second power supply when the apparatus enters a low power mode. The control unit includes a first comparator to compare the second power supply with a first reference, a second comparator to compare the second power supply with a second reference, and a counter. The counter counts up when the second power supply is higher than the first reference and counts down when the second power supply is lower than the second reference.

Abstract: A voltage level shifter includes: in stages a pull-down driving unit suitable for receiving an input signal swinging between a ground voltage and a first supply voltage, and pull-down driving an output node to the ground voltage according to a voltage level of the input signal, wherein an output signal outputted through the output node swings between the ground voltage level and a second supply voltage level higher than the first supply voltage; a pull-up driving unit suitable for pull-up driving the output node, to the second supply voltage according to the voltage level of the input signal; a bias generation unit suitable for generating a bias voltage fixed to a preset voltage level; and a bias operation unit coupled between the output node and the pull-down driving unit, and suitable for lowering a voltage level of the output node in stages based on the bias voltage to supply the lowered voltage to the pull-down driving unit when a pull-down operation is performed by the pull-down driving unit.

Abstract: Various systems may benefit from interfaces for handling multiple types of inputs. For example, a device with a trigger input from an external device may benefit from an isolated logic level trigger that is capable of addressing multiple types and values of voltage. An apparatus can include an input configured to receive an external trigger input signal having a trigger input voltage. The apparatus can also include circuitry configured to automatically adjust the trigger input voltage to a value configured to be compatible with a provided attached system. A working range of the trigger input voltage can exceed a compatible working range of the provided attached system.

Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.

Abstract: Aspects of the invention can include a pulse generating means that outputs a set signal and reset signal for driving the high potential side switching element is such that, while either one of the set signal or reset signal is in an on-state as a main pulse signal for putting the high potential side switching element into a conductive state or non-conductive state, the other signal is turned on a certain time after the rise of the main pulse signal, thereby generating a condition in which the set signal and reset signal are both in an on-state.

Abstract: A semiconductor circuit includes a first circuit and a second circuit. The first circuit is configured to generate a voltage level at a first node based on a voltage level of input data, an inverted value of the voltage level at the first node, a voltage level of a clock signal, and a voltage level at a second node; and the second circuit is configured to generate the voltage level at the second node based on the voltage level of input data, an inverted value of the voltage level at the second node, the voltage level of the clock signal, and the inverted value of the voltage level at the first node. When the clock signal is at a first level, the first and second nodes have different logical levels. When the clock signal is at a second level, the first and second nodes have the same logical level.

Abstract: Techniques are provided to permit a programmable logic device (PLD) to comply with a communication standard before the PLD is fully configured. In one example, a method includes programming a first portion of a programmable logic device (PLD) with first configuration data. After the first portion is programmed, the first portion is operated in accordance with a communication standard to exchange data with a host system while a second portion of the PLD is programmed with second configuration data.

Abstract: A circuit arrangement for enabling a partial reconfiguration of a circuit implemented in an integrated circuit device is described. The circuit arrangement comprises a plurality of circuit blocks, wherein each circuit block is configurable to implement a predetermined function and comprises a control circuit configured to receive a global enable signal and a plurality of global reconfiguration signals; and a routing network coupled to the plurality of circuit blocks for routing the global enable signal and the plurality of global reconfiguration signals to each circuit block of the plurality of circuit blocks; wherein each circuit block of the plurality of circuit blocks is configured to independently receive a local enable signal enabling a partial reconfiguration of the circuit in response to the plurality of global reconfiguration signals.

Abstract: A reconfigurable logic array(RLA) uses pipeline control methods. A do-not-end step signal is communicated to a controller in response to a backpressure condition. In response, a program executing in the RLA is suspended. Source and sink elements are arranged with respective sensors that identify back pressure conditions at interfaces. The source or sink elements communicate a do-not-end step signal to the controller. Local memory interfaces and an interrupt buffer generate similar signals in response to other internal and external conditions. The controller coordinates pipelined control signals with a global counter that issues the control signals with an end-of-step signal broadcast throughout the RLA. When a number of loop iterations is known before execution of the loop instructions, the information is shared with source and sink elements and the controller, which operate accordingly in a limited mode. At appropriate times write-enable inputs of configuration registers are disabled.

Abstract: In a multi-context PLD (dynamically reconfigurable circuit), at the time of rewriting configuration data on a non-selected context during circuit operation, configuration data is stably stored. At the time of rewriting configuration data on a non-selected context, writing to a row which is to be rewritten continues until input signals supplied to input terminals of routing switches in the row become “L” all that time or the input signals become “L” at least once. More specifically, a write selection signal for the row continues to be output. In addition, while the write selection signal is being output, loading of configuration data into a driver circuit is not conducted, or loading of configuration data into a driver circuit is conducted but storage thereof in a line buffer is not conducted.

Abstract: A determination circuit receives an input data signal and determines a value of the input data signal when a logic level of a sampling clock changes. A sampling clock generation circuit generates the sampling clock on the basis of the input data signal, generates a frequency adjustment value on the basis of the frequency difference between the sampling clock and the input data signal, and adjusts the frequency of the sampling clock on the basis of the frequency adjustment value. A frequency pull-in control circuit performs integration on frequency adjustment values and obtains an integral value in an individual time period. When the integral value reaches a threshold before a single time period elapses, the frequency pull-in control circuit outputs a reset signal that causes the sampling clock generation circuit to output an initial value of the frequency adjustment value until the time period elapses.

Abstract: A phase locked loop (PLL) includes a controllable oscillator, a charge pump, a type II loop filter, a frequency divider and a phase error processing circuit. The controllable oscillator generates an oscillating signal. The charge pump circuit receives a calibration signal and generates a charge pump output according to the calibration signal when the PLL operates in a calibration mode. The type II loop filter receives the charge pump output, and generates a first control signal to the controllable oscillator according to the charge pump output. The frequency divider receives the oscillating signal and an adjusting signal, and refers to the adjusting signal to perform frequency division upon the oscillating signal for generating a feedback signal. The phase error processing circuit receives the feedback signal and a reference signal, and outputs the adjusting signal based on a comparison result of the reference signal and the feedback signal.

Abstract: Systems and methods involving phase-locked-loop (PLL) circuitry are disclosed. In one illustrative implementation, a PLL circuit device may comprise voltage controlled oscillator (VCO) circuitry having a bias signal that sets a frequency range, circuitry that shifts the VCO circuitry to operate in one of the frequency ranges, and other circuitry to compare/calibrate signals and/or set the bias current. According to further implementations, as a function of operation of the circuitry, an operating frequency range of the VCO circuitry may be shifted to a different operating frequency range, and closed-loop, continuous frequency range, auto-calibration or other features may be provided.

Abstract: A frequency synthesis device, including: a first generator configured to generate a periodical signal with a frequency f1; a second generator, coupled to the first generator and generating from the signal with a frequency f1 a signal SG corresponding to a train of oscillations with a frequency substantially equal to N·f1, with a duration lower than T1=1/f1 and periodically repeated at the frequency f1; a third generator generating, from the signal SG, m periodical signals SLO_CH1 to SLO_CHm with frequency spectra each include a main line with a frequency fLO_CHi corresponding to an integer multiple of f1, with 1?i?m, the third generator operating as a band-pass filter applied to the signal SG and discarding from the frequency spectra of each of the periodical signals SLO_CH1 to SLO_CHm lines other than the main line with a frequency fLO_CHi.

Abstract: The overall performance of a dual-path ADC system may be improved by using a VCO-based ADC for small-amplitude signals and employing non-linear cancelation to remove nonlinearities in signals output by the VCO-based ADC. In particular, VCO-based dual-path ADC systems of this disclosure may be configured to receive a first digital signal from a first ADC and a second digital signal from a second ADC, wherein the second digital signal is more non-linear than the first digital signal. The dual-path systems may also be configured to determine one or more non-linear coefficients of the second digital signal based, at least in part, on processing of the first and second digital signals. The dual-path systems may be further configured to modify the second digital signal based, at least in part, on the determined one or more non-linear coefficients to generate a more linear second digital signal.

Abstract: The present invention is directed integrated circuits and methods thereof. More specifically, an embodiment of the present invention provides a comparator calibration loop where a digital integrator stores a running sum based on the output of a comparator. A DAC converts the running sum and generates an offset calibration voltage, which is filtered by a low-pass filter module, and the filtered offset calibration voltage is used to cancel out the intrinsic offset voltage and low frequency noise of the comparator. There are other embodiments as well.

Abstract: The disclosure provides a capacitor array. The capacitor array includes one or more first metal plates vertically stacked parallel to each other. A second metal plate is horizontally stacked to couple one end of each first metal plate of the one or more first metal plates. One or more third metal plates are vertically stacked parallel to the one or more first metal plates. Each third metal plate of the one or more third metal plates is stacked between two first metal plates.

Abstract: An embodiment ADC device includes a plurality of comparator elements, each comparator element of the plurality of comparator elements having a first input connected to an input port, each comparator element of the plurality of comparator elements having a second input port connected to a reference signal port. The ADC device further has a switch matrix having routing circuitry connected to an output of each comparator of the plurality of comparators, and a plurality of latches, with each latch of the plurality of latches having an input connected to the routing circuitry. The routing circuitry is configured to connect the output of each comparator of the plurality of comparators to an input of each latch of the plurality of latches according to one or more signals received at one or more control ports.

Abstract: A semiconductor device and operating method thereof are provided.

Abstract: A semiconductor device includes an analog-digital converter circuit. The analog-digital converter circuit includes a delay cell array that includes n-number (n is a natural number of 2 or more) of serially-coupled delay cells, receives a reference clock signal, and utilizes an analog input signal as the power supply voltage for delay cells in each stage, and an encoder that encodes the output signal of the delay cells in each stage of the delay cell array. The n number of delay cells include a delay quantity weighted for each delay cell, and the encoder encodes the output signal of the delay cell in each stage of the delay cell array by weighting corresponding to the number of delay cell stages. The delay cells output signal without changing polarity of inputted signals.

Abstract: An analog-to-digital converter (ADC) is provided includes a first sigma-delta modulator (SDM) electrically coupled to a first signal input. The first SDM includes a first summing junction configured to receive a plurality of inputs to the first SDM. The ADC further includes a second sigma-delta modulator (SDM) electrically coupled to a second signal input. The second SDM includes a second summing junction configured to receive a plurality of inputs to the second SDM. The first SDM also includes a cross-coupled feedback loop from an output of the first SDM to a negative input of the first summing junction and to a positive input of the second summing junction. The second SDM also includes a cross-coupled feedback loop from an output of the second SDM to a negative input of the first summing junction and to a negative input of the second summing junction.

Abstract: A method for determining an encoding used for a sequence of bytes may be provided. The method comprises providing a set of candidate code pages and transforming them into different groups of sequences of bytes, wherein each group of sequences of bytes corresponds to one of the candidate code pages. Thereby each code point is transformed by applying a transformation from one of the candidate code pages to a reference code point value relating to a reference encoding for each code point. The method comprises further separating each of the transformed sequences of bytes into groups of tokens, wherein each group of tokens relates to one candidate code page, and providing an index relating to a text corpus. Furthermore, the method comprises selecting a code page from the set of candidate code pages at least partially based on how many tokens are found in the index.

Abstract: In a method in a computer system for recoding a coded intermediate variable into a recoded result variable a product is formed by multiplying an input constant by an input variable to be coded. The coded intermediate variable is formed as a function of the product and a multiplicative inverse is determined on the basis of the input constant. The multiplicative inverse is applied to the coded intermediate variable, so that no uncoded or partially uncoded interim result is produced and/or an error information potentially contained in the coded intermediate variable is still detectable in the interim result.

Abstract: Apparatus and methods for conversion from floating point to signed integer representation are provided. Two's complementation and determination of a shift control signal indicating the number of bit positions for shifting the two's complemented mantissa to produce the signed integer are performed in parallel. Generation of the shift control signal, including application of an optional scaling factor, is performed using an adder, with the most significant bit of input floating point exponent inverted and an external carry-in of one. Two's complementation for generation of the signed integer from the mantissa is performed using an adder. Certain aspects may be utilized for purposes other than format conversion. The two's complementation may be used for general conversion from unsigned to signed integer format or from signed to unsigned integer format.

Abstract: The method for decoding a serially transmitted signal including: sampling the serially transmitted signal to obtain a plurality of sampled values according to a sampling period; obtaining a period of the serially transmitted signal according to a transition status of the sampled values; calculating a plurality of phase values according to the period and the transition status of the sampled values; obtaining a plurality of boundaries according to the phase values; and outputting a decoded data according to the boundaries and the transition status.

Abstract: A method and an apparatus for calculating an estimated data compression ratio relate to the field of data processing technologies. In the solutions, an estimated data compression ratio is calculated using a related indicator that represents a distribution pattern of symbols in a symbol sequence, where the related indicator that represents the distribution pattern of the symbols in the symbol sequence is relatively closely related to the estimated data compression ratio.

Abstract: A system for hardware error-correcting code (ECC) detection or correction of a received codeword from an original codeword includes an error-detecting circuit configured to process a selection of symbols of the received codeword using a set of factors, the original codeword being recomputable from a corresponding said selection of symbols of the original codeword using the set of factors. The error-detecting circuit includes a hardware multiplier and accumulator configured to use the set of factors and the selection of symbols of the received codeword to recompute remaining symbols of the original codeword, and a hardware comparator configured to compare the recomputed remaining symbols of the original codeword with corresponding said remaining symbols of the received codeword and to output first results of this comparison.

Abstract: In an advanced adaptive modulation and coding (AMC) scheme, the code rate and the parity-check matrix (PCM) for low-density parity-check (LDPC) codes are adapted according to modulation formats and variable-iteration receivers. The degree distribution for the PCM adaptation is designed by heuristic optimization to minimize the required SNR via an extrinsic information transfer (EXIT) trajectory analysis for finite-iteration decoding. The method uses dynamic window decoding by generating spatially coupled PCM for quasi-cyclic LDPC convolutional coding. The method also provides a way to jointly optimize labeling and decoding complexity for high-order and high-dimensional modulations.

Abstract: Systems and methods for data transport, including encoding streams of input data using generalized low-density parity check (GLDPC) encoders, the one or more GLDPC encoders being configured to generate GLDPC coded data streams using a plurality of component local codes to improve error correction strength, employ single-parity checks and two or more local block codes during generation of the GLDPC codes, and enable continuous tuning of code rate using the generated GLDPC codes. Signals may be generated using mappers, the mappers configured to assign bits of signals to signal constellations and to associate the bits of the signals with signal constellation points. The signal may be modulated using an I/Q or 4-D modulator composed of one polarization beam splitter, two I/Q modulators, and one polarization beam combiner. The modulated signals are multiplexed using a mode-multiplexer, transmitted over a transmission medium, and the signals are received and decoded using GLDPC decoders.

Abstract: A controller for a solid state drive is proposed. The solid state drive comprises memory cells each one for storing a symbol among a plurality of possible symbols that the memory cell is designed to store. The controller comprises a unit for encoding information bits into encoded bits; a unit for mapping the encoded bits into the symbols, wherein the symbols are determined based on a plurality of allowed symbols, among the possible symbols, that the memory cells are allowed to store, whereas the symbols, among the possible symbols, other than the allowed symbols define forbidden symbols not allowed to be stored in the memory cells; a unit for demapping read symbols and for providing an indication of the reliability of the read symbols based on the forbidden symbols; and a unit for soft decoding the read symbols according to the reliability indication thereby obtaining the information bits.

Abstract: An arrangement for decoding a data word using a Reed-Muller code, has: (1) N input terminals, (2) a first level of E>>D summing modules, each summing module being linked with F different input terminals and each input terminal being linked with E summing modules, (3) a first level of E decision modules, each of the D inputs of each decision module being linked respectively with an output from D different summing modules, (4) a second level of H summing modules, (5) a second level of G decision modules, (6) a third level of G summing modules, and (7) G output terminals. N signifies the code length and D signifies the minimum spacing of the code, E is equal to D-2, F is equal to N/D, G is the number of symbols of the data word that need to be corrected and is a natural number between 1 and E<<D.

Abstract: This invention gives a coding method of MBR (Minimum Bandwidth Regenerating) codes. The related method includes the following steps: equally divide the original file of size B into k(k+1)/2 blocks, obtaining the first packets; construct a symmetrical k×k system matrix S with these first packets; generate k ID codes, wherein each ID code contains k elements; obtain the coded packet through operations between one column of the system matrix and the ID code; repeat the above steps with (n?k) different columns of the system matrix separately to get the (n?k) coded packets; construct the (n?k)×k check matrix P with the column number g which is the serial number of the ID codes in the coded packet set Pg; store the rows of the system matrix and coded matrix to n nodes, each node stores one row. The present invention also involves a method to repair the failed nodes of the above coding scheme.

Abstract: A cellular radio architecture for a vehicle that includes a triplexer coupled to an antenna structure and including three signal paths, where each signal path includes a bandpass filter that passes a different frequency band than the other bandpass filters and a circulator that provides signal isolation between the transmit signals and the receive signals. The architecture also includes a receiver module having a separate signal channel for each of the signal paths in the triplexer, where each signal channel in the receiver module includes a receiver delta-sigma modulator that converts analog receive signals to a representative digital signal. The delta-sigma modulator includes an LC filter having a plurality of LC resonator circuits, a plurality of transconductance amplifiers and a plurality of integrator circuits, where a combination of one resonator circuit, transconductance amplifier and integrator circuit represents a two-order stage of the LC filter.

Abstract: Front end circuitry for a wireless communication system includes a first antenna node, a second antenna node, a first triplexer, a second triplexer, and front end switching circuitry coupled between the first triplexer, the second triplexer, the first antenna node, and the second antenna node. The front end switching circuitry is configured to selectively couple the first triplexer to one of the first antenna node and the second antenna node and couple the second triplexer to a different one of the first antenna node and the second antenna node. By using a first triplexer and a second triplexer in the mobile front end circuitry, the mobile front end circuitry may operate in one or more carrier aggregation configurations while reducing the maximum load presented to the first antenna node and the second antenna node, thereby improving the performance of the front end circuitry.

Abstract: A method and system for determining position and/or pose of an object. A robotic device moves throughout an environment and includes a master transceiver tag and, optionally, additional tags. The environment includes a plurality of anchor nodes that are configured to form a network. A master anchor node is in communication with at least a portion of the plurality of anchor nodes and is configured to transmit a ranging message as a UWB signal, receive a ranging message response from each other anchor node in the network, generate a reference grid representing physical locations of the plurality of anchor nodes within the network based upon the received ranging message responses, and distribute the reference grid to each of the other anchor nodes. The master transceiver tag receives the reference grid information and, based upon further calculations, determines a specific position and pose of the robotic device within the environment.

Abstract: A semiconductor device (10) includes a transmitting circuit (12) that converts transmission data into a transmission signal with a specified frequency, an amplifier (13) that amplifies a power of the transmission signal, a matching circuit (14) that converts the transmission signal from a balanced signal to an unbalanced signal, and a filter circuit (14) that restricts a frequency band of the transmission signal. The matching circuit includes a primary inductor and a secondary indictor, the filter circuit includes an inductor for a filter, and the primary inductor, the secondary indictor and the inductor for a filter are wound substantially concentrically on one plane.

Abstract: A controller can include a signal generator configured to provide an input signal to a modulator. The controller can be configured to generate a modulator compensation parameter in response to a modulated feedback signal corresponding to an output of the modulator. The controller can also be configured to generate a power amplifier predistortion signal in response to an amplified feedback signal corresponding to an output of a power amplifier coupled to the modulator.

Abstract: Embodiments relate to enhancing echo cancellation in a transceiver integrated circuit (IC) for full-duplex communication by providing a signal path connected to a dummy driver that replicates a signal path between a main driver and a counterpart transceiver IC to cause a duplicated signal generated by the dummy driver to more closely replicate a sending signal generated by the main driver. The signal path connected to the dummy driver includes circuit elements having transmission line parameters and RLC parameters that replicate transmission line parameters and RLC parameters of circuit elements in the signal path between the main driver and the counterpart transceiver IC.

Abstract: Appropriate signal processing may be beneficial in a variety of communication systems and elements thereof. For example, time domain digital pre-distortion may benefit from suitable treatment of frequency switching. A method can include determining whether an instantaneous frequency of an input signal is positive or negative. The method can also include selecting a pre-distortion model from a set of pre-distortion models based on the determination of positive or negative instantaneous frequency. The method can further include applying the selected pre-distortion model to the input signal for a time corresponding to the determination of instantaneous frequency to provide an output signal. The method can additionally include providing the output signal to a power amplifier.

Abstract: An apparatus for generating a transmit signal includes an up-conversion module and a delay module. The up-conversion module up-converts a first component signal of a multi-phase baseband transmit signal using a first oscillator signal and up-converts a delayed second component signal of the multi-phase baseband transmit signal using a second oscillator signal to generate a radio frequency transmit signal. The first oscillator signal and the second oscillator signal comprise an oscillator signal phase offset so that an edge of the second oscillator signal occurs earlier than a corresponding edge of the first oscillator signal. The delay module delays a second component signal of the multi-phase baseband transmit signal relative to the first component signal of the multi-phase baseband transmit signal by a predefined component signal delay to generate the delayed second component signal of the multi-phase baseband transmit signal.

Abstract: A RF communication system includes a radio transmitter comprising an RF power amplifier, the RF power amplifier including an input to receive an RF signal for transmission and being configured to amplify the RF signal for transmission across a communication channel; a RF digital pre- or post-distortion configured to compensate for nonlinearity of the RF communication system by operating on the RF signal entering or exiting the amplifier.

Abstract: A cellular radio architecture that includes a transceiver front-end circuit including an antenna and a switch module having a switching network that directs analog transmit signals to be transmitted to the antenna and receives receive signals from the antenna. The architecture further includes a receiver module having a separate signal channel for each of the signal paths in the multiplexer module, where each signal channel in the receiver module includes a receiver delta-sigma modulator that converts analog receive signals to a representative digital signal. The architecture also includes a transmitter module having a transmitter delta-sigma modulator for converting digital data bits to the transmit signals. The transmitter module includes a tunable bandpass filter and a power amplifier for amplifying the transmit signals before transmitting. The architecture also includes a calibration feedback and switch module that receives the amplified signals from the power amplifier.

Abstract: An integrated circuit comprises a frequency detector. The frequency detector comprises a timer state machine unit operably couplable to a timer and arranged to receive an incoming carrier signal; determine whether the incoming carrier signal comprises a valid frequency; generate a valid carrier indication when the incoming carrier signal is determined as having a valid frequency; and adjust the timer between at least a first timing mode of operation and a second timing mode of operation of the frequency detector in response to the determination.

Abstract: In some embodiments, techniques are provided for extending the functionality of a receiving unit which is configured to express a state during an event. In some embodiments, a receiving unit configured to receive a first set of transmissions during an event from one or more transmitting units and express a state in response may also be configured to receive a second set of transmissions from other components at a time other than during the event and express a state in response to receiving the second set of transmissions.

Abstract: Described herein are technologies related to an implementation of noise power estimation in a receiver of a device.

Abstract: Methods, systems, and devices are described for wireless communications at a wireless device. A wireless device may adaptively select a parity check matrix to increase the reliability of signal transmission by adapting to different channel statistics and channel types (e.g., erasure channels, channels with additive white Gaussian noise, and channels with discrete or continuous alphabets). For example, polarization codes (i.e., codes based on rows of a polarization matrix) may be used to construct parity check matrices “on-the-fly” given an estimation of dynamic channel conditions or diverse channel structures. The channel may be decomposed into polarized sub-channels corresponding to the polarization codes, and mutual information profiles may be determined for each of the polarized sub-channels. The parity check matrix corresponding to the polarization codes may be constructed based on the mutual information profile of all polarized sub-channels.

Abstract: A mobile apparatus includes a touch screen and a controller. The controller estimates that the mobile apparatus is being immersed in water when a detection result of the touch screen satisfies a predetermined condition.

Abstract: A memory card adapter includes a body having a set of contact pins. The set of contact pins include input pins and output pins implemented in a pin-to-pin structure. The input pins connect with pins of an inserted memory card and the output pins connect with an external socket. The body includes a bottom lead adapted to support the main body, and a top lead adapted to be combined with the bottom lead. The body includes a fixing substance adapted to combine with the contact pins. The body includes a conduction plate on a top surface or a bottom surface of the fixing substance, where the conduction plate is connected to at least one of the contact pins.