Abstract: A system for monitoring of integrity of a communication bus includes a communication bus cooperating with at least one transmitter configured to generate and transmit a signal on communication bus. At least one receiver is configured to receive a signal generated by the transmitter and transmitted on communication bus. The receiver is further configured to receive the transmitted signal as well as any reflected signals arising from non-impedance matched section in communication bus and wherein a time difference between transmitted pulse width and received pulse width indicates a distance between the non-impedance matched section and the transmitter on the communication bus.

Abstract: Apparatus and method for accelerated testing of a multi-device storage system. In some embodiments, the storage system includes a server adapted to communicate with a user device, and a plurality of data storage devices adapted to store and retrieve data objects from the user device. The server maintains a map structure that describes the data objects stored on the data storage devices. A fault injection module is adapted to induce simulated failures of selected data storage devices in relation to a time-varying failure rate distribution associated with the data storage devices that indicates an observed failure rate over a first time interval. The simulated failures are induced by the fault injection module over a second time interval shorter than the first time interval. The server operates to modify the map structure responsive to the simulated failures.

Abstract: In a diagnosis method of a control valve, position data representing a position of a control valve, and pressure data representing a pressure difference over a valve actuator, and optionally travel direction of the control valve, is measured during online operation of the control valve. The position data and the pressure difference data are processed to contain data around starting points of a plurality of individual travel movements of the control valve during normal online operation of the control valve. Finally, a valve signature graph of the control valve is determined based on the processed position and pressure difference data, collected at a plurality of points along the travel range of the control valve during online operation of the control valve.

Abstract: One aspect is a method that includes analyzing, by a processor of an analysis system, an instruction set architecture of a targeted complex-instruction set computer (CISC) processor to generate an instruction set profile for each CISC architectural instruction variant of the instruction set architecture. A combination of instruction sequences for the targeted CISC processor is determined from the instruction set profile that corresponds to a desired stressmark type. The desired stressmark type defines a metric representative of functionality of interest of the targeted CISC processor. Performance of the targeted CISC processor is monitored with respect to the desired stressmark type while executing each of the instruction sequences. One of the instruction sequences is identified as most closely aligning with the desired stressmark type based on performance results of execution of the instruction sequences with respect to the desired stressmark type.

Abstract: A method for automatically scaling estimates of digital power consumed by a portion of an integrated circuit (IC) device by the operating frequency of the portion of the IC are described herein. The method may include obtaining an energy value which may correspond to an amount of energy used by the portion of the IC. A cumulative energy value may be generated by repeatedly, at a frequency proportional to the operating frequency of the portion of the IC, obtaining energy values and adding each obtained energy value to a sum of energy values for the portion of the IC. The cumulative energy value may be sampled at a time sample interval to generate an estimate of the portion of the IC's digital power consumption that is automatically scaled with the operating frequency of the portion of the IC.

Abstract: The present invention discloses a solution for adding a profiling agent to a virtual machine (VM), which permits unit test programs to access information relating to memory and performance from runtime data areas of the VM. Operations permitted by the agent can include starting/stopping VM monitor, getting objects from the heap, retrieving an invocation count, determining a size of an instantiated object, getting a current thread time, and the like. Memory and performance information gathered during a test can be stored for later analysis under a test version identifier. A comparison engine can create reports that use the stored performance and memory data, which can help developers compare memory/performance deltas among different unit versions. In one embodiment, the VM can be a JAVA VIRTUAL MACHINE (JVM) and the unit test programs can be JUNIT programs.

Abstract: Example apparatus and methods monitor conditions in an object storage system. The conditions monitored may include a load balance measure in the system, a capacity balance measure in the system, a fault tolerance measure in the system, or a usage pattern measure in the system. A distribution plan or redistribution plan for storing or moving erasure codes in the object storage system may be determined based on the conditions. The distribution plan or the redistribution plan for the erasure codes may be updated dynamically in response to changing conditions in the object storage system. The distribution or redistribution may depend on a weighted combination of the load balance measure, the capacity balance measure, the fault tolerance measure, or the usage pattern measure so that responding to one sub-optimal condition (e.g., load imbalance) does not create a different sub-optimal condition (e.g., unacceptable fault tolerance).

Abstract: One or more expressions are evaluated that represent one or more characteristics of a dataflow graph that includes vertices representing data processing components connected by links representing flows of work elements between the components. A request is received by a computing system to evaluate the one or more expressions that include one or more operations on one or more variables; and the one or more expressions are evaluated by the computing system. The evaluating includes: defining a data structure that includes one or more fields, collecting, during execution of the dataflow graph, tracking information associated with one or more components of the dataflow graph, storing values associated with the tracking information in the one or more fields, and replacing one or more variables of the one or more expressions with the values stored in the one or more fields to compute a result of evaluating the one or more expressions.

Abstract: A cloud computing environment consists of a cloud deployment platform and a cloud management server configured to manage a plurality of virtual machines deployed in a cloud infrastructure. When a request to deploy an application to the cloud infrastructure is received by the cloud deployment platform, application deployment errors are monitored and tracked. A unique identifier is generated for each virtual machine, and requests to instantiate the virtual machines in the cloud infrastructure are then transmitted. A log containing error records that identify the occurrence of deployment errors is monitored based on the generated virtual machine identifiers, where the deployment errors are detected by the cloud deployment platform or the cloud management server. Based on the monitoring, error messages are generated by the cloud deployment platform.

Abstract: A method and apparatus of simulating performance characteristics of a virtual machine are disclosed. An example method may include selecting and inserting a virtual machine into a business application service group that includes a plurality of enterprise network devices, initiating a simulation sequence for a predetermined amount of time, recording results of the simulation sequence, and storing the results in memory.

Abstract: An analysis management system (AMS) is described that analyzes the in-field behavior of a program resource installed on a collection of computing devices, such as mobile telephone devices or the like. In operation, the AMS can instruct different devices to collect data regarding different observation points associated with the program resource, thus spreading the reporting load among the devices. Based on the data that is collected, the AMS can update a dependency graph that describes dependencies among the observation points associated with the program resource. The AMS can then generate new directives based on the updated dependency graph. The AMS can also use the dependency graph and the collected data to infer information regarding observation points that is not directly supplied by the collected data.

Abstract: An engineering tool includes a program display/editing unit that edits an official program to be run as an actual product and a debugging program to be used at the time of operation confirmation of the official program distinctively in such a manner that the debugging program is executed by a controller when the debugging program is selected and that the official program is executed by the controller without the debugging program being executed when the debugging program is not selected.

Abstract: Described herein are means for debugging byte code in an on-demand service environment system including a system for simulating execution debug in a multi-tenant database environment. Such means may include: receiving a request at a web-server of the system, determining one or more trace preferences are active for the request, sending the request to a logging framework communicatively interfaced to the multi-tenant database implementation, processing the request via the logging framework, and capturing at least a portion of the execution data emitted responsive to execution of the plurality of events for use in simulating execution debug of the events. Other related embodiments are additionally described.

Abstract: A debugging module determines by analysis of code build information of a system with an identified error, where to set a debug entry point at which to start execution of the system during a program subset debug session. Debug entry point metadata for the program subset debug session is captured in association with a subsequent execution of the system. The captured debug entry point metadata includes an initial file state of at least one file accessed by the system, any file inputs and file outputs (I/Os) detected as being performed by the system during the subsequent execution of the system up to the debug entry point, and an image of all instantiated objects at the debug entry point.

Abstract: A web application intended to be called by a cloud service is debugged locally in a developer's machine. A debugging session is configured to initiate execution of the web application in its intended cloud context by utilizing a reverse proxy mechanism to forward network traffic from a calling cloud service to the developer's machine. In a first embodiment, an integrated development environment (IDE) is able to establish a connection with the reverse proxy mechanism during the debugging session. In a second embodiment, a separate process is used to establish the connection with the reverse proxy mechanism where the separate process is outside of the IDE.

Abstract: A device receives code generated via a technical computing environment (TCE), the code including a value to be tested, and receives a value modifier, a test case, and a constraint. The value modifier customizes a manner in which the value of the code is presented to the constraint for verification. The device also generates a test based on the value modifier, the test case, and the constraint, performs the test on the value of the code to generate a result, and outputs or stores the result.

Abstract: A system, method, and computer program product are provided for automated exploratory testing. In use, a plurality of actions to be performed as a test flow in an exploratory test associated with at least one testing project are identified. Additionally, a plurality of additional options are identified for each performed action of the plurality of actions of the test flow that are capable of being performed instead of one or more of the plurality of actions in the test flow. Further, a graph is generated showing all combinations of the plurality of first actions and the plurality of additional options as a possible scope of the exploratory test associated with the at least one testing project. In addition, the graph is modified based on received input, the received input identifying one or more test flows to execute as the exploratory test associated with the at least one testing project.

Abstract: A method for application testing recommendation includes deploying a software application to first testers having first system configurations, and receiving testing coverage data describing (i) a first subset of features of the software application being tested by the first testers and (ii) information describing the first system configurations. The method further includes deploying the software application to a marketplace, and receiving market coverage data describing (i) a second subset of features being used by market users and (ii) second system configurations of the market users. The method further includes comparing the market coverage data and the testing coverage data to identify a coverage discrepancy, selecting second testers to test the software application based on the coverage discrepancy, and deploying the software application to the second testers.

Abstract: The technology disclosed enables understanding the user experience of accessing a web page under high loads. A testing system generates a simulated load by retrieving and loading a single web object. A performance snapshot is taken of accessing an entire web page from the server under load. The performance snapshot may be performed by emulating a browser accessing a web page's URL, the web page comprising multiple objects that are independently retrieved and loaded. The simulated load is configured with a number of users per region of the world where the user load will originate, and a single object from the web page to retrieve. Performance data such as response time for the single object retrieved, number of hits per second, number of timeouts per sec, and errors per second may be recorded and reported. An optimal number of users may be determined to achieve a target user experience goal.

Abstract: A method of testing a software application may include receiving a business process model of a software application, the business process model comprising representations of elements of the software application and labels for the elements of the software application. The method may further include generating a plurality of test cases according to the business process model, each test case comprising respective links between one or items of test data and the labels for the elements of the software application, and executing the test cases to test the software application. The method may further include prioritizing and generating pre-conditions for test cases. The method may be embodied in an article of manufacture, such as a non-transitory computer-readable medium storing instructions.

Abstract: Methods and systems for implementing improved partitioning and virtualization in a multi-host environment are provided. According to one embodiment, multiple devices, including CPUs and peripherals, coupled with a system via an interconnect matrix/bus are associated with a shared memory logically partitioned into multiple domains. A first domain is associated with a first set of the devices and a second domain is associated with a second set of the devices. A single shared virtual map module (VMM), maps a memory access request to an appropriate partitioned domain of the memory to which the originating device has been assigned based on an identifier associated with the device and further based on they type of memory access. The VMM causes a memory controller to perform memory access on behalf of the device by outputting a physical address based on the identified domain and the virtual address specified by the request.

Abstract: Metadata that corresponds to application data is distributed across different disruption regions of an asymmetric memory component such that metadata is written in the same disruption region as the application data to which it corresponds. A first block of application data is written to a first disruption region and a second block of application data is written to a second disruption region. A first block of metadata corresponding to the first block of application data and a second block of metadata corresponding to the second block of application data both are generated. The first block of metadata is written to the first disruption region and the second block of metadata is written to the second disruption region such that the first and second blocks of metadata are written to the same disruption regions as the blocks of application data to which they correspond.

Abstract: A memory system or flash card may include an algorithm or process for managing the handling of large tables in memory. A delta may be used for each table to accumulate updates. There may be a plurality of deltas for a multi-level delta structure. In one example, the first level delta is stored in random access memory (RAM), while the other level deltas are stored in the flash memory. Multiple-level deltas may improve the number of flash writes and reduce the number and amount of each flush to the actual table in flash. The use of multi-level deltas may improve performance by more efficiently writing to the table in flash.

Abstract: This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage.

Abstract: A storage drive including a first and second memories and a controller. The second memory has a write cycle lifetime that is less than a write cycle lifetime of the first memory. Each of the first and second memories includes solid-state memory. The controller: determines a write frequency for a first logical address; and based on the write frequency, determines a write frequency ranking for the first logical address. The write frequency ranking is based on a weighted time-decay average of write counts or an average of elapsed times of write cycles. The controller also: determines whether the write frequency ranking is greater than a lowest write frequency ranking of logical addresses of the first memory; and if the write frequency ranking of the first logical address is greater, maps the logical address with the lowest write frequency ranking in the first memory to the second memory.

Abstract: A processing device identifies a plurality of solid state storage devices arranged in an array and determines, for at least one solid state storage device of the plurality of solid state storage devices, a first time window during which the at least one solid state storage device is permitted to perform one or more garbage collection operations. The processing device then sends, to the at least one solid state storage device, a message comprising the first time window allocated to the at least one storage device, wherein the at least one solid state storage device is to perform the garbage collection operations during the first time window allocated to the at least one solid state storage device.

Abstract: Techniques are provided for minimizing latency due to garbage collection in a distributed system. Time data is stored at a computing device. The time data indicates when each of multiple computing nodes (e.g., servers) in the distributed system might be performing (or is scheduled to perform) a garbage collection operation. The computing device receives a first request and, in response, determines, based on the time data, one or more computing nodes to process a second (e.g., related) request, which may contain identical content as in the first request. The second request is sent to the one or more computing nodes.

Abstract: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.

Abstract: First and second data representation are stored in first and second blocks of a non-volatile, solid-state memory. The first and second blocks share series-connected bit lines. The first and second blocks are selected and other blocks of the non-volatile, solid-state memory that share the bit lines are deselected. The bit lines are read to determine a combination of the first and second data representations. The combination may include a union or an intersection.

Abstract: A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.

Abstract: A storage device includes a first nonvolatile memory that includes memory cells, each capable of storing data of a first number of bits, a second nonvolatile memory of which memory capacity is larger than a memory capacity of the first nonvolatile memory, and a memory controller is configured to control the first nonvolatile memory to store data of a second number of bits that is smaller than the first number in each of at least a part of the memory cells according to a usage amount of the memory cells.

Abstract: During runtime of a system, a memory controller is caused to relinquish control of a memory module that includes a volatile memory and a non-volatile memory. After the triggering, an indication is activated to the memory module, the indication causing a backup operation in the memory module, the backup operation being controlled by an internal controller in the memory module, and the backup operation involving a transfer of data from the volatile memory to the non-volatile memory in the memory module.

Abstract: A method of caching data in the memory of electronic processor units including compiling, in a first processor configured to perform data-parallel computation, a set of asymmetric coherent caching rules. The set of rules configure the first processor to be: inoperable to cache, in a second level memory cache of the first electronic processor unit, data whose home location is in a final memory store of a second electronic processor unit; operable to cache, in the second level memory cache of the first electronic processor unit, the data whose home location is in a final memory store of the first electronic processor unit; and operable to cache, in a first level memory cache of the first electronic processor unit, the data, regardless of a home location of the data.

Abstract: A computer system comprising multiple nodes, each node comprising a plurality of processors and a local cache hierarchy, suppresses local cache coherency of a node operations or global cache coherency operations between nodes based on the coherency request being a global or local request, and the state of the cache line at the node.

Abstract: A method to monitor the behavior of a working set cache of a full data set at run time and determine whether it provides a performance benefit is disclosed. An effectiveness metric of the working set cache is tracked over a period of time by efficiently computing the amount of physical memory consumption the cache saves and comparing this to a straightforward measure of its overhead. If the effectiveness metric is determined to be on an ineffective side of a selected threshold amount, the working set cache is disabled. The working set cache can be re-enabled in response to a predetermined event.

Abstract: An interconnect and method of managing a snoop filter within such an interconnect are provided. The interconnect is used to connect a plurality of devices, including a plurality of master devices where one or more of the master devices has an associated cache storage. The interconnect comprises coherency control circuitry to perform coherency control operations for data access transactions received by the interconnect from the master devices. In performing those operations, the coherency control circuitry has access to snoop filter circuitry that maintains address-dependent caching indication data, and is responsive to a data access transaction specifying a target address to produce snoop control data providing an indication of which master devices have cached data for the target address in their associated cache storage.

Abstract: A grace period detection technique for a preemptible read-copy update (RCU) implementation that uses a combining tree for quiescent state tracking. When a leaf level bitmask indicating online/offline CPUs is fully cleared due to all of its assigned CPUs going offline as a result of hotplugging operations, the bitmask state is not immediately propagated to the root level of the combining tree as in prior art RCU implementations. Instead, propagation is deferred until all tasks are removed from an associated leaf level task list tracking tasks that were preempted inside an RCU read-side critical section. Deferring bitmask propagation obviates the need to migrate the task list to the combining tree root level in order to prevent premature grace period termination. The task list can remain at the leaf level. In this way, CPU hotplugging is accommodated while avoiding excessive degradation of real-time latency stemming from the now-eliminated task list migration.

Abstract: Preventing request conflicts within microprocessors and/or computer systems. More particularly, embodiments of the invention relate to a technique to manage request conflicts within a processor and/or computer system in which a number of accesses may be made to a particular cache or group of caches shared amongst a set of cores or processors or agents.

Abstract: According to one aspect of the present disclosure, a method and technique for performance-driven cache line memory access is disclosed. The method includes: receiving, by a memory controller of a data processing system, a request for a cache line; dividing the request into a plurality of cache subline requests, wherein at least one of the cache subline requests comprises a high priority data request and at least one of the cache subline requests comprises a low priority data request; servicing the high priority data request; and delaying servicing of the low priority data request until a low priority condition has been satisfied.

Abstract: Systems and methods are provided herein for efficient local caching of data tiered to cloud storage to help reduce the bandwidth cost of repeated reads and writes to the same region of a stubbed file, increase the performance of write operations, and increase performance of read operations to portions of a stubbed file accessed repeatedly. When operations are directed toward data tiered to the cloud, the data can be read from cloud storage and stored within a local cache. A cache tracking tree can be generated and used to track file regions of a stub file, cached states associated with regions of the stub file, a set of cache flags, and other file and mapping data. For example, the cache state of regions of a stub file can be tracked including a cached data state, a non-cached state, a modified state, or a truncated state.

Abstract: A method and system to perform stream buffer management instructions in a processor. The stream buffer management instructions facilitate the creation and usage of a dedicated memory space or stream buffer of the processor in one embodiment of the invention. The dedicated memory space is a contiguous memory space and has a sequential or linear addressing scheme in one embodiment of the invention. The processor has logic to execute a stream buffer management instruction to copy data from a source memory address to a destination memory address that is specified with a desired level of memory hierarchy.

Abstract: Systems and methods presented herein provide for region lock management in an expander. In one embodiment, an expander, being operable to link a plurality of initiators to a plurality of Redundant Array of Independent Disks logical volumes, includes a plurality of physical transceivers, each being operable to link the logical volumes to the initiators, and a region lock manager operable to receive a request from a first of the initiators to lock a region of the logical volumes for an input/output operation by the first initiator. The region lock manager is also operable to determine if the requested region is unlocked, to lock the requested region from the remaining initiators to allow the input/output operation of the first initiator after determining the requested region is unlocked, and to unlock the requested region after the input/output operation of the first initiator is complete.

Abstract: Embodiments of methods to communicate a timestamp to a storage system are generally described herein. Other embodiments may be described and claimed.

Abstract: A non-blocking texture cache memory for a texture mapping pipeline and an operation method of the non-blocking texture cache memory may include: a retry buffer configured to temporarily store result data according to a hit pipeline or a miss pipeline; a retry buffer lookup unit configured to look up the retry buffer in response to a texture request transferred from a processor; a verification unit configured to verify whether result data corresponding to the texture request is stored in the retry buffer as the lookup result; and an output control unit configured to output the stored result data to the processor when the result data corresponding to the texture request is stored as the verification result.

Abstract: An apparatus and method are described for distributed snoop filtering. For example, one embodiment of a processor comprises: a plurality of cores to execute instructions and process data; first snoop logic to track a first plurality of cache lines stored in a mid-level cache (“MLC”) accessible by one or more of the cores, the first snoop logic to allocate entries for cache lines stored in the MLC and to deallocate entries for cache lines evicted from the MLC, wherein at least some of the cache lines evicted from the MLC are retained in a level 1 (L1) cache; and second snoop logic to track a second plurality of cache lines stored in a non-inclusive last level cache (NI LLC), the second snoop logic to allocate entries in the NI LLC for cache lines evicted from the MLC and to deallocate entries for cache lines stored in the MLC, wherein the second snoop logic is to store and maintain a first set of core valid bits to identify cores containing copies of the cache lines stored in the NI LLC.

Abstract: A processor may support a two-dimensional (2-D) gather instruction and a 2-D cache. The processor may perform the 2-D gather instruction to access one or more sub-blocks of data from a 2-D image stored in a memory coupled to the processor. The 2-D cache may store the sub-blocks of data in a multiple cache lines. Further, the 2-D cache may support access of more than one cache lines while preserving a 2-D structure of the 2-D image.

Abstract: An apparatus including a plurality of cores and a fuse array. The plurality of cores is disposed on a die. The fuse array is disposed on the die and is coupled to each of the plurality of cores, where the fuse array includes a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The first plurality of semiconductor fuses is programmed with compressed configuration data for the each of the plurality of cores. The second plurality of semiconductor fuses is programmed with core designation data that associates some of the compressed configuration data with one of the plurality of cores, where the one of the plurality of cores accesses and decompresses the some of the compressed configuration data upon power-up/reset, for initialization of elements within the one of the plurality of cores.

Abstract: An apparatus is contemplated for storing and providing configuration data to an integrated circuit device, the apparatus has a fuse array and a plurality of cores. The fuse array is disposed on a die. The fuse array has a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the fuse array. The each of the plurality of cores includes array control, configured to access the first and second pluralities of fuses, and configured to process first states of the first plurality of semiconductor fuses and second states of the second plurality of semiconductor fuses according to contents of a configuration data register.

Abstract: Techniques are described for compressing cache pages from an LRU (Least-Recently-Used) queue so that data takes longer to age off and be removed from the cache. This increases the likelihood that data will be available within the cache upon subsequent re-access, reducing the need for costly disk accesses due to cache misses.

Abstract: A processor includes translation-lookaside buffer (TLB) and a mapping module. The TLB includes a plurality of entries, wherein each entry of the plurality of entries is configured to hold an address translation and a valid bit vector, wherein each bit of the valid bit vector indicates, for a respective address translation context, the address translation is valid if set and invalid if clear. The TLB also includes an invalidation bit vector having bits corresponding to the bits of the valid bit vector of the plurality of entries, wherein a set bit of the invalidation bit vector indicates to simultaneously clear the corresponding bit of the valid bit vector of each entry of the plurality of entries. The mapping module generates the invalidation bit vector.