Abstract: Methods and systems are presented for evicting or copying-forward blocks in a storage system during garbage collection. In one method, a block status is maintained in a first memory to identify if the block is active or inactive, blocks being stored in segments that are configured to be cacheable in a second memory, a read-cache memory. Whenever an operation on a block is detected making the block inactive in one volume, the system determines if the block is still active in any volume, the block being cached in a first segment in the second memory. When the system detects that the first segment is being evicted from the second memory, the system re-caches the block into a second segment in the second memory if the block status of the block is active and the frequency of access to the block is above a predetermined value.

Abstract: Method and apparatus to efficiently manage data in caches. Data in caches may be managed based on priorities assigned to the data. Data may be requested by a process using a virtual address of the data. The requested data may be assigned a priority by a component in a computer system called an address range priority assigner (ARP). The ARP may assign a particular priority to the requested data if the virtual address of the requested data is within a particular range of virtual addresses. The particular priority assigned may be high priority and the particular range of virtual addresses may be smaller than a cache's capacity.

Abstract: According to embodiments of the present disclosure, a method for invalidating an address translation entry in an effective address to real address translation table (ERAT) for a computer memory can include receiving a first invalidation request. According to some embodiments, the method may also include determining that a first entry in the ERAT corresponds with the first invalidation request, wherein the ERAT has a plurality of entries, each entry in the plurality of entries having an indicator. In particular embodiments, the method may then determine that a first indicator associated with the first entry indicates that the first entry is not being used by any of a plurality of memory access entities (MAE), wherein a first MAE can concurrently use a same entry as a second MAE. The first entry may then be invalidated in response to determining that the first entry is not being used.

Abstract: A computer-implemented method for protecting a translation lookaside buffer (TLB) from TLB pollution includes receiving, via a processor, a virtual address for a data portion, determining, via the processor, whether the virtual address has a classification of memory cache transiency, creating, via the processor, a TLB entry in a first TLB, wherein the TLB entry omits a most recently used (MRU) classification, and installing the TLB entry in a next available LRU position.

Abstract: A system and method for efficiently maintaining metadata stored among a plurality of solid-state storage devices. A data storage subsystem supports multiple mapping tables. Records within a mapping table are arranged in multiple levels. Each level stores at least pairs of a key value and a physical pointer value. The levels are sorted by time. New records are inserted in a created new highest (youngest) level. No edits are performed in-place. A data storage controller determines both a cost of searching a given table exceeds a threshold and an amount of memory used to flatten levels exceeds a threshold. In response, the controller incrementally flattens selected levels within the table based on key ranges. After flattening the records in the selected levels within the key range, the records may be removed from the selected levels. The process repeats with another different key range.

Abstract: A method for writing data objects, the method may include accumulating, in a first memory module, multiple new data entities in one or more dirty pages of a data layer; wherein each new data entity and a corresponding older data entity are associated with a same application object; wherein the accumulating comprises storing each new data entity in a page that differs from a page that stores the corresponding older data entity; calculating multiple new sets of descriptors by generating to each new data entity, a new set of descriptors; wherein each set of descriptors comprises descriptors that belong to multiple descriptors layers; wherein the multiple descriptors layers and the data layer belong to an hierarchical data structure; accumulating the multiple new sets of descriptors in one or more dirty pages of one or more descriptors layers; wherein each corresponding older data entity is associated with a corresponding set of descriptors; wherein the accumulating comprises storing each new set of descriptor in

Abstract: Embodiments of the present invention disclose a method and apparatus of cache management for a non-volatile storage device. The method embodiment includes: determining a size relationship between a capacity sum of a clean page subpool and a dirty page subpool and a cache capacity; determining, when the capacity sum is equal to the cache capacity, whether identification information of a to-be-accessed page is in a history list of clean pages or a history list of dirty pages; and when it is determined that the identification information of the to-be-accessed page is in the history list of clean pages, adding a first adjustment value to a clean page subpool capacity threshold; and when the identification information of the to-be-accessed page is in the history list of dirty pages, subtracting a second adjustment value from the clean page subpool capacity threshold.

Abstract: A set-associative cache memory includes a plurality of congruence classes each including multiple entries for storing cache lines of data. A respective one of a plurality of counters is maintained for each cache line stored in the multiple entries. In response to a memory access request, the cache memory selects a victim cache line stored in a particular entry of a particular congruence class for eviction from the cache memory by reference to at least a counter value of the victim cache line. The cache memory also receives a new cache line of data for insertion into the particular entry and an indication of a coherence state of the new cache line at a data source from which the cache memory received the new cache line. The cache memory installs the new cache line in the particular entry and sets an initial counter value of the counter for the new cache line based on the received indication of the coherence state at the data source.

Abstract: A set-associative cache memory includes a plurality of congruence classes each including multiple entries for storing cache lines of data. A respective one of a plurality of counters is maintained for each cache line stored in the multiple entries. In response to a memory access request, the cache memory selects a victim cache line stored in a particular entry of a particular congruence class for eviction from the cache memory by reference to at least a counter value of the victim cache line. The cache memory also receives a new cache line of data for insertion into the particular entry and an indication of a distance from the cache memory to a data source from which the cache memory received the new cache line. The cache memory installs the new cache line in the particular entry and sets an initial counter value of the counter for the new cache line based on the received indication of the distance.

Abstract: A method of operation of a self-locking mass storage system includes: providing storage media and an inactivity timer; timing a period of read/write inactivity of the storage media using the inactivity timer; comparing the period of read/write inactivity against a preset maximum idle time; locking access to the storage media when the period of read/write inactivity exceeds the preset maximum idle time; and, resetting the period of read/write inactivity following read/write activity while the self-locking mass-storage system is in an unlocked state.

Abstract: Data storage systems are disclosed for automatically generating encryption rules based on a set of training files that are known to include sensitive information. The system may use a number of heuristic algorithms to generate one or more encryption rules for determining whether a file includes sensitive information. Further, the system may apply the heuristic algorithms to the content of the files, as determined by using natural language processing algorithms, to generate the encryption rules. Moreover, systems are disclosed that are capable of automatically determining whether to encrypt a file based on the generated encryption rules. The content of the file may be determined using natural language processing algorithms and then the encryption rules may be applied to the content of the file to determine whether to encrypt the file.

Abstract: Techniques for implementing a log-based storage scheme upon data storage devices are described herein. A data storage device is initialized by writing an identifying record. For each portion of data to be written to the drive, a first record including information regarding the anticipated nature of the portion of data is written prior to the data. The data is then written as a second record that includes at least the raw data as well as integrity verification information. A third record is stored following the second record, and includes an accounting and/or index of the data successfully written in the second record. On sequentially written devices, the information in the first stored record may be used to locate the third record, which in turn may be used to record data in the second record as well as the location of a first record of another portion of data.

Abstract: Apparatuses and methods for providing data to a configurable storage area are disclosed herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.

Abstract: Methods and systems for a device interfacing with a computing system are provided. The device is configured to send an input/output status block (IOSB) and an interrupt message to the processor of a computing system interfacing upon completion of an operation. The device generates the interrupt message while the IOSB is waiting to be transmitted; and transmits the IOSB to the processor, followed by the interrupt message, using a same data path for both the IOSB and the interrupt message. Furthermore, the device is configured to detect a request from the processor of the computing system interfacing to clear an interrupt status maintained by the device at a hardware location; send a message to the processor to de-assert the interrupt status and in parallel, clear the hardware location to clear the interrupt status such that the computing system can transfer information to the device for a next operation.

Abstract: Disclosed herein is a peripheral equipment control device controlling data flow via a peripheral equipment, the peripheral equipment control device including: a peripheral equipment control processor that can control an operation of one or more peripheral equipment; and a bus adapted to connect the peripheral equipment control processor, a main processor, and the one or more peripheral equipment, the main processor being provided outside the peripheral equipment control device to control the operation of the one or more peripheral equipment, in which the bus stores addresses that are referenced by the main processor and the peripheral equipment control processor to access the one or more peripheral equipment, and the bus prohibits access to the peripheral equipment by the peripheral equipment control processor while the main processor is active.

Abstract: The disclosure includes a system and method for optimizing a bus to log sensor data. The system includes a processor and a memory storing instructions that, when executed by the processor, cause the system to: estimate a use case of a journey of a mobile device; retrieve a set of sensor configuration parameters associated with the estimated use case; and configure one or more sensors according to the set of sensor configuration parameters to operate during at least a portion of the journey according to the set of sensor configuration parameters.

Abstract: In an embedded system, there are a plurality of data requesting devices, a plurality of data sources and a bus fabric interconnecting the data requesting devices and the data sources, wherein the bus fabric comprises a plurality of bus components. Some or all of the data sources and arbitration devices associated with the bus components resolve contentions between data bursts by selecting a first one of the contending data bursts; determining a length of a critical section of the first selected data burst; and processing the critical section of the selected data burst. Then, a second one of the contending data bursts is selected, a length of a critical section of the second selected data burst is determined, and the critical section of the second selected data burst is processed before a non-critical section of the selected data burst.

Abstract: A bridge for coupling a requesting interconnect and a serving interconnect connected to a number of coherent units in a computer system includes a first interface configured to receive a read request and a number of dependent write requests that the read request depends on from the requesting interconnect; and an issuer configured to issue the received number of dependent write requests to the serving interconnect and for issuing the received read request to the serving interconnect after issuing the number of dependent write requests and before receiving write acknowledgments for the issued dependent write requests from the serving interconnect.

Abstract: A First Come First Server (FCFS) arbiter that receives a request to utilize a shared resource from a plurality of devices and in response generates a grant value indicating if the request is granted. The FCFS arbiter includes a circuit and a storage device. The circuit receives a first request and a grant enable during a first clock cycle and outputs a grant value. The grant enable is received from a shared resource. The grant value communicated to the source of the first request. The storage device includes a plurality of request buckets. The first request is stored in a first request bucket when the first request is not granted during the first clock cycle and is moved from the first request bucket to a second request bucket when the first request is not granted during a second clock cycle. A granted request is cleared from all request buckets.

Abstract: Each processor of a plurality of processors is configured to execute an interrupt message instruction. A message filtering unit includes storage circuitry configured to store captured identifier information from each processor. In response to a processor of the plurality of processors executing an interrupt message instruction, the processor is configured to provide a message type and a message payload to the message filtering unit. The message filtering unit is configured to use the captured identifier information to determine a recipient processor indicated by the message payload and, in response thereto, provides an interrupt request indicated by the message type to the recipient processor.

Abstract: A diagnostic testing utility is used to perform online path diagnostic tests to troubleshoot components in a path that contribute to performance degradations and check application level data integrity, while traffic is allowed to flow as normal. To perform the diagnostic tests, two HBA or CNA ports at each end of a path are identified and used to send test frames to perform the diagnostic tests. The entire diagnostic procedure is performed without taking any ports or servers offline.

Abstract: A system and method for transferring data between a memory and peripheral units via a plurality of direct memory access (DMA) transactions, wherein a respective timestamp is assigned and/or appended to at least two of the plurality of the DMA transactions.

Abstract: A data storage system includes a storage server, including non-volatile memory (NVM) and a server network interface controller (NIC), which couples the storage server to a network. A host computer includes a host central processing unit (CPU), a host memory and a host NIC, which couples the host computer to the network. The host computer runs a driver program that is configured to receive, from processes running on the host computer, commands in accordance with a protocol defined for accessing local storage devices connected to a peripheral component interface bus of the host computer, and upon receiving a storage access command in accordance with the protocol, to initiate a remote direct memory access (RDMA) operation to be performed by the host and server NICs so as to execute on the storage server, via the network, a storage transaction specified by the command.

Abstract: An object of the present invention is to prevent occurrence of data destruction when a transfer source region and a transfer destination region of data overlap with each other and even when transfer is performed using a burst transfer function. The data read from the transfer source region is temporarily written into a ring buffer, and then the data written into the ring buffer is written into the transfer source region. In this case, reading of the data from the ring buffer is controlled, based on a magnitude relation between the number of times of wrap-arounds caused by writing of the data into the ring buffer and the number of times of wrap-arounds caused by reading of the data from the ring buffer.

Abstract: A method and system is disclosed for accessing I/O and memory devices utilizing a DMA controller. Each device may be connected to the DMA controller through an individual channel. Clocking circuitry in the DMA may allow the DMA controller to send signals to each device at a prescribed frequency. Furthermore, the DMA controller is capable of activating and deactivating a channel clock, used in sending signals to the devices, based on the operational status of the individual devices. The DMA controller is also capable of tuning the channel clock dependant on the capabilities of any active devices. In this manner, the amount of bandwidth used during a DMA data transfer can be tailored to the specific requirements of the devices involved with the data transfer.

Abstract: Communication systems and communication control methods are disclosed. In one example, a slave device belonging to a group of devices to which arbitration is applicable sequentially transmits a start bit and a first address including a first bit having a value different from a corresponding first bit of predetermined pattern data. A master device sequentially transmits the start bit and the predetermined pattern data. The master device arbitrates the master device and the first slave device based on the value of the first bit.

Abstract: The USB device remote control method in a remote control system including a first device connected with a terminal through USB and a second device connected with the first device via a network includes installing, at the first device, a USB driver of the terminal, providing, at the first device, a remote terminal control module to the terminal using the USB driver, transmitting, at the second device, a control command for controlling the terminal to the first device and providing, at the first device, the control command to the terminal using the USB driver, executing, at the remote terminal control module, a command corresponding to the received control command and capturing and providing a display image showing the execution result to the first device through the USB driver, transmitting, at the first device, the display image to the second device.

Abstract: Described embodiments process data packets received that include a source address and at least one destination address. If the destination address is stored in a memory of an I/O adapter, the received data packet is processed in accordance with bridging rules associated with each destination address stored in the I/O adapter memory. If the destination address is not stored in the I/O adapter memory, the I/O adapter sends a task message to a processor to determine whether the destination address is stored in an address table stored in a shared memory of the network processor. The I/O adapter memory has lower access latency than the address table. If the destination address is stored in the address table, the received data packet is processed in accordance with bridging rules stored in the address table and the bridging rules stored in the I/O adapter memory are updated.

Abstract: An interface conversion device and a wireless communication system including the interface conversion device are disclosed. The interface conversion device is connected to GPIB-equipped devices in a GPIB network to convert data in the GPIB format to the ZigBee format and vice versa, thereby transforming a cable network to a wireless network to increase the mobility, range, and number of devices in the network.

Abstract: Representative embodiments are disclosed for data transfer between field programmable gate arrays (FPGAs). A representative system includes: a PCIe communication network comprising a PCIe switch and a plurality of PCIe communication lines; a host computing system coupled to the PCIe communication network; a nonblocking crossbar switch; a plurality of memory circuits; and a plurality of field programmable gate arrays, each field programmable gate array configurable for a plurality of data transfers to and from the host computing system and any other field programmable gate array of the plurality of field programmable gate arrays, with each data transfer including a designation of a first memory address, a file size, and a stream number. Once base DMA registers have been initialized for a selected application, no further involvement by the host computing system is involved for the duration of the selected application.

Abstract: The present disclosure is directed to an input/output module.

Abstract: A method of performing an identical packet multicast packet ready command (common packet multicast mode operation) is described herein. A packet ready command is received from a first memory system via a bus and onto a network interface circuit. The packet ready command includes a multicast value. A communication mode is determined as a function of the multicast value. The multicast value indicates a single packet is to be communicated by the network interface circuit to a first number of destinations. A free packet command is output from the network interface circuit onto the bus. The free packet command includes a Free On Last Transfer (FOLT) value that indicates that the packet will not be freed from the first memory system by the network interface circuit once the packet is transmitted. The network interface circuit and the memory system are included on an Island-Based Network Flow Processor.

Abstract: A method of performing an unicast packet ready command (unicast mode operation) is described herein. A packet ready command is received from a memory system via a bus and onto a network interface circuit. The packet ready command includes a multicast value. A communication mode is determined as a function of the multicast value. The multicast value indicates a single packet is to be communicated to a single destination by the network interface circuit. A free packet command is outputted from the network interface circuit onto the bus. The free packet command includes a Free On Last Transfer (FOLT) value that indicates that the packet is to be freed from the memory system by the network interface circuit after the packet is communicated to the network interface circuit. The network interface circuit and the memory system are included on an Island-Based Network Flow Processor.

Abstract: An integrated circuit is provided. The integrated circuit includes a communication-mode determination circuitry configured to detect a signal level at one or both of a first data line and a second data line and to determine whether a communication mode of the first data line and the second data line is a first universal series bus (USB) communication mode or a second USB communication mode. The integrated circuit also includes a first transceiver circuitry configured to operate in one of multiple modes, based on the communication mode determined. The integrated circuit also includes a second transceiver circuitry configured to operate in one of multiple modes, based on the communication mode determined. A maximum signal level of the first USB communication mode is greater than a maximum signal level of the second USB communication mode.

Abstract: Various embodiments for managing assets in a data center device rack include: establishing a data connection between a cabinet level controller and at least one primary power distribution unit (PDU); using a first electrical outlet on the primary PDU to establish an electrical connection between the primary PDU an electrical asset in a data center equipment rack; using a first asset interface connector on the cabinet level controller to establish a data connection between the cabinet level controller and the electrical asset in the data center equipment rack, the first electrical outlet and the first asset interface connector being in horizontal alignment; using a router integrated into the cabinet level controller to connect the cabinet level controller to a wide area Internet Protocol (IP) network; and using the router to establish a single IP address corresponding to a plurality of electrical assets in the data center equipment rack.

Abstract: A system and methodology for effectively managing, without interrupting the overall system, the power and control logic of the system during the removal, insertion and programming of programmable components that control the logic. The system and methodology detect a removal of a first programmable component from its socket and switch at least one control signal from being driven by the first programmable component to being driven by the second programmable component. Upon detecting an insertion of the first programmable component into its socket, the system and methodology switch the at least one control signal from being driven by the second programmable component to being driven by the first programmable component.

Abstract: In a wireless docking system a dockee device (120) communicates with a host device (100) that is coupled to at least one peripheral (110, 111, 112). The host device has a host communication unit (102) and a docking processor (101) arranged for docking at least one dockee device. The dockee device has a dockee communication unit (121), and a dockee processor (122) for docking to the host device. The dockee processor is arranged for providing at least one virtual peripheral device in a virtual docking environment, the virtual peripheral device having a privacy level. When docking, the virtual peripherals are mapped on actual peripherals so as to apply the privacy level to the actual peripheral. When docked, data transfer with the actual peripheral is controlled according to the respective peripheral privacy level.

Abstract: Methods and apparatus, including computer program products, are provided for communications control in a dual row connector. In one aspect there is provided a method. The method may include coupling a first data connector including a pair of communication control pins and another pair of communication control pins, wherein the pair further comprises a first communication control pin located at a first row of the first data connector and a second communication control pin located at a second row of the data connector, wherein the other pair further comprises a third communication control pin located at the first row of the first data connector and a fourth communication control pin located at the second row of the first data connector. Related apparatus, systems, methods, and articles are also described.

Abstract: Methods and systems are described for emulating a bi-directional synchronous communications protocol for bi-directional bus communication using unidirectional channels between a master device and a slave device. The master device includes a physical interface to the unidirectional channels that resynchronizes outgoing and incoming data streams in order to reconstruct a bitstream that is compliant with the bi-directional synchronous communications protocol. The reconstructed bitstream is input to the master digital interface controller as though it had been received from the slave device.

Abstract: In one embodiment, a monolithic integrated circuit includes a first UART, a second UART, and a multiplexer. The first UART has a parallel IO interface to couple to a host system to transceive parallel data and a serial IO interface. The second UART has a parallel IO interface and a serial IO interface coupled to the serial IO interface of the first UART. The first and second UARTs convert parallel data into serial data and serial data into parallel data. The multiplexer has an output coupled to the serial input of the first UART, a first input coupled to the serial output of the second UART, a second input coupled to a serial input of a serial communication port, and a select input coupled to a control signal selectively coupling serial interfaces of first and second UARTs together for remote terminal services at a remote computer system over a network.

Abstract: Techniques are disclosed for peer-to-peer data transfers where a source device receives a request to read data words from a target device. The source device creates a first and second read command for reading a first portion and a second portion of a plurality of data words from the target device, respectively. The source device transmits the first read command to the target device, and, before a first read operation associated with the first read command is complete, transmits the second read command to the target device. The first and second portions of the plurality of data words are stored in a first and second portion a buffer memory, respectively. Advantageously, an arbitrary number of multiple read operations may be in progress at a given time without using multiple peer-to-peer memory buffers. Performance for large data block transfers is improved without consuming peer-to-peer memory buffers needed by other peer GPUs.

Abstract: Methods and apparatus for a pipelined architecture for storage lifecycles are disclosed. A method includes identifying, during a transition candidate discovery iteration, storage objects of a multi-tenant service for which respective lifecycle transitions are to be scheduled, including a particular storage object identified as being a candidate for a particular lifecycle transition. The method includes generating transition job objects, each job comprising respective indications of one or more of the storage objects identified during the discovery iteration. The method includes assigning, during a transition execution iteration, resources to initiate storage operations for the particular lifecycle transition, and initiating, using the assigned resources, storage operations for the particular lifecycle transition.

Abstract: A method for RDMA optimized high availability for in-memory storing of data includes receiving RDMA key-value store write requests in a network adapter of a primary computing server directed to writing data to an in-memory key-value store of the primary computing server and performing RDMA write operations of the data by the network adapter of the primary computing server responsive to the RDMA key-value store write requests. The method also includes replicating the RDMA key-value store write requests to a network adapter of a secondary computing server, by the network adapter of the primary computing server. Finally, the method includes providing address translation data for the in-memory key-value store of the primary computing server from the network adapter of the primary computing server to the network adapter of the secondary computing server.

Abstract: A method for RDMA optimized high availability for in-memory storing of data includes receiving RDMA key-value store write requests in a network adapter of a primary computing server directed to writing data to an in-memory key-value store of the primary computing server and performing RDMA write operations of the data by the network adapter of the primary computing server responsive to the RDMA key-value store write requests. The method also includes replicating the RDMA key-value store write requests to a network adapter of a secondary computing server, by the network adapter of the primary computing server. Finally, the method includes providing address translation data for the in-memory key-value store of the primary computing server from the network adapter of the primary computing server to the network adapter of the secondary computing server.

Abstract: Data exchange section 104 has a step of determining whether or not pairs of the transmission selecting conditions and reception selecting conditions satisfy a standard for exchanging, through a determined pair, data between a transmission user who corresponds to a transmission selecting condition in the determined pair and a reception user who corresponds to a reception selecting condition in the determined pair. Data exchange system 100 exchanges data satisfying both the transmission selecting condition and the reception selecting condition in the determined pair between the transmission user and the reception user, respectively corresponding to the transmission selecting condition and the reception selecting condition in the determined pair.

Abstract: A reconfigurable vector processor is described that allows the size of its vector units to be changed in order to process vectors of different sizes. The reconfigurable vector processor comprises a plurality of processor units. Each of the processor units comprises a control unit for decoding instructions and generating control signals, a scalar unit for processing instructions on scalar data, and a vector unit for processing instructions on vector data under control of control signals. The reconfigurable vector processor architecture also comprises a vector control selector for selectively providing control signals generated by one processor unit of the plurality of processor units to the vector unit of a different processor unit of the plurality of processor units.

Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

Abstract: Provided is a reconfigurable processor capable of reducing the routing processing time of routing nodes by driving the routing nodes at a greater frequency than a driving frequency of the processing elements. The reconfigurable processor includes one or more processing elements configured to be driven at a first driving frequency, and one or more routing nodes configured to be provided on paths that are formed between the processing elements, and to be driven at a second driving frequency that is greater than the first driving frequency.

Abstract: A calculation device for deriving solutions of a system of linear equations, which realizes a solution of the system of linear equations using an iterative method belonging to a Krylov subspace method, includes a plurality of arithmetic units. In the calculation device, a vector sequence xk (k is a natural number containing 0) approximating to the solutions of the system of linear equations is formed by a plurality of components in accordance with an order of the vector sequence xk, and when the vector sequence xk is divided into a plurality of different regions corresponding to the plurality of components and the respective arithmetic units are caused to execute arithmetic processings corresponding to the plurality of different regions in parallel in iterative computation of causing the vector sequence xk to approximate to the solutions, a preconditioned matrix that is used in the iterative computation is a diagonal matrix.

Abstract: Techniques for efficiently performing full and scaled transforms on data received via full and scaled interfaces, respectively, are described and comprise (1) performing a first transform on a block of first input values to obtain a block of first output values by scaling the block to obtain scaled input values, performing a scaled one-dimensional (1D) transform on each row of the block, and performing a scaled 1D transform on each column of the block; and (2) performing a second transform on a block of second input values to obtain a block of second output values by performing a scaled 1D transform on each row of the block, performing a scaled 1D transform on each column of the block, and scaling the block.